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* Add abstract "Reset" which can be inferred to AsyncReset or UInt<1>
* Enhance async reset initial value literal check to support aggregates
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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* Check mems for legal latencies; ban zero write latency.
* Trigger
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* Avoid redundancy between CheckChirrtl and CheckHighForm, add more checks
* Add test case for illegal Chirrtl memory in HighForm
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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- use scala.io.Source instead of io.Source
- .toList cleaner way to force stream to be read.
- clear old commented out code in ProtoBufSpec
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Fixes a threading bug in where lazy reading of file
caused a problem for multithreaded access to the that was read.
Changes all uses of io.Source to use new API
getText
getLines
getTextResource
getLinesResouce
Make style to only import FileUtils and not its methods
So code is more explicit as e.g. FileUtils.getText()
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* Allow name of blackbox resource .f file to change from static value
* Restore fileListName as a deprecated def per Jack's feedback
* Support both local and absolute paths for .f resource files
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This fixes a bug in the TopWiringTransform when wiring aggregates by
adding ExpandConnects to its list of fixup passes. TopWiringTransform
is MidForm => MidForm, but when wiring aggregates, it will output bulk
connects. This violates the MidForm prerequisite that ExpandConnects
has run. Symptomatically, this will manifest as match errors in
LowerTypes if a user tries to use the TopWiringTransform on
aggregates.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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* fix RenameMap chaining
* fix order of chaining, add another test case
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* Add SimplifyMems transform to lower memories without splitting
* Remove spurious anonymous function
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* check isLocal before removing target tokens in RenameMap
* add fix for Adam's test case, add more test cases
* fix multiple renaming bug
* call componentGet before checking underlying for ReferenceTargets in recursiveGet
* add ModuleGet that implements new instance rename order
* normalize target before renaming
* fix forall/exists bug
* add guards for isLocal cases
* fix circuit renaming, fix traverseHierarchy, add debug prints
* remove sensitivity stuff
* add more tests
* reapply parent path to renamed subpath, fix reference -> instance renames
* remove debug prints
* add instance as reference test case
* fix Ref->IsMod, IsMod->Ref renamed, fix extra test cases
* fix ofModule renaming for refs/instances
* fix renaming of ofModules, change tests
* fix more InstanceTarget rename bugs
* remove bad ReferenceTarget test case
* cleanup midRename of recursiveGet
* fix comments
* fix multiple ModuleTarget renames for InstanceTargets
* dis-allow renaming of ModuleTargets to References
* add back removed lines in RemoveCHIRRTL
* fix indents
* only add ofModule to refs if renaming an inst as a ref
* change .moduleOpt.get to .module
* disallow renaming ReferenceTarget->ModuleTarget
* disallow ref->mod renames in tests, add inst as ref test cases
* cache results of get functions
* fix bot/mid/top renames, add andThen
* fix andThen, add test case
* add more test cases, fix ++
* fix comments, make things private
* dont quit if earlier returns None, add dedup/inline rename tests
* don't rename OfModules to instances paths
* update dedup test
* don't treat references as instances, don't reapply parents to absolute paths
* fix more test cases
* short-circuit OfModule renames if an absolute path is found
* update andThen, remove orElse, deprecate ++
* removed commented code
* update comments
* respond to comments
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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This changes the Dependency API to specify dependencies in terms of
classes subtyping the DependencyAPI trait. Previously, this was
invariant which caused a bunch of ugly, unneeded .asInstanceOf jank.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Adds tests for the PhaseManager. This includes outputs in
"test_run_dir" of Graphviz output. This will automatically generate a
PNG if "dot" is on the path. Otherwise, it will just generate the
Graphviz output. This includes tests that check for determinism.
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* Add Test for AddDefaults phase
* Refactor AddDefaultsSpec
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Emit Verilog IntParams that fit in 32-bits as Integer literals
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* Added test to GroupComponentsSpec demonstrating bug
* Added bugfix to GroupComponents for invalid ports of grouped instances
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Abstracts away option writing such that users no longer have to
understand scopt semantics. This adds a ShellOption class and a
HasShellOptions trait for something which provides one or more
ShellOptions. This refactors the FIRRTL codebase to use this style of
option specification.
Adds and uses DeletedWrapper to automatically generate
DeletedAnnotations.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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- Add tests for DriverCompatibility.AddImplicitEmitter
- Add tests for DriverCompatibility.AddImplicitOutputFile
- Use a different top name in DriverSpec emit circuit tests for better
coverage
- Add tests for DriverCompatibility.WriteEmitted
- Add catchWrites firrtlTests utility to intercept file writes
- Add tests for WriteOutputAnnotations
- Add tests for --custom-transforms reversing
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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This adds FirrtlStage, a reimplementation of the original FIRRTL
Driver as a Stage. This updates the original firrtl.options package to
implement FirrtlStage (namely, TransformLike is added) along with
FirrtlMain. Finally, the original FIRRTL Driver is converted to a
compatibility wrapper around FirrtlStage.
For background, Stage and Phase form the basis of the Chisel/FIRRTL
Hardware Compiler Framework (HCF). A Phase is a class that performs a
mathematical transformation on an AnnotationSeq (in effect, a
generalization of a FIRRTL transform). Curtly, a Stage is a Phase that
also provides a user interface for generating annotations. By their
construction, Phases are designed to be composed sequentially into a
transformation pipeline.
This modifies the existing options package (which provides
Stage/Phase) to build out a type hierarchy around Stage/Phase. This
adds TransformLike[A] which implements a mathematical transformation
over some type A. Additionally, and as an interface between different
TransformLikes, this adds Translator[A, B] which extends
TransformLike[A], but does an internal transformation over type B.
This is used to interface Phases with the existing FIRRTL compiler.
This adds a runTransform method to Phase that, like
Transform.runTransform, will automatically detect deleted Annotations
and generate DeletedAnnotations.
The new FirrtlStage, a reimplementation of FIRRTL's Driver, is added
as a Stage composed of the following Phases:
1. AddDefaults - add default annotations
2. AddImplicitEmitter - adds an implicit emitter derived from the
compiler
3. Checks - sanity check the AnnotationSeq
4. AddCircuit - convert FIRRTL input files/sources to circuits
5. AddImplicitOutputFile - add a default output file
6. Compiler - run the FIRRTL compiler
7. WriteEmitted - write any emitted modules/circuits to files
The Driver is converted to a compatibility layer that replicates old
Driver behavior. This is implemented by first using new toAnnotation
methods for CommonOptions and FirrtlExecutionOptions that enable
AnnotationSeq generation. Second, the generated AnnotationSeq is
preprocessed and sent to FirrtlStage. The resulting Phase order is
then:
1. AddImplicitAnnotationFile - adds a default annotation file
2. AddImplicitFirrtlFile - adds a default FIRRTL file using top name
3. AddImplicitOutputFile - adds an output file from top name
4. AddImplicitEmitter - adds a default emitter derived from a
compiler and any split modules command line option
5. FirrtlStage - the aforementioned new FirrtlStage
Finally, the output AnnotationSeq is then viewed as a
FirrtlExecutionResult. This compatibility layer enables uninterrupted
usage of old Driver infrastructure, e.g., FirrtlExecutionOptions and
CommonOptions can still be mutated directly and used to run the
Driver.
This results in differing behavior between the new FirrtlStage and the
old Driver, specifically:
- FirrtlStage makes a clear delineation between a "compiler" and an
"emitter". These are defined using separate options. A compiler is
"-X/--compiler", while an emitter is one of "-E/--emit-circuit" or
"-e/--emit-modules".
- Related to the above, the "-fsm/--split-modules" has been removed
from the FirrtlStage. This option is confusing once an implicit
emitter is removed. It is also unclear how this should be handled
once the user can specify multiple emitters, e.g., which emitter
should "--split-modules" apply to?
- WriteOutputAnnotations will, by default, not write
DeletedAnnotations to the output file.
- The old top name ("-tn/--top-name") option has been removed from
FirrtlStage. This option is really a means to communicate what
input and output files are as opposed to anything associated with
the circuit name. This option is preserved for the Driver
compatibility layer.
Additionally, this changes existing transform scheduling to work for
emitters (which subclass Transform). Previously, one emitter was
explicitly scheduled at the end of all transforms for a given
compiler. Additional emitters could be added, but they would be
scheduled as transforms. This fixes this to rely on transform
scheduling for all emitters. In slightly more detail:
1. The explicit emitter is removed from Compiler.compile
2. An explicit emitter is added to Compiler.compileAndEmit
3. Compiler.mergeTransforms will schedule emitters as late as
possible, i.e., all emitters will occur after transforms that
output their input form.
4. All AddImplicitEmitter phases (DriverCompatibility and normal)
will add RunFirrtlTransformAnnotations to add implicit emitters
The FIRRTL fat jar utilities are changed to point at FirrtlStage and not
at the Driver. This has backwards incompatibility issues for users
that are using the utilities directly, e.g., Rocket Chip.
The Logger has been updated with methods for setting options based on
an AnnotationSeq. This migrates the Logger to use AnnotationSeq as
input parameters, e.g., for makeScope. Old-style methods are left in
place and deprecated. However, the Logger is not itself a Stage.
The options of Logger Annotations are included in the base Shell and
Stage is updated to wrap its Phases in a Logger scope.
Additionally, this changes any code that does option parsing to always
prepend an annotation as opposed to appending an annotation. This is
faster, but standardizing on this has implications for dealing with
the parallel compilation annotation ordering.
A Shell will now put the initial annotations first (in the order the
user specified) and then place all annotations generating from parsing
after that. This adds a test case to verify this behavior.
Discovered custom transforms (via `RunFirrtlTransformAnnotation`s) are
discovered by the compiler phase in a user-specified order, but are
stored in reverse order to more efficiently prepend (as opposed to
append) to a list. This now reverses the transform order before
execution to preserve backwards compatibility of custom transform
ordering.
The Compiler phase also generates one deleted annotation for each
`RunFirrtlTransformAnnotation`. These are also reversed.
Miscellaneous small changes:
- Split main method of Stage into StageMain class
- Only mix in HasScoptOptions into Annotation companion objects (h/t
@jackkoenig)
- Store Compiler in CompilerAnnotation
- CompilerNameAnnotation -> CompilerAnnotation
- Make Emitter abstract in outputSuffix (move out of FirrtlOptions)
- Add DriverCompatibility.AddImplicitOutputFile that will add an
output file annotation based on the presence of a
TopNameAnnotation. This is important for compatibility with the
old Driver.
- Cleanup Scaladoc
- Refactor CircuitOption to be abstract in "toCircuit" that converts
the option to a FirrtlCircuitAnnotation. This allows more of the
conversion steps to be moved out of AddCircuit and into the actual
annotation.
- Add WriteDeletedAnnotation to module WriteOutputAnnotations
- A method for accessing a FirrtlExecutionResultView is exposed in
FIRRTL's DriverCompatibilityLayer
- Using "--top-name/-tn" or "--split-modules/-fsm" with FirrtlStage
generates an error indicating that this option is no longer
supported
- Using FirrtlStage without at least one emitter will generate a
warning
- Use vals for emitter in Compiler subclasses (these are used to
build RunFirrtlTransformAnnotations and the object should be
stable for comparisons)
- Fixes to tests that use LowTransformSpec instead of
MiddleTransformSpec. (SimpleTransformSpec is dumb and won't
schedule transforms correctly. If you rely on an emitter, you need
to use the right transform spec to test your transform if you're
relying on an emitter.)
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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* Improve memoization for register const prop
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should be parsable without excepting (#1060)
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* Add serialization support for LoadMemoryFileType in LoadMemoryAnnotation
Add custom LoadMemoryFileTypeSerializer.
Add test to verify LoadMemoryAnnotation can be correctly serialized/deserialized.
* Simplify and focus LoadMemoryAnnotation serialization/deserialization.
Respond to comments on earlier implementations.
* Add type FileType definition for current chisel3 code.
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* Copy MemConf.scala from ucb-bar/barstools#35 into memlib.
This provides a data structure wrapper around the existing memory conf format
which contains both reading and writing methods, making it easier to write code
that needs to read the format.
* Add MemConf tests and use a Map[MemPort, Int] for port lists instead of a Seq[MemPort] which is a bit less fragile.
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* Don't create nodes to hold Muxes with >0 void cases
* Added test case demonstrating void error
* Memoize intermediate expression when checking for WVoid-ness
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* Add --nodedup option to facilitate FIRRTL to verilog regression testing.
* Short-circuit the DedupModules transform if NoCircuitDedupAnnotation exists.
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* Create a simple generic graphviz renderer for DiGraph
There are three basic kinds
- A simple default renderer
- A ranked renderer that places nodes in columns based on depth from sources
- A sub-graph render for graphs that contain a loop
- Renders just nodes that are part of first loop found
- Plus the neighbors of the loop
- Loop edges are shown in red.
* Create a simple generic graphviz renderer for DiGraph
- Moved the graph loop finder into DiGraph
- Fixed scala doc per Edward's comments
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* Run CheckHighForm after all non-emitter transforms in firrtl tests
* Remove shlw from checks.scala
* Removed mistake in fix
* Fix FirrtlSpec fix
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* refactor InferWidths to allow for extra contraints, add InferWidthsWithAnnos
* add test cases
* add ResolvedAnnotationPaths trait to InferWidthsWithAnnos
* remove println
* cleanup tests
* remove extraneous constraints
* use foreachStmt instead of mapStmt
* remove support for aggregates
* fold InferWidthsWithAnnos into InferWidths
* throw exception if ref not found, check for annos before AST walk
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Instead, just forward the exception
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(#1025)
* No time left for you - quickly rename deep bundles still occasionally fails.
Run the "quick" calibration test three times and choose the maximum as the basis for comparison with the "deep" test.
* Rename local variable to less confusing name.
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* Correctly handle dots in loaded memory paths
* Added test for loadmem filename
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UniquifySpec.quicklyrenamedeepbundles (#1000)
* Attempt to deal with timing vagaries in UniquifySpec.quicklyrenamedeepbundles
Switching to Scala 2.12.8 cause this test to start failing on OSX. Try earlier scheme to compare shallow vs deep to reduce brittleness.
* Address review concerns; update comment.
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Fixes #219
* Adds AsyncResetType (similar to ClockType)
* Registers with reset signal of type AsyncResetType are async reset
registers
* Registers with async reset can only be reset to literal values
* Add initialization logic for async reset registers
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This uses the foldShiftRight method of the ConstantPropagation
Transform when legalizing Shr PrimOps. This has the effect of removing
literals with bit extracts from the MinimumVerilogCompiler.
This makes the formerly private foldShiftRight method of a public
method of the ConstantPropagation companion object.
Tests in the MimimumVerilogCompilerSpec are updated to check that Shr
is handled as intended.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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This adds the RemoveValidIf Pass to the MinimumLowFirrtlOptimization
Transform. A test case is included to verify that `is invalid` is
properly converted to a connection to zero.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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This adds runs of the minimum Verilog compiler and SystemVerilog
compiler in DriverSpec.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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