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authorJohn Wright2019-03-19 11:08:07 -0700
committermergify[bot]2019-03-19 18:08:07 +0000
commitde20d4d7d0bb98430871d37e0a7c7c6612b44e0f (patch)
tree88c17fa924ae78d2faadfa6036c555529b1dd963 /src/test
parent9911b3467de2ebe92827ddc3288bd6db477cc636 (diff)
Designs with no SeqMems should produce empty MemConf strings, and this should be parsable without excepting (#1060)
Diffstat (limited to 'src/test')
-rw-r--r--src/test/scala/firrtlTests/ReplSeqMemTests.scala22
1 files changed, 22 insertions, 0 deletions
diff --git a/src/test/scala/firrtlTests/ReplSeqMemTests.scala b/src/test/scala/firrtlTests/ReplSeqMemTests.scala
index b51e2271..a1f27958 100644
--- a/src/test/scala/firrtlTests/ReplSeqMemTests.scala
+++ b/src/test/scala/firrtlTests/ReplSeqMemTests.scala
@@ -487,6 +487,28 @@ circuit CustomMemory :
checkMemConf(confLoc, mems)
(new java.io.File(confLoc)).delete()
}
+
+ "ReplSeqMem" should "produce an empty conf file with no SeqMems" in {
+ val input = """
+circuit NoMemsHere :
+ module NoMemsHere :
+ input clock : Clock
+ input in : UInt<8>
+ output out : UInt<8>
+
+ out is invalid
+
+ out <= in
+"""
+ val mems = Set.empty[MemConf]
+ val confLoc = "ReplSeqMemTests.confTEMP"
+ val annos = Seq(ReplSeqMemAnnotation.parse("-c:CustomMemory:-o:"+confLoc),
+ InferReadWriteAnnotation)
+ val res = compileAndEmit(CircuitState(parse(input), ChirrtlForm, annos))
+ // Check the emitted conf
+ checkMemConf(confLoc, mems)
+ (new java.io.File(confLoc)).delete()
+ }
}
// TODO: make more checks