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authorJohn Wright2019-03-19 11:08:07 -0700
committermergify[bot]2019-03-19 18:08:07 +0000
commitde20d4d7d0bb98430871d37e0a7c7c6612b44e0f (patch)
tree88c17fa924ae78d2faadfa6036c555529b1dd963 /src
parent9911b3467de2ebe92827ddc3288bd6db477cc636 (diff)
Designs with no SeqMems should produce empty MemConf strings, and this should be parsable without excepting (#1060)
Diffstat (limited to 'src')
-rw-r--r--src/main/scala/firrtl/passes/memlib/MemConf.scala5
-rw-r--r--src/test/scala/firrtlTests/ReplSeqMemTests.scala22
2 files changed, 25 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/passes/memlib/MemConf.scala b/src/main/scala/firrtl/passes/memlib/MemConf.scala
index 55600bf6..e53a5de7 100644
--- a/src/main/scala/firrtl/passes/memlib/MemConf.scala
+++ b/src/main/scala/firrtl/passes/memlib/MemConf.scala
@@ -51,9 +51,10 @@ object MemConf {
def fromString(s: String): Seq[MemConf] = {
s.split("\n").toSeq.map(_ match {
- case MemConf.regex(name, depth, width, ports, maskGran) => MemConf(name, depth.toInt, width.toInt, MemPort.fromString(ports), Option(maskGran).map(_.toInt))
+ case MemConf.regex(name, depth, width, ports, maskGran) => Some(MemConf(name, depth.toInt, width.toInt, MemPort.fromString(ports), Option(maskGran).map(_.toInt)))
+ case "" => None
case _ => throw new Exception(s"Error parsing MemConf string : ${s}")
- })
+ }).flatten
}
def apply(name: String, depth: Int, width: Int, readPorts: Int, writePorts: Int, readWritePorts: Int, maskGranularity: Option[Int]): MemConf = {
diff --git a/src/test/scala/firrtlTests/ReplSeqMemTests.scala b/src/test/scala/firrtlTests/ReplSeqMemTests.scala
index b51e2271..a1f27958 100644
--- a/src/test/scala/firrtlTests/ReplSeqMemTests.scala
+++ b/src/test/scala/firrtlTests/ReplSeqMemTests.scala
@@ -487,6 +487,28 @@ circuit CustomMemory :
checkMemConf(confLoc, mems)
(new java.io.File(confLoc)).delete()
}
+
+ "ReplSeqMem" should "produce an empty conf file with no SeqMems" in {
+ val input = """
+circuit NoMemsHere :
+ module NoMemsHere :
+ input clock : Clock
+ input in : UInt<8>
+ output out : UInt<8>
+
+ out is invalid
+
+ out <= in
+"""
+ val mems = Set.empty[MemConf]
+ val confLoc = "ReplSeqMemTests.confTEMP"
+ val annos = Seq(ReplSeqMemAnnotation.parse("-c:CustomMemory:-o:"+confLoc),
+ InferReadWriteAnnotation)
+ val res = compileAndEmit(CircuitState(parse(input), ChirrtlForm, annos))
+ // Check the emitted conf
+ checkMemConf(confLoc, mems)
+ (new java.io.File(confLoc)).delete()
+ }
}
// TODO: make more checks