Change Memory Depth to a BigInt (#1075)

2 files changed, 110 insertions, 3 deletions

diff --git a/src/test/scala/firrtlTests/MemSpec.scala b/src/test/scala/firrtlTests/MemSpec.scala
index 67b7e74d..612a952d 100644
--- a/src/test/scala/firrtlTests/MemSpec.scala
+++ b/src/test/scala/firrtlTests/MemSpec.scala
@@ -2,7 +2,10 @@
 
 package firrtlTests
 
-class MemSpec extends FirrtlPropSpec {
+import firrtl._
+import FirrtlCheckers._
+
+class MemSpec extends FirrtlPropSpec with FirrtlMatchers {
 
   property("Zero-ported mems should be supported!") {
     runFirrtlTest("ZeroPortMem", "/features")
@@ -11,5 +14,68 @@ class MemSpec extends FirrtlPropSpec {
   property("Mems with zero-width elements should be supported!") {
     runFirrtlTest("ZeroWidthMem", "/features")
   }
+
+  property("Very large memories should be supported") {
+    val addrWidth = 65
+    val memSize = BigInt(1) << addrWidth
+    val input =
+      s"""
+         |circuit Test :
+         |  module Test :
+         |    input clock : Clock
+         |    input raddr : UInt<$addrWidth>
+         |    output rdata : UInt<8>
+         |    input wdata : UInt<8>
+         |    input waddr : UInt<$addrWidth>
+         |    input wen : UInt<1>
+         |
+         |    mem m :
+         |      data-type => UInt<8>
+         |      depth => $memSize
+         |      reader => r
+         |      writer => w
+         |      read-latency => 1
+         |      write-latency => 1
+         |      read-under-write => undefined
+         |    rdata <= m.r.data
+         |    m.r.addr <= raddr
+         |    m.r.en <= UInt(1)
+         |    m.r.clk <= clock
+         |    m.w.addr <= waddr
+         |    m.w.data <= wdata
+         |    m.w.en <= wen
+         |    m.w.clk <= clock
+         |    m.w.mask <= UInt(1)
+       """.stripMargin
+    val result = (new VerilogCompiler).compileAndEmit(CircuitState(parse(input), ChirrtlForm, List.empty))
+    // TODO Not great that it includes the sparse comment for VCS
+    result should containLine (s"reg /* sparse */ [7:0] m [0:$addrWidth'd${memSize-1}];")
+  }
+
+  property("Very large CHIRRTL memories should be supported") {
+    val addrWidth = 65
+    val memSize = BigInt(1) << addrWidth
+    val input =
+      s"""
+         |circuit Test :
+         |  module Test :
+         |    input clock : Clock
+         |    input raddr : UInt<$addrWidth>
+         |    output rdata : UInt<8>
+         |    input wdata : UInt<8>
+         |    input waddr : UInt<$addrWidth>
+         |    input wen : UInt<1>
+         |
+         |    cmem m : UInt<8>[$memSize]
+         |    read mport r = m[raddr], clock
+         |    rdata <= r
+         |    write mport w = m[waddr], clock
+         |    when wen :
+         |      w <= wdata
+       """.stripMargin
+    val result = (new VerilogCompiler).compileAndEmit(CircuitState(parse(input), ChirrtlForm, List.empty))
+    // TODO Not great that it includes the sparse comment for VCS
+    result should containLine (s"reg /* sparse */ [7:0] m [0:$addrWidth'd${memSize-1}];")
+  }
 }
 
diff --git a/src/test/scala/firrtlTests/ProtoBufSpec.scala b/src/test/scala/firrtlTests/ProtoBufSpec.scala
index 090a7fea..7a0c3eeb 100644
--- a/src/test/scala/firrtlTests/ProtoBufSpec.scala
+++ b/src/test/scala/firrtlTests/ProtoBufSpec.scala
@@ -107,12 +107,12 @@ class ProtoBufSpec extends FirrtlFlatSpec {
     FromProto.convert(ToProto.convert(ext).build) should equal (ext)
   }
 
-  it should "supported FixedType" in {
+  it should "support FixedType" in {
     val ftpe = ir.FixedType(IntWidth(8), IntWidth(4))
     FromProto.convert(ToProto.convert(ftpe).build) should equal (ftpe)
   }
 
-  it should "supported FixedLiteral" in {
+  it should "support FixedLiteral" in {
     val flit = ir.FixedLiteral(3, IntWidth(8), IntWidth(4))
     FromProto.convert(ToProto.convert(flit).build) should equal (flit)
   }
@@ -138,6 +138,47 @@ class ProtoBufSpec extends FirrtlFlatSpec {
     FromProto.convert(ToProto.convert(slit).build) should equal (slit)
   }
 
+  // Backwards compatibility
+  it should "support mems using old uint32 and new BigInt" in {
+    val size = 128
+    val mem = DefMemory(NoInfo, "m", UIntType(IntWidth(8)), size, 1, 1, List("r"), List("w"), List("rw"))
+    val builder = ToProto.convert(mem).head
+    val defaultProto = builder.build()
+    val oldProto = Firrtl.Statement.newBuilder().setMemory(
+      builder.getMemoryBuilder.clearDepth().setUintDepth(size)
+    ).build()
+    // These Proto messages are not the same
+    defaultProto shouldNot equal (oldProto)
+
+    val defaultMem = FromProto.convert(defaultProto)
+    val oldMem = FromProto.convert(oldProto)
+
+    // But they both deserialize to the original!
+    defaultMem should equal (mem)
+    oldMem should equal (mem)
+  }
+
+  // Backwards compatibility
+  it should "support cmems using old VectorType and new TypeAndDepth" in {
+    val size = 128
+    val cmem = CDefMemory(NoInfo, "m", UIntType(IntWidth(8)), size, true)
+    val vtpe = ToProto.convert(VectorType(UIntType(IntWidth(8)), size))
+    val builder = ToProto.convert(cmem).head
+    val defaultProto = builder.build()
+    val oldProto = Firrtl.Statement.newBuilder().setCmemory(
+      builder.getCmemoryBuilder.clearTypeAndDepth().setVectorType(vtpe)
+    ).build()
+    // These Proto messages are not the same
+    defaultProto shouldNot equal (oldProto)
+
+    val defaultCMem = FromProto.convert(defaultProto)
+    val oldCMem = FromProto.convert(oldProto)
+
+    // But they both deserialize to the original!
+    defaultCMem should equal (cmem)
+    oldCMem should equal (cmem)
+  }
+
   it should "support AsyncResetTypes" in {
     val port = ir.Port(ir.NoInfo, "reset", ir.Input, ir.AsyncResetType)
     FromProto.convert(ToProto.convert(port).build) should equal (port)