diff options
| author | Jim Lawson | 2019-02-21 13:13:13 -0800 |
|---|---|---|
| committer | mergify[bot] | 2019-02-21 21:13:13 +0000 |
| commit | b3833821a50eb7b08fe75f3729ef57355d5765ec (patch) | |
| tree | b0d2d38b408b06219539b7be344d6829ec2a79c6 /src/test | |
| parent | ad0c4ce7afc9856c127031a582232330276bdafe (diff) | |
Don't let the main module become deduped out of existence. (#1023)
Diffstat (limited to 'src/test')
| -rw-r--r-- | src/test/scala/firrtlTests/transforms/DedupTests.scala | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/src/test/scala/firrtlTests/transforms/DedupTests.scala b/src/test/scala/firrtlTests/transforms/DedupTests.scala index d4fe54a1..9b949274 100644 --- a/src/test/scala/firrtlTests/transforms/DedupTests.scala +++ b/src/test/scala/firrtlTests/transforms/DedupTests.scala @@ -532,5 +532,26 @@ class DedupModuleTests extends HighTransformSpec { cs.annotations.toSeq should not contain (SingleTargetDummyAnnotation(A.ref("x"))) cs.deletedAnnotations.isEmpty should be (true) } + "main" should "not be deduped even if it's the last module" in { + val input = + """circuit main: + | module dupe: + | input in: UInt<8> + | output out: UInt<8> + | out <= in + | module main: + | input in: UInt<8> + | output out: UInt<8> + | out <= in + """.stripMargin + val check = + """circuit main: + | module main: + | input in: UInt<8> + | output out: UInt<8> + | out <= in + """.stripMargin + execute(input, check, Seq.empty) + } } |
