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path: root/src/test/scala/firrtlTests/transforms/BlacklBoxSourceHelperSpec.scala
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2019-07-25Allow name of blackbox resource .f file to change from static value (#1129)Albert Magyar
* Allow name of blackbox resource .f file to change from static value * Restore fileListName as a deprecated def per Jack's feedback * Support both local and absolute paths for .f resource files
2018-10-31Don't include verilog header files in "FileList" for VCS/Verilator. (#918)Jim Lawson
When constructing the black box helper file list (firrtl_black_box_resource_files.f), filter out Verilog header files (*.vh) - Fixes #917
2018-10-24Better error message on missing BlackBox resourceSchuyler Eldridge
This wraps interactions with a BlackBox resource file such that a FileNotFoundException are wrapped in a BlackBoxNotFoundException and rethrown. This provides a better, verbose error message to the user and avoids a FileNotFoundException showing up as an internal FIRRTL error. This adds tests that the expected exception is thrown for both BlackBoxResourceAnno and BlackBoxResourceAnno. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-10-01add BlackBoxPathAnno (#903)albertchen-sifive
2018-07-26Support for load memory annotations in chisel (#833)Chick Markley
* Support for load memory annotations in chisel This PR * Delays the BlackBoxSourceHelper transformation to the Emitter stage of the VerilogCompiler * remove from VerilogCompiler * move to VerilogEmitter * Changes the verilog emitter to allow programmatic access to the verilog module declaration * Creating a bindable module requires headers to match * Provides a unit test that shows how to generate a bindable module. * Binding support Treadle needed LoadMemoryAnnotation to be in firrtl instead of chisel in order to recognize the annotations and use them for memory loading * Binding support - Fixed bug that handled suffixes on memory initializing files * Binding support - Add a bit more doc to the API provided by the VerilogRenderer
2018-04-11Cleaning up BlackBoxSourceHelper (#786)Henry Cook
Create sources once per module, not once per instance Clean up writing the file list Don't prepend file list with '-v's (non-standard and not all verilog) Change file list file name (not all verilog) Use ListSets for determinism
2018-02-27Refactor Annotations (#721)Jack Koenig
- Old Annotation renamed to deprecated LegacyAnnotation - Annotation is now a trait that can be extended - New JsonProtocol for Annotation [de]serialization - Replace AnnotationMap with AnnotationSeq - Deprecate Transform.getMyAnnotations - Update Transforms - Turn on deprecation warnings - Remove deprecated Driver.compile - Make AnnotationTests abstract with Legacy and Json subclasses - Add functionality to convert LegacyAnnotations of built-in annos This will give a noisy warning and is more of a best effort than a robust solution. Fixes #475 Closes #609
2017-06-28[Testing] Clean up SimpleTransformSpec execute methodsJack Koenig
This makes it more concise to write tests
2017-03-06Add ability to emit 1 file per module (#443)Jack Koenig
Changes Emitters to also be Transforms and use Annotations for both telling an emitter to do emission as well as getting the emitted result. Helper functions ease the use of the new interface. Also adds a FirrtlExecutionOptions field as well as a command-line option. Use of Writers in Compilers and Emitters is now deprecated.
2017-01-31Blackboxhelper (#418)Chick Markley
* First pass at implementing a annotation based mechanism to move black box verilator files into the target directory * A little bit of style cleanup * A little bit of style cleanup * Fix the driver, wasn't appending targetDir properly Add some docs * test had wrong value now that targetdir is added to annnos * Now saves a list of all black box verilog files moved into target directory. Then creates a file black_box_verilog_files.f that contains this list with -v prepended to each line * Made black box source helper be low to low form Added it to the verilog compiler transforms Added a test to make sure it got there * targetDir annotation is targeted to a CircuitName("All")