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* Add FileInfo to asyncResetAlwaysBlocks
Always blocks need three FileInfo (if, true, false) to show line numbers,
but initially, every always blocks only have one FileInfo (false).
RemoveReset adds the extra two FileInfo to sync always blocks,
so sync always blocks can have line numbers.
Async always blocks don't provide their only FileInfo, so there are no line numbers.
This commit gives async always block the extra FileInfo to show line numbers for them.
This code:
```scala
import chisel3._
import chisel3.stage._
import firrtl.CustomDefaultRegisterEmission
class Test extends Module with RequireAsyncReset {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
val valid = RegInit(false.B)
valid := io.in
io.out := valid
}
object Test extends App {
new ChiselStage().execute(Array(), Seq(
ChiselGeneratorAnnotation(() => new Test()),
CustomDefaultRegisterEmission(useInitAsPreset = false, disableRandomization = true)
))
}
```
will generate this Verilog:
```verilog
module Test(
input clock,
input reset,
input io_in,
output io_out
);
reg valid; // @[Playground.scala 10:22]
assign io_out = valid; // @[Playground.scala 12:10]
always @(posedge clock or posedge reset) begin
if (reset) begin // @[Playground.scala 10:22]
valid <= 1'h0; // @[Playground.scala 10:22]
end else begin
valid <= io_in; // @[Playground.scala 11:9]
end
end
endmodule
```
they have correct line numbers (10, 10, 11).
* Add test for async always block line numbers
* Add comment for review
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(#2423)
Co-authored-by: Jack Koenig <koenig@sifive.com>
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* Add option to disable random mem/reg init
Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
* fix for code review.
Co-authored-by: SharzyL <me@sharzy.in>
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* Add new util "groupByIntoSeq"
* Restore annotation order when dedupping annotations
* Attribute annotations now deduplicate
* Implement doc string anno dedup
Co-authored-by: Jack Koenig <koenig@sifive.com>
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Fixes bug with mul or div followed by cat.
Also fixes some Verilog lint issues.
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Overflow of 32-bit Int would cause any negative literal value equal to
-(2^(width % 32 - 1)) where width >= 32 to be incorrectly inverted
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This should speed up the common case
as the compiler never operates on the
unescaped string.
The new escape function also fixes a bug
where ']' was not escaped even though it
is the delimiting character for FileInfo.
In order to maintain backwards
compatibility for the ProtoBuf format,
this patch adds escape/unescape calls
when going from/to protobuf format.
For better performance we should consider
changing the protobuf format.
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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* Add attributes, ifdefs to emitter.
* Make ifdef API a little cleaner.
* Remove references to ifdefs.
* Remove more of the ifdef stuff I missed
* Fix up failing tests
* Add multiple attribute test case
* Remove tpe as a parameter from Annotations.
Some general refactoring.
* Add some documentation.
* Incorporate some feedback
* Expand some spaghetti code, add comments
* Fix type signature by removing it
* bug fix in test
* Fix unchecked type parameter matches in AddDescriptionNodes.
* use target to replace name
Co-authored-by: Paul Rigge <rigge@berkeley.edu>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* consolidated wire <type> x; assign x = y; to wire <type> x = y;
* Remove dead code from Emitter.scala
Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
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* adding init macros
* fix missing tick
* adding more documentation; fixing up emitter tests
* adding initial-guarding macro test
* prefixing macros with FIRRTL
* cleanup
* typo fix
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* Pull out common test utilities into a separate package
* Project a fat jar for test utilities
Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
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Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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This reverts commit f77487d37bd7c61be231a8000a3197d37cf55499.
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Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* Generates lint-clean Verilog for the case: x + -1
...where x is anything and 1 is any literal.
Master behavior:
input x : SInt<8>
output z : SInt<9>
z <= add(x, SInt(-2))
generates
assign z = $signed(x) + -8'sh2;
After this PR:
assign z = $signed(x) - 8'sh2;
If the literal is the maximum possible literal, a special case is triggered to properly trim the resulting subtraction.
Input:
input x : SInt<2>
output z : SInt<3>
z <= add(x, SInt(-2))
now generates (after this PR)
assign z = $signed(x) - 3'sh2;
* Updated documentation
* Change ArrayBuffer to ListBuffer
* Change name to minNegValue
* Remove mutable public interfaces
Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* transform InlineBitExtractions
* InlineNotsTransform, InlineBitExtractionsTransform: inputForm/outputForm = UnknownForm
* clean up some minor redundancies from Adam review
* clarifications from Seldrige review
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[skip formal checks]
Adds new InlineCastsTransform to the VerilogEmitter which removes
Statements that do nothing but cast by inlining the cast Expression
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[skip formal checks]
* ConstProp FoldEqual/FoldNotEqual propagate boolean (non-)equality with true/false
* transform InlineNots
* transform back-to-back Nots into straight rename
* swap mux with inverted select
Co-authored-by: Jack Koenig <jack.koenig3@gmail.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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- Add firrtl.transforms.CombineCats
- Use CombineCats in LowFirrtlOptimization
- Modify Verilog emitter to allow for nested Cat DoPrims
- Modify firrtlEquivalenceTest to write input FIRRTL string to test directory
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This moves VerilogRename out of Passes.scala and genericizes it as the new
Transform KemoveKeywordCollisions. This new Transform will remove keywords
for arbitrary sets of reserved keyword.
This adds VerilogRename back as a class instead of an object.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Summary of changes to firrtl.passes.VerilogRename:
- Use "_" to mangle names that conflict with Verilog
keywords (previously "$")
- Rewrite to operate on the whole AST to propogate mangled ports and
module names
- Make VerilogRename a Transform (was previously a Pass)
- Renames are now propagated
- Adds documentation for new VerilogRename
This makes the VerilogRename Transform (previously a Pass) use an
underscore ('_') instead of a dollar sign ('$') to mangle names that
conflict with Verilog keywords. This prevents problems with potentially
buggy tools that are not expecting '$' in Verilog names.
This reimplements VerilogRename to be safe for name collisions that may
occur anywhere in the AST, e.g., in ports, module names, circuit names, or
in any statements/expressions. Previously, names were only mangled in
statements and in place. This resulted in problems where renames of ports
in a child's namespace would not be guaranteed to be mangled the same way
in a parent's namespace. The algorithm is reimplemented to walk all
modules in reverse topological order (from leafs to main) and relying on a
RenameMap to track name changes.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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add description nodes, transform; modify VerilogEmitter to emit comments
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* Support for load memory annotations in chisel
This PR
* Delays the BlackBoxSourceHelper transformation to the Emitter stage of the VerilogCompiler
* remove from VerilogCompiler
* move to VerilogEmitter
* Changes the verilog emitter to allow programmatic access to the verilog module declaration
* Creating a bindable module requires headers to match
* Provides a unit test that shows how to generate a bindable module.
* Binding support
Treadle needed LoadMemoryAnnotation to be in firrtl instead of chisel in order to recognize the annotations and use them for memory loading
* Binding support
- Fixed bug that handled suffixes on memory initializing files
* Binding support
- Add a bit more doc to the API provided by the VerilogRenderer
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* Make VerilogEmitter properly handle pad of width <= width of arg
* Constant prop pads with pad amount <= width of arg
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but not Emitter. (#717)
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Changes Emitters to also be Transforms and use Annotations for both
telling an emitter to do emission as well as getting the emitted result.
Helper functions ease the use of the new interface. Also adds a
FirrtlExecutionOptions field as well as a command-line option. Use of
Writers in Compilers and Emitters is now deprecated.
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* Add pass that fixes up widths with modulus operator for verilog
* Add basic test for Verilog emission of Rem
* Oops, left in some printlns.
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Restricts annotations to be string-based (and thus less typesafe)
Makes annotations more easily serializable and interact with Chisel
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Replace with more sensible comment to see LICENSE rather than including the
whole license in every file
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* Transform Ids now handled by Class[_ <: Transform] instead of magic numbers
* Transforms define inputForm and outputForm
* Custom transforms can be inserted at runtime into compiler or the Driver
* Current "built-in" custom transforms handled via above mechanism
* Verilog-specific passes moved to the Verilog emitter
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Fixed Verilog emission reduce ops with efficient implementation
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