sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Expand)	Author
2022-01-06	Add FileInfo to asyncResetAlwaysBlocks (#2451)	sinofp
2021-11-30	[deprecation clean up] remove trait firrtl.util.BackendCompilationUtilities (...	Jiuyang Liu
2021-11-19	Disable random init (#2396)	Jiuyang Liu
2021-07-29	Dedup attribute annos (#2297)	Jared Barocsi
2021-01-28	Stop padding multiply and divide ops (#2058)	Jack Koenig
2020-10-26	fix a test not detecting verilog name conflicts.	Jiuyang liu
2020-10-01	Fix "fix" for negative literals > 32 bits	Jack Koenig
2020-09-16	Change to Apache 2.0 License (#1901)	Chick Markley
2020-08-26	Emit parentheses in Verilog for nested unary ops (#1865)	Jack Koenig
2020-08-14	Apply scalafmt again	Jack Koenig
2020-08-14	All of src/ formatted with scalafmt	chick
2020-07-15	ir: store FileInfo string in escaped format (#1690)	Kevin Laeufer
2020-06-25	Add a second instance to Verilog keyword test	Schuyler Eldridge
2020-06-22	recore of Attributes (#1643)	Jiuyang Liu
2020-05-13	consolidated wire+assign to just wire, with expression inlined (#1600)	Murali Vijayaraghavan
2020-05-08	deprecating BackendCompilationUtilities trait for object (#1575)	Deborah Soung
2020-05-05	before/after initial block macros (#1550)	Deborah Soung
2020-03-17	[RFC] Factor out common test classes; package them (#1412)	David Biancolin
2020-03-11	Migrate to DependencyAPI	Schuyler Eldridge
2020-03-04	Revert "Verilog emitter transform InlineNots (#1270)"	Albert Magyar
2020-02-12	Removed unused imports in src/test/ (#1381)	Jim Lawson
2020-02-12	Fixing lint error: x + -1 (#1374)	Adam Izraelevitz
2020-01-15	Verilog emitter transform InlineBitExtractions (#1296)	John Ingalls
2020-01-07	Remove unnecessary $signed casts for PrimOps in Verilog Emitter	Jack Koenig
2020-01-06	Verilog emitter transform InlineNots (#1270)	John Ingalls
2019-10-31	Guard initial blocks in emitted Verilog with `ifndef SYNTHESIS	Jack Koenig
2019-10-22	Add Register Updates/else-if Verilog Emitter tests	Schuyler Eldridge
2018-11-15	Combine cats (#851)	Albert Chen
2018-10-12	Refactor VerilogRename -> RemoveKeywordCollisions	Schuyler Eldridge
2018-10-12	Verilog renaming uses "_", works on whole AST	Schuyler Eldridge
2018-08-30	Emit Verilog Comments (#874)	albertchen-sifive
2018-07-26	Support for load memory annotations in chisel (#833)	Chick Markley
2018-05-29	Fix pad (#817)	Jack Koenig
2018-02-22	Add tests for #702. Adds Utility functions. Allows clock muxing in FIRRTL, bu...	Adam Izraelevitz
2017-03-06	Add ability to emit 1 file per module (#443)	Jack Koenig
2017-02-26	Align types and names of ports in emitted Verilog (#463)	Jack Koenig
2017-01-19	Verilog rem fix (#404)	grebe
2016-11-23	Stringified annotations (#367)	Adam Izraelevitz
2016-11-04	Cleanup license at top of every file (#364)	Jack Koenig
2016-11-04	Refactor Compilers and Transforms	jackkoenig
2016-10-31	Fixed Verilog emission of andr, orr, and xorr (#357)	Adam Izraelevitz