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- Fix & test MemorySynthInit behavior with MemoryArrayInitAnnotation and MemoryScalarInitAnnotation.
Add test case for MemoryRandomInitAnnotation which is, on the contrary, expected not to leak any randomization statement in synthesis context.
- Refactor MemoryInitSpec for improved results readability
Context:
PR #2166 (commit: 4530152) introduced MemorySynthInit annotation to control whether statement generated with Memory*InitAnnotation (emitted within initial begin block in verilog) should be guarded with ifndef SYNTHESIS or not.
Unfortunately only one configuration (MemoryFileInlineAnnotation) has been tested while the others have been generating incorrect verilog statements (MemoryArrayInitAnnotation and MemoryScalarInitAnnotation).
Signed-off-by: Jean Bruant <jean.bruant@ovhcloud.com>
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* Add transform to deduplicate memory annotations
* Add annotation deduplication to Dedup stage
* ResolveAnnotationPaths and EliminateTargetPaths now invalidate the dedup annotations transform
* Verilog emitter now throws exception when memory annotations fail to dedup
Co-authored-by: Jack Koenig <koenig@sifive.com>
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This PR adds options for memory initialization inside or outside the
`ifndef SYNTHESIS` block.
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This PR adds a new annotation allowing inline loading for memory files
in Verilog code.
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* Utils: add to_dir helper function
* firrt.SymbolTable trait for scanning declarations
* ir: RefLikeExpression trait to represent SubField, SubIndex, SubAccess and Reference nodes
* add new implementation of the LowerTypes pass
* replace LowerTypes with NewLowerTypes
* remove dependencies on Uniquify
* GroupComponentSpec: GroupComponents is run before lower types
* NewLowerTypes: address Adam's suggestions
* LoweringCompilerSpec: Uniquify was removed and NewLowerTypes
* LowerTypesSpec: add newline at the end of file
* LowerTypesSpec: port Uniquify tests to combined pass
* NewLowerTypes: ensure that internal methods are not visible
* NewLowerTypes: extend DependencyAPIMigration
* NewLowerTypes: lower ports without looking at the body
* LowerTypesSpec: use TransformManager instead of hard coded passes.
* NewLowerTypes: names are already assumed to be part of the namespace
* LowerTypesSpec: test name clashes between ports and nodes, inst, mem
* NewLowerTypes: correctly rename nodes, mems and instances that clash with port names
* NewLowerTypes: Iterable[String] instead of Seq[String] for 2.13
* NewLowerTypes: add a fast path for ground types without renaming
* LowerTypesSpec: remove trailing commans for 2.11
* LowerTypesSpec: explain why there are two
* Uniquify: use loweredName from NewLowerType
* replace old LowerTypes pass with NewLowerTypes pass
* Uniquify: deprecate pass usage
There are some functions that are still used by other passes.
* LowerTypes: InstanceKeyGraph now has a private constructor
* LowerTypes: remove remaining references to NewLowerTypes
* LoweringCompilerSpec: fix transform order to LowerTypes
* SymbolTable: add improvements from PR
* LoweringCompilerSpec: ignore failing CustomTransform tests
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* Support Memory Initialization for Simulation and FPGA Flows
This adds a minimal annotation that allows users to
influence if memories are randomly initialized,
if all entries are initialized to the same scalar or
if each entry should be initialized to a different value.
We use the init block in order to initialize memories
which is supported by verilator as well as yosys
and has previously been used to randomize the initial
memory contents.
* LowerTypes: error when trying to split up a memory with MemoryInitAnnotation
Currently the MemoryInitAnnotation only works for
ground-type memories.
We catch misuse of this annotation at the point of
the firrtl compiler at which memories on non-ground type
get split up, i.e., the LowerTypes transform.
Chisel should try to prevent annotating non-ground
type memories in the frontend, but it is nice to
have an additional check.
* MemoryInitSpec: test JSON deserialization
* MemoryInitAnnotation: split up into three different annotations instead of exposing MemoryInitValue
Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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