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path: root/src/test/scala/firrtlTests/CompilerTests.scala
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2020-09-16Change to Apache 2.0 License (#1901)Chick Markley
2020-08-14All of src/ formatted with scalafmtchick
2020-08-14tests: Decrease Dependency on Deprecated APIs (#1839)Kevin Laeufer
* test: add LeanTransformSpec to replace the old SimpleTransformSpec SimpleTransformSpec isn't simple anymore! * AnnotationTests: remove deprecated Compiler code * LeanTransformSpec: implicitly add right EmitCircuitAnnotation * AsyncResetSpec: move to new lean spec * CheckCombLoopsSpec: remove deprecated Compiler code * ChirrtlMemSpec: remove deprecated compiler code * CompilerTest: remove use of deprecated Compiler API
2020-05-13consolidated wire+assign to just wire, with expression inlined (#1600)Murali Vijayaraghavan
* consolidated wire <type> x; assign x = y; to wire <type> x = y; * Remove dead code from Emitter.scala Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
2020-05-06Update scalatest to 3.1.1 (#1405)Scala Steward
* Update scalatest to 3.1.1 * Update scalatest to 3.1.1 * Update scalatest to 3.1.1 Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu> Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-04-13Add test-case for explicit padding of SInts in mverilog compilerAlbert Magyar
2020-03-25Update scalatest 3.1.0 (#1383)Jim Lawson
* Removed unused imports in src/test/ * Update ScalaTest deprecations. * Update scalatest from 3.0.8 to 3.1.0; apply auto fix for deprecations Co-authored-by: Jack Koenig <koenig@sifive.com>
2020-02-12Removed unused imports in src/test/ (#1381)Jim Lawson
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2019-02-05Do Shr constant propagation in LegalizeSchuyler Eldridge
This uses the foldShiftRight method of the ConstantPropagation Transform when legalizing Shr PrimOps. This has the effect of removing literals with bit extracts from the MinimumVerilogCompiler. This makes the formerly private foldShiftRight method of a public method of the ConstantPropagation companion object. Tests in the MimimumVerilogCompilerSpec are updated to check that Shr is handled as intended. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-02-05Add RemoveValidIf to -X mverilogSchuyler Eldridge
This adds the RemoveValidIf Pass to the MinimumLowFirrtlOptimization Transform. A test case is included to verify that `is invalid` is properly converted to a connection to zero. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-02-05Add "mverilog" Compiler Option, Compiler FixesSchuyler Eldridge
This adds "mverilog" to the "--compiler" command line option. This will run the MinimumVerilogCompiler. This additionally fixes the MinimumVerilogCompiler such that DeadCodeElimination will not be run (it's not supposed to be). This is done by adding a MinimumVerilogEmitter, subclassing VerilogVerilog, that strips the DeadCodeElimination step from its parent. Additionally, BlackBoxSourceHelper is removed from the MinimumVerilogCompiler since this will be run by the VerilogEmitter already. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2017-12-27Removed top preamble (#640)Adam Izraelevitz
2017-03-06Add ability to emit 1 file per module (#443)Jack Koenig
Changes Emitters to also be Transforms and use Annotations for both telling an emitter to do emission as well as getting the emitted result. Helper functions ease the use of the new interface. Also adds a FirrtlExecutionOptions field as well as a command-line option. Use of Writers in Compilers and Emitters is now deprecated.
2016-12-14Remove scalpels.Jim Lawson
2016-12-14Add support for top-level use of MiddleFirrtlCompiler.Jim Lawson
2016-11-04Cleanup license at top of every file (#364)Jack Koenig
Replace with more sensible comment to see LICENSE rather than including the whole license in every file
2016-11-04Refactor Compilers and Transformsjackkoenig
* Transform Ids now handled by Class[_ <: Transform] instead of magic numbers * Transforms define inputForm and outputForm * Custom transforms can be inserted at runtime into compiler or the Driver * Current "built-in" custom transforms handled via above mechanism * Verilog-specific passes moved to the Verilog emitter
2016-08-25emit wires instead of registers for invalid randomizationHoward Mao
Before, the verilog emitter would connect registers to the invalid ports and use random initialization on the generated registers. It is better to generate wires instead and use random assignment on the wires.
2016-08-25update verilog generation testHoward Mao
2016-07-27Reworked annotation system. Added tenacity and permissibilityAdam Izraelevitz
Conflicts: src/main/scala/firrtl/Compiler.scala src/main/scala/firrtl/LoweringCompilers.scala src/main/scala/firrtl/passes/Inline.scala src/test/scala/firrtlTests/AnnotationTests.scala src/test/scala/firrtlTests/InlineInstancesTests.scala
2016-06-10API Cleanup - ASTJack
trait AST -> abstract class FirrtlNode Move all IR to new package ir Add import of firrtl.ir._
2016-05-12Restructured Compiler to use Transforms. Added an InlineInstance pass.Adam Izraelevitz
Transforms are new unit of modularity within the compiler.
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