All of src/ formatted with scalafmt

1 files changed, 82 insertions, 82 deletions

diff --git a/src/test/scala/firrtlTests/CompilerTests.scala b/src/test/scala/firrtlTests/CompilerTests.scala
index dfa796c4..129ff8f5 100644
--- a/src/test/scala/firrtlTests/CompilerTests.scala
+++ b/src/test/scala/firrtlTests/CompilerTests.scala
@@ -12,36 +12,36 @@ import org.scalatest.flatspec.AnyFlatSpec
 import org.scalatest.matchers.should.Matchers
 
 /**
- * An example methodology for testing Firrtl compilers.
- *
- * Given an input Firrtl circuit (expressed as a string),
- * the compiler is executed. The output of the compiler
- * should be compared against the check string.
- */
+  * An example methodology for testing Firrtl compilers.
+  *
+  * Given an input Firrtl circuit (expressed as a string),
+  * the compiler is executed. The output of the compiler
+  * should be compared against the check string.
+  */
 abstract class CompilerSpec(emitter: Dependency[firrtl.Emitter]) extends LeanTransformSpec(Seq(emitter)) {
-   def input: String
-   def getOutput: String = compile(input).getEmittedCircuit.value
+  def input: String
+  def getOutput: String = compile(input).getEmittedCircuit.value
 }
 
 /**
- * An example test for testing the HighFirrtlCompiler.
- *
- * Given an input Firrtl circuit (expressed as a string),
- * the compiler is executed. The output of the compiler
- * is parsed again and compared (in-memory) to the parsed
- * input.
- */
+  * An example test for testing the HighFirrtlCompiler.
+  *
+  * Given an input Firrtl circuit (expressed as a string),
+  * the compiler is executed. The output of the compiler
+  * is parsed again and compared (in-memory) to the parsed
+  * input.
+  */
 class HighFirrtlCompilerSpec extends CompilerSpec(Dependency[firrtl.HighFirrtlEmitter]) with Matchers {
-   val input =
-"""circuit Top :
+  val input =
+    """circuit Top :
   module Top :
     input a : UInt<1>[2]
     node x = a
 """
-   val check = input
-   "Any circuit" should "match exactly to its input" in {
-      (parse(getOutput)) should be (parse(check))
-   }
+  val check = input
+  "Any circuit" should "match exactly to its input" in {
+    (parse(getOutput)) should be(parse(check))
+  }
 }
 
 /**
@@ -53,8 +53,8 @@ class HighFirrtlCompilerSpec extends CompilerSpec(Dependency[firrtl.HighFirrtlEm
   * string compared to the correct lowered circuit.
   */
 class MiddleFirrtlCompilerSpec extends CompilerSpec(Dependency[firrtl.MiddleFirrtlEmitter]) with Matchers {
-   val input =
-      """
+  val input =
+    """
 circuit Top :
   module Top :
     input reset : UInt<1>
@@ -64,77 +64,77 @@ circuit Top :
     when reset :
       b <= UInt(0)
 """
-   // Verify that Vecs are retained, but widths are inferred and whens are expanded.
-   val check = Seq(
-      "circuit Top :",
-      "  module Top :",
-      "    input reset : UInt<1>",
-      "    input a : UInt<1>[2]",
-      "    wire b : UInt<1>",
-      "    node _GEN_0 = mux(reset, UInt<1>(\"h0\"), a[0])",
-      "    b <= _GEN_0\n\n"
-   ).reduce(_ + "\n" + _)
-   "A circuit" should "match exactly to its MidForm state" in {
-      (parse(getOutput)) should be (parse(check))
-   }
+  // Verify that Vecs are retained, but widths are inferred and whens are expanded.
+  val check = Seq(
+    "circuit Top :",
+    "  module Top :",
+    "    input reset : UInt<1>",
+    "    input a : UInt<1>[2]",
+    "    wire b : UInt<1>",
+    "    node _GEN_0 = mux(reset, UInt<1>(\"h0\"), a[0])",
+    "    b <= _GEN_0\n\n"
+  ).reduce(_ + "\n" + _)
+  "A circuit" should "match exactly to its MidForm state" in {
+    (parse(getOutput)) should be(parse(check))
+  }
 }
 
 /**
- * An example test for testing the LoweringCompiler.
- *
- * Given an input Firrtl circuit (expressed as a string),
- * the compiler is executed. The output of the compiler is
- * a lowered version of the input circuit. The output is
- * string compared to the correct lowered circuit.
- */
+  * An example test for testing the LoweringCompiler.
+  *
+  * Given an input Firrtl circuit (expressed as a string),
+  * the compiler is executed. The output of the compiler is
+  * a lowered version of the input circuit. The output is
+  * string compared to the correct lowered circuit.
+  */
 class LowFirrtlCompilerSpec extends CompilerSpec(Dependency[firrtl.LowFirrtlEmitter]) with Matchers {
-   val input =
-"""
+  val input =
+    """
 circuit Top :
   module Top :
     input a : UInt<1>[2]
     node x = a
 """
-   val check = Seq(
-      "circuit Top :",
-      "  module Top :",
-      "    input a_0 : UInt<1>",
-      "    input a_1 : UInt<1>",
-      "    node x_0 = a_0",
-      "    node x_1 = a_1\n\n"
-   ).reduce(_ + "\n" + _)
-   "A circuit" should "match exactly to its lowered state" in {
-      (parse(getOutput)) should be (parse(check))
-   }
+  val check = Seq(
+    "circuit Top :",
+    "  module Top :",
+    "    input a_0 : UInt<1>",
+    "    input a_1 : UInt<1>",
+    "    node x_0 = a_0",
+    "    node x_1 = a_1\n\n"
+  ).reduce(_ + "\n" + _)
+  "A circuit" should "match exactly to its lowered state" in {
+    (parse(getOutput)) should be(parse(check))
+  }
 }
 
 /**
- * An example test for testing the VerilogCompiler.
- *
- * Given an input Firrtl circuit (expressed as a string),
- * the compiler is executed. The output of the compiler is
- * the corresponding Verilog. The output is string compared
- * to the correct Verilog.
- */
+  * An example test for testing the VerilogCompiler.
+  *
+  * Given an input Firrtl circuit (expressed as a string),
+  * the compiler is executed. The output of the compiler is
+  * the corresponding Verilog. The output is string compared
+  * to the correct Verilog.
+  */
 class VerilogCompilerSpec extends CompilerSpec(Dependency[firrtl.VerilogEmitter]) with Matchers {
-   val input = """circuit Top :
-                 |  module Top :
-                 |    input a : UInt<1>[2]
-                 |    output b : UInt<1>[2]
-                 |    b <= a""".stripMargin
-   val check = """module Top(
-                 |  input   a_0,
-                 |  input   a_1,
-                 |  output  b_0,
-                 |  output  b_1
-                 |);
-                 |  assign b_0 = a_0;
-                 |  assign b_1 = a_1;
-                 |endmodule
-                 |""".stripMargin
-   "A circuit's verilog output" should "match the given string and not have RANDOMIZE if no invalids" in {
-      getOutput should be (check)
-   }
+  val input = """circuit Top :
+                |  module Top :
+                |    input a : UInt<1>[2]
+                |    output b : UInt<1>[2]
+                |    b <= a""".stripMargin
+  val check = """module Top(
+                |  input   a_0,
+                |  input   a_1,
+                |  output  b_0,
+                |  output  b_1
+                |);
+                |  assign b_0 = a_0;
+                |  assign b_1 = a_1;
+                |endmodule
+                |""".stripMargin
+  "A circuit's verilog output" should "match the given string and not have RANDOMIZE if no invalids" in {
+    getOutput should be(check)
+  }
 }
 
 class MinimumVerilogCompilerSpec extends CompilerSpec(Dependency[firrtl.MinimumVerilogEmitter]) with Matchers {
@@ -166,6 +166,6 @@ class MinimumVerilogCompilerSpec extends CompilerSpec(Dependency[firrtl.MinimumV
                  |endmodule
                  |""".stripMargin
   "A circuit's minimum Verilog output" should "pad signed RHSes but not reflect any const-prop or DCE" in {
-    getOutput should be (check)
+    getOutput should be(check)
   }
 }