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AgeCommit message (Expand)Author
2021-09-29Add RTLIL Backend. (#2331)Nicolas Machado
2021-03-19Legalize neg: -x becomes 0 - x (#2128)Jack Koenig
2020-09-16Change to Apache 2.0 License (#1901)Chick Markley
2020-08-13Remove LegacyAnnotation and [most] MoultingYaml (#1833)Jack Koenig
2020-08-01Error on ExtModules w/ same defname, diff. ports (#1734)Schuyler Eldridge
2020-07-27Fix out-of-scope reference in handwritten CHIRRTL mem testAlbert Magyar
2020-03-12Add Support for FPGA Bitstream Preset-registers (#1050)John's Brew
2019-05-24Emit legal Verilog literals for ExtModule IntParams > 32-bit (#1087)Jack Koenig
2019-02-14Asynchronous Reset (#1011)Jack Koenig
2018-11-07Add firrtl.options testsSchuyler Eldridge
2018-10-31Don't include verilog header files in "FileList" for VCS/Verilator. (#918)Jim Lawson
2018-06-11Allow escaped single quotes in RawParams (#820)Richard Lin
2018-05-21Fix more problems with zero width things. (#779)grebe
2018-03-19Masks for zero-width fields of mems should be width zero. (#763)grebe
2018-02-27Refactor Annotations (#721)Jack Koenig
2017-06-21Add --no-dce command-line option to skip DCEJack Koenig
2017-06-12Add option to disable combinational loop detectionJack Koenig
2017-04-18"Scope" test resource (top.cpp). (#398)Jim Lawson
2017-01-29Keep firrtl's simulation environment in sync with chisel's. (#425)Jim Lawson
2016-12-08Clk2clock - rename the implicit "clk" module input "clock" (#387)Jim Lawson
2016-11-23Stringified annotations (#367)Adam Izraelevitz
2016-11-05Fix CHIRRTL bugs (#355)Donggyu
2016-11-04Cleanup license at top of every file (#364)Jack Koenig
2016-11-04Refactor Compilers and Transformsjackkoenig
2016-10-26Add RawString ExtModule parameter supportjackkoenig
2016-10-26Add Support for Parameterized ExtModules and Name Overridejackkoenig
2016-10-26Add ExtModule Testsjackkoenig
2016-10-07Add test for Firrtl mems with no ports (#327)Jack Koenig
2016-09-12Add LegalizeSpec for testing Verilog Legalization passJack
2016-05-12Restructured Compiler to use Transforms. Added an InlineInstance pass.Adam Izraelevitz
2016-05-03Add Expand Whens testjackkoenig
2016-05-03Make simulations that time out fail when run in firrtlTestsjackkoenig
2016-04-20Add tests for CHIRRTL mem port definitions.jackkoenig
2016-04-20Fix top.cpp reset race condition #137jackkoenig
2016-04-08Add small test for issue #105jackkoenig
2016-03-15Revamp string literal handlingjackkoenig
2016-03-03Add some integration tests: successful compilation and executionjackkoenig
2016-02-23Add rocket regression, just runs rocket.fir through Verilog compiler and comp...Jack
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