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2020-05-13consolidated wire+assign to just wire, with expression inlined (#1600)Murali Vijayaraghavan
* consolidated wire <type> x; assign x = y; to wire <type> x = y; * Remove dead code from Emitter.scala Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
2020-05-11Have AppendInfo use MultiInfo, rather than appending with : (#1580)Adam Izraelevitz
* Bugfix - have AppendInfo use MultiInfo, rather than appending with : * Address reviewer feedback Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-05-11Add andr, orr, xorr literal constant propagationSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-05-08Don't check Types of Expressions in CheckHighFormLikeJack Koenig
Expression Types are derived. They cannot cause the errors detected by CheckHighFormLike independently of the user-specified types that remain chedked. This speeds up CheckChirrtl and CheckHighForm substantially.
2020-05-08Lazily generate more detailed error messages in CheckHighFormLikeJack Koenig
Don't serialize Expressions unless there is an error
2020-05-08deprecating BackendCompilationUtilities trait for object (#1575)Deborah Soung
2020-05-05before/after initial block macros (#1550)Deborah Soung
* adding init macros * fix missing tick * adding more documentation; fixing up emitter tests * adding initial-guarding macro test * prefixing macros with FIRRTL * cleanup * typo fix Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-05-04Add LegalizeAndReductionsTransformJack Koenig
Workaround for https://github.com/verilator/verilator #2300 present in Verilator versions v4.026 - v4.032. This transform turns AND reductions for expressions > 64-bits into an equality check with all ones. It is included as a prerequisite for all Verilog emitters.
2020-05-01Add missing invalidations to some transforms (#1541)Schuyler Eldridge
This adds missing invalidations to four transforms: - ExpandConnects - RemoveAccesses - SplitExpressions - VerilogMemDelays This necessarily updates test cases which expect exact transform orders to reflect the new order. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-05-01Emitter: guard _RAND_* declarations with ifdef (#1548)Albert Chen
* Emitter: add declare functions ifdef guard * Emitter: add ifdef initials * Emitter: add comments, cleanup * Emitter: changes from code review - make new methods private - use .withDefault - remove empty initial block Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-04-27Fix remaining 'removed in 1.3' deprecations (#1542)Albert Magyar
* Bump old 'removed in 1.3' deprecation * Remove outdated passes.VerilogRename * Fixes #1467
2020-04-22s/dependents/optionalPrerequisiteOf/Schuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-04-22Add optionalPrerequisiteOf, deprecate dependentsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-04-22Avoid repeated set construction in WiringTransform invalidatesSchuyler Eldridge
Co-authored-by: Jack Koenig <koenig@sifive.com> Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-04-22Mixin DependencyAPIMigration to all TransformsSchuyler Eldridge
This mixes in the new DependencyAPIMigration trait into all Transforms and Passes. This enables in-tree transforms/passes to build without deprecation warnings associated with the deprecated CircuitForm. As a consequence of this, every Transform now has UnknownForm as both its inputForm and outputForm. This PR modifies legacy Compiler and testing infrastructure to schedule transforms NOT using mergeTransforms/getLoweringTransforms (which rely on inputForm and outputForm not being UnknownForm), but instead using the Dependency API. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-04-22Add ExpandPrepares wrapperSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-04-22Add IdentityLike mix-in for TransformLikeSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-04-22Add trait-based Dependency API migration pathSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-04-22Use private LinkedHashSets in DependencyManagerSchuyler Eldridge
Changes the DependencyManager to use the private[options] LinkedHashSet members that shadow the public Seq[_] dependencies. This should avoid some unnecessary set construction and also improves readability of the DependencyManager code. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-04-22Fix typo in private DependencyAPI memberSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-04-20Avoid using infix for mutable append in CheckWidthsAlbert Magyar
2020-04-20Ensure arguments to asClock / asAsyncReset are single-bitAlbert Magyar
2020-04-14Avoid infinite loops on async-reset self-inits in CheckResetsAlbert Magyar
* Fixes #1516 * Tighten up logic for "casted literal" checking
2020-04-14Allow casts in AsyncReset literal value check (#1523)Jack Koenig
Chisel emits all literals as UInts cast to the correct type, make CheckResets support casts when checking that async reset registers are reset to literal values. Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-04-13Ensure PadWidths is run in mverilog compilerAlbert Magyar
2020-04-13Check EmitAnnotation class before emittingSchuyler Eldridge
Fixes a bug where an Emitter was only checking for the presence of an EmitCircuitAnnotation or EmitAllModulesAnnotation to control its emission flavor (one-file-per-module or one-file). This changes the check to ensure that the class of emitter matches that of the annotation. This allows for correct behavior when mixing different emitters, e.g., -E high -e middle. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-04-13Split Checks into separate filesAlbert Magyar
2020-04-13Split Resolves into separate filesAlbert Magyar
* Remove unused imports
2020-04-13move asyncInitials inside initial block RANDOMIZE ifdef (#1510)John Ingalls
2020-04-11EliminateTargetPaths: don't duplicate modules with only one instance (#1504)Albert Chen
* EliminateTargetPaths: add lone instance test cases * EliminateTargetPaths: don't rename lone instances * get rid of trailing comma Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-04-10Split Passes.scala into separate files (#1496)Adam Izraelevitz
* Split Passes.scala into separate files * Add imports of implicit things Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-04-10Add ground type serializer (#1502)Albert Chen
* update JsonProtocolSpec to test GroundType * add custom serializer for GroundType * get rid of trailing comma Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-04-10Support infoMode for Strings (#782)edwardcwang
* Support infoMode for Strings It seemed like an API hole that I couldn't use infoMode with a string but had to manually create an iterator first. * Fix build error Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu>
2020-04-07Fix dynamic SubAccess of zero-length vectors (#1450)Albert Magyar
* Fix dynamic SubAccess of zero-length vectors * Fixes #230 * Add new ZeroLengthVecs pass that occurs before RemoveAccesses * Include this in stage.Forms.MidForm * Add to High->Mid order in compiler test based on @seldridge feedback * Use validif to produce out-of-bounds value in ZeroLengthVecs * Update scaladoc * Fix test imports
2020-04-06* Remove deprecated 'Gender' methods/aliasesAlbert Magyar
2020-04-06Remove deprecated ResolveGenders and CheckGendersAlbert Magyar
* Remove few remaining uses of these passes from FIRRTL codebase
2020-04-06Avoid using deprecated 'Gender' objectsAlbert Magyar
* Remove 'gender' as pattern match binding
2020-03-30Make InlineCasts invalidate LegalizeClocksAlbert Magyar
2020-03-30Avoid generating illegal part-selects in InlineCastsAlbert Magyar
2020-03-30Don't use postfix operator in transforms.FlattenSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-03-26Eliminate warnings on `sbt doc` and `sbt unidoc` (#1470)Chick Markley
* Eliminate warnings on `sbt doc` and `sbt unidoc` - removed toFirrtl reference on MultiTargetAnnotation - lots of places where package path has to be added to comment references - Change to use `/** text starts here` convention when wrong in comment with a doc fix. - Did not exhaustively change these - Wrestled doc example in RenderDiGraph#renderNode, not sure if I won - Cleaned up InferWidths & CatchExceptions imports - Added missing license message to a couple of files. - fixed a couple of stale parameter names in scaladoc - Added @unchecked to stop erasure warning in Emitting where emission annotations are collected - Change types to [_] on match in RenameMap#recordAll to fix erasure warning * Where possible change [[firrtl.ir.X]] to [[firrtl.ir.X X]] for better display in scaladoc Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-03-26Support octal and binary literal formats as described in the specAlbert Magyar
* Fixes #1464
2020-03-23Support Java API doc Scaladoc/Unidoc References (#1420)Schuyler Eldridge
* Link to Java API Documentation This adds a build.sbt apiMappings to allow for Scaladoc/Unidoc linking to Java API documentation. This uses the exact strategy that Scala upstream uses for linking. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Add example of Java and Scala API docs linking Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-03-23Remove toNamed (and friends) deprecation. (#1449)Jim Lawson
* Remove toNamed (and friends) deprecation. * Add inadvertently deleted leading double quote. * Remove commented out deprecations.
2020-03-23Explicitly initialize firrtl.stage.Forms to prevent multi-thread collisions ↵Jim Lawson
(#1463) * Explicitly initialize firrtl.stage.Forms to prevent multi-thread collisions See https://github.com/freechipsproject/firrtl/issues/1462. Convert `lazy val` members of firrtl.stage.Forms to plan `val`s. Reference firrtl.stage.Forms in sufficient locations to ensure the object is initialized before its members are accessed. * Respond to comments - make _dummyForms private. * Move Forms initialization to package object. * Merge with master
2020-03-23Change annotation logging (#1461)Jack Koenig
* Change from log-level debug to trace * Serialize as JSON rather than .serialize on each annotation Co-Authored-By: Chick Markley <chick@qrhino.com>
2020-03-17Add method to CheckCompLoops which returns its full netlist (#1458)David Biancolin
2020-03-16Check for collision of defnames with Module namesAlbert Magyar
* Fixes #1096
2020-03-16Check for module name conflictsAlbert Magyar
* Fixes #1436
2020-03-13Make InlineInstances invalidate ResolveKindsJack Koenig
Fixes #1453
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