diff options
| author | Murali Vijayaraghavan | 2020-05-13 09:47:47 -0700 |
|---|---|---|
| committer | GitHub | 2020-05-13 16:47:47 +0000 |
| commit | 96fbaf5025ab337a6fc151795f49c1891f79a91e (patch) | |
| tree | c8b0cde148815fc438891ac0c1d684de56475a47 /src/main | |
| parent | d7631649488d24b5edbbb8c8de251f8e652f6304 (diff) | |
consolidated wire+assign to just wire, with expression inlined (#1600)
* consolidated wire <type> x; assign x = y; to wire <type> x = y;
* Remove dead code from Emitter.scala
Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
Diffstat (limited to 'src/main')
| -rw-r--r-- | src/main/scala/firrtl/Emitter.scala | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala index 84f11eef..f97ab7ca 100644 --- a/src/main/scala/firrtl/Emitter.scala +++ b/src/main/scala/firrtl/Emitter.scala @@ -874,8 +874,7 @@ class VerilogEmitter extends SeqTransform with Emitter { if (!options.disableRandomization) initialize(e, sx.reset, sx.init) case sx: DefNode => - declare("wire", sx.name, sx.value.tpe, sx.info) - assign(WRef(sx.name, sx.value.tpe, NodeKind, SourceFlow), sx.value, sx.info) + declare("wire", sx.name, sx.value.tpe, sx.info, sx.value) case sx: Stop => simulate(sx.clk, sx.en, stop(sx.ret), Some("STOP_COND"), sx.info) case sx: Print => |