From 96fbaf5025ab337a6fc151795f49c1891f79a91e Mon Sep 17 00:00:00 2001 From: Murali Vijayaraghavan Date: Wed, 13 May 2020 09:47:47 -0700 Subject: consolidated wire+assign to just wire, with expression inlined (#1600) * consolidated wire x; assign x = y; to wire x = y; * Remove dead code from Emitter.scala Co-authored-by: Albert Magyar --- src/main/scala/firrtl/Emitter.scala | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'src/main') diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala index 84f11eef..f97ab7ca 100644 --- a/src/main/scala/firrtl/Emitter.scala +++ b/src/main/scala/firrtl/Emitter.scala @@ -874,8 +874,7 @@ class VerilogEmitter extends SeqTransform with Emitter { if (!options.disableRandomization) initialize(e, sx.reset, sx.init) case sx: DefNode => - declare("wire", sx.name, sx.value.tpe, sx.info) - assign(WRef(sx.name, sx.value.tpe, NodeKind, SourceFlow), sx.value, sx.info) + declare("wire", sx.name, sx.value.tpe, sx.info, sx.value) case sx: Stop => simulate(sx.clk, sx.en, stop(sx.ret), Some("STOP_COND"), sx.info) case sx: Print => -- cgit v1.2.3