diff options
Diffstat (limited to 'src/main')
| -rw-r--r-- | src/main/scala/firrtl/Emitter.scala | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala index 84f11eef..f97ab7ca 100644 --- a/src/main/scala/firrtl/Emitter.scala +++ b/src/main/scala/firrtl/Emitter.scala @@ -874,8 +874,7 @@ class VerilogEmitter extends SeqTransform with Emitter { if (!options.disableRandomization) initialize(e, sx.reset, sx.init) case sx: DefNode => - declare("wire", sx.name, sx.value.tpe, sx.info) - assign(WRef(sx.name, sx.value.tpe, NodeKind, SourceFlow), sx.value, sx.info) + declare("wire", sx.name, sx.value.tpe, sx.info, sx.value) case sx: Stop => simulate(sx.clk, sx.en, stop(sx.ret), Some("STOP_COND"), sx.info) case sx: Print => |