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authorDeborah Soung2020-05-05 12:48:05 -0700
committerGitHub2020-05-05 19:48:05 +0000
commite9073463dfe77746f23afdfe782e1143a5e5be9f (patch)
tree3fd2bcb93b388d2f1d28e0eae0bdd2616900186a /src/main
parentc9d49aa8a600a59f3cfc1dcfc9ec8729077d5107 (diff)
before/after initial block macros (#1550)
* adding init macros * fix missing tick * adding more documentation; fixing up emitter tests * adding initial-guarding macro test * prefixing macros with FIRRTL * cleanup * typo fix Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
Diffstat (limited to 'src/main')
-rw-r--r--src/main/scala/firrtl/Emitter.scala8
-rw-r--r--src/main/scala/firrtl/util/BackendCompilationUtilities.scala19
2 files changed, 25 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index 2ebf11b6..84f11eef 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -1029,6 +1029,10 @@ class VerilogEmitter extends SeqTransform with Emitter {
}
emit(Seq("`endif"))
emit(Seq("`ifndef SYNTHESIS"))
+ // User-defined macro of code to run before an initial block
+ emit(Seq("`ifdef FIRRTL_BEFORE_INITIAL"))
+ emit(Seq("`FIRRTL_BEFORE_INITIAL"))
+ emit(Seq("`endif"))
emit(Seq("initial begin"))
emit(Seq(" `ifdef RANDOMIZE"))
emit(Seq(" `ifdef INIT_RANDOM"))
@@ -1054,6 +1058,10 @@ class VerilogEmitter extends SeqTransform with Emitter {
for (x <- asyncInitials) emit(Seq(tab, x))
emit(Seq(" `endif // RANDOMIZE"))
emit(Seq("end // initial"))
+ // User-defined macro of code to run after an initial block
+ emit(Seq("`ifdef FIRRTL_AFTER_INITIAL"))
+ emit(Seq("`FIRRTL_AFTER_INITIAL"))
+ emit(Seq("`endif"))
emit(Seq("`endif // SYNTHESIS"))
}
diff --git a/src/main/scala/firrtl/util/BackendCompilationUtilities.scala b/src/main/scala/firrtl/util/BackendCompilationUtilities.scala
index 20a65895..91b88090 100644
--- a/src/main/scala/firrtl/util/BackendCompilationUtilities.scala
+++ b/src/main/scala/firrtl/util/BackendCompilationUtilities.scala
@@ -100,14 +100,16 @@ trait BackendCompilationUtilities extends LazyLogging {
* @param cppHarness C++ testharness to compile/link against
* @param suppressVcd specifies if VCD tracing should be suppressed
* @param resourceFileName specifies what filename to look for to find a .f file
+ * @param extraCmdLineArgs list of additional command line arguments
*/
- def verilogToCpp(
+ def verilogToCppWithExtraCmdLineArgs(
dutFile: String,
dir: File,
vSources: Seq[File],
cppHarness: File,
suppressVcd: Boolean = false,
- resourceFileName: String = firrtl.transforms.BlackBoxSourceHelper.defaultFileListName
+ resourceFileName: String = firrtl.transforms.BlackBoxSourceHelper.defaultFileListName,
+ extraCmdLineArgs: Seq[String] = Seq.empty
): ProcessBuilder = {
val topModule = dutFile
@@ -138,6 +140,7 @@ trait BackendCompilationUtilities extends LazyLogging {
"verilator",
"--cc", s"${dir.getAbsolutePath}/$dutFile.v"
) ++
+ extraCmdLineArgs ++
blackBoxVerilogList ++
vSourcesFiltered.flatMap(file => Seq("-v", file.getCanonicalPath)) ++
Seq("--assert",
@@ -160,6 +163,18 @@ trait BackendCompilationUtilities extends LazyLogging {
command
}
+ @deprecated("use verilogtoCppWithExtraCmdLineArgs","1.3")
+ def verilogToCpp(
+ dutFile: String,
+ dir: File,
+ vSources: Seq[File],
+ cppHarness: File,
+ suppressVcd: Boolean = false,
+ resourceFileName: String = firrtl.transforms.BlackBoxSourceHelper.defaultFileListName
+ ): ProcessBuilder = {
+ verilogToCppWithExtraCmdLineArgs(dutFile, dir, vSources, cppHarness, suppressVcd, resourceFileName)
+ }
+
def cppToExe(prefix: String, dir: File): ProcessBuilder =
Seq("make", "-C", dir.toString, "-j", "-f", s"V$prefix.mk", s"V$prefix")