Add missing invalidations to some transforms (#1541)

This adds missing invalidations to four transforms:

  - ExpandConnects
  - RemoveAccesses
  - SplitExpressions
  - VerilogMemDelays

This necessarily updates test cases which expect exact transform
orders to reflect the new order.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

4 files changed, 18 insertions, 8 deletions

diff --git a/src/main/scala/firrtl/passes/ExpandConnects.scala b/src/main/scala/firrtl/passes/ExpandConnects.scala
index f80c705c..d28e6399 100644
--- a/src/main/scala/firrtl/passes/ExpandConnects.scala
+++ b/src/main/scala/firrtl/passes/ExpandConnects.scala
@@ -2,16 +2,21 @@ package firrtl.passes
 
 import firrtl.Utils.{create_exps, flow, get_field, get_valid_points, times, to_flip, to_flow}
 import firrtl.ir._
-import firrtl.options.{PreservesAll, Dependency}
+import firrtl.options.Dependency
 import firrtl.{DuplexFlow, Flow, SinkFlow, SourceFlow, Transform, WDefInstance, WRef, WSubAccess, WSubField, WSubIndex}
 import firrtl.Mappers._
 
-object ExpandConnects extends Pass with PreservesAll[Transform] {
+object ExpandConnects extends Pass {
 
   override def prerequisites =
     Seq( Dependency(PullMuxes),
          Dependency(ReplaceAccesses) ) ++ firrtl.stage.Forms.Deduped
 
+  override def invalidates(a: Transform) = a match {
+    case ResolveFlows => true
+    case _            => false
+  }
+
   def run(c: Circuit): Circuit = {
     def expand_connects(m: Module): Module = {
       val flows = collection.mutable.LinkedHashMap[String,Flow]()
diff --git a/src/main/scala/firrtl/passes/RemoveAccesses.scala b/src/main/scala/firrtl/passes/RemoveAccesses.scala
index 176312d5..d5615260 100644
--- a/src/main/scala/firrtl/passes/RemoveAccesses.scala
+++ b/src/main/scala/firrtl/passes/RemoveAccesses.scala
@@ -23,8 +23,8 @@ object RemoveAccesses extends Pass {
          Dependency(ExpandConnects) ) ++ firrtl.stage.Forms.Deduped
 
   override def invalidates(a: Transform): Boolean = a match {
-    case Uniquify => true
-    case _        => false
+    case Uniquify | ResolveKinds | ResolveFlows => true
+    case _                                      => false
   }
 
   private def AND(e1: Expression, e2: Expression) =
diff --git a/src/main/scala/firrtl/passes/SplitExpressions.scala b/src/main/scala/firrtl/passes/SplitExpressions.scala
index 7124111b..c536cd5d 100644
--- a/src/main/scala/firrtl/passes/SplitExpressions.scala
+++ b/src/main/scala/firrtl/passes/SplitExpressions.scala
@@ -3,9 +3,9 @@
 package firrtl
 package passes
 
-import firrtl.{SystemVerilogEmitter, VerilogEmitter}
+import firrtl.{SystemVerilogEmitter, Transform, VerilogEmitter}
 import firrtl.ir._
-import firrtl.options.{Dependency, PreservesAll}
+import firrtl.options.Dependency
 import firrtl.Mappers._
 import firrtl.Utils.{kind, flow, get_info}
 
@@ -14,7 +14,7 @@ import scala.collection.mutable
 
 // Splits compound expressions into simple expressions
 //  and named intermediate nodes
-object SplitExpressions extends Pass with PreservesAll[Transform] {
+object SplitExpressions extends Pass {
 
   override def prerequisites = firrtl.stage.Forms.LowForm ++
     Seq( Dependency(firrtl.passes.RemoveValidIf),
@@ -24,6 +24,11 @@ object SplitExpressions extends Pass with PreservesAll[Transform] {
     Seq( Dependency[SystemVerilogEmitter],
          Dependency[VerilogEmitter] )
 
+  override def invalidates(a: Transform) = a match {
+    case ResolveKinds => true
+    case _            => false
+  }
+
    private def onModule(m: Module): Module = {
       val namespace = Namespace(m)
       def onStmt(s: Statement): Statement = {
diff --git a/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala b/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala
index 131a198b..dd644323 100644
--- a/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala
+++ b/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala
@@ -175,7 +175,7 @@ object VerilogMemDelays extends Pass {
          Dependency[SystemVerilogEmitter] )
 
   override def invalidates(a: Transform): Boolean = a match {
-    case _: transforms.ConstantPropagation => true
+    case _: transforms.ConstantPropagation | ResolveFlows => true
     case _ => false
   }