| Age | Commit message (Expand) | Author |
|---|
| 2016-09-23 | use .isEmpty, .nonEmpty, isDefined | chick |
| 2016-09-23 | use .indices | chick |
| 2016-09-23 | use .head instead of (0) | chick |
| 2016-09-22 | Fixed width inference for add, sub (#312) | Adam Izraelevitz |
| 2016-09-21 | Fix clock connections in InferReadWrite (#310) | Donggyu |
| 2016-09-21 | swap functions in MemPortUtils and MemTransformUtils properly for further ref... | Donggyu Kim |
| 2016-09-21 | refactor AnnotateValidMemConfigs | Donggyu Kim |
| 2016-09-21 | refactor ReplaceMemMacros | Donggyu Kim |
| 2016-09-21 | refactor UpdateDuplicateMemMacros | Donggyu Kim |
| 2016-09-21 | clean up ReplSeqMem | Donggyu Kim |
| 2016-09-21 | refactor AnnotateMemMacros | Donggyu Kim |
| 2016-09-21 | refactor InferReadWrite | Donggyu Kim |
| 2016-09-21 | generalize Analysis.getConnects for code resuse | Donggyu Kim |
| 2016-09-16 | fill empty module body with "begin end" (#305) | Yunsup Lee |
| 2016-09-15 | Fix non-determinism bug in ExpandWhens (#303) | Jack Koenig |
| 2016-09-14 | fix spaces in WIR.scala | Donggyu Kim |
| 2016-09-14 | style fixes for Compiler.scala, LoweringCompiler.scala | Donggyu Kim |
| 2016-09-14 | Fix for more general case of getConnectOrigin with reg feedback (#301) | Angie Wang |
| 2016-09-14 | fix enable signal inferecne for smems' read ports (#289) | Donggyu |
| 2016-09-14 | Fixed infinite loop for finding connect origin in ReplSeqMem (#300) | Angie Wang |
| 2016-09-13 | Fix a lurking width-inference bug; improve adjacent style (#298) | Andrew Waterman |
| 2016-09-13 | use BoolType for UIntType(IntWidth(1)) | Donggyu Kim |
| 2016-09-13 | remove VIndent | Donggyu Kim |
| 2016-09-13 | use case object for WVoid, WInvalid | Donggyu Kim |
| 2016-09-13 | cache IntWidths to avoid redudant object creations | Donggyu Kim |
| 2016-09-13 | use case object for Kind | Donggyu Kim |
| 2016-09-13 | clean up PadWidth | Donggyu Kim |
| 2016-09-13 | clean up LowerTypes | Donggyu Kim |
| 2016-09-13 | clean up Passes.scala | Donggyu Kim |
| 2016-09-13 | type aliases | Donggyu Kim |
| 2016-09-13 | remove Utils.{width_BANG, long_BANG} | Donggyu Kim |
| 2016-09-13 | remove Utils.get_type | Donggyu Kim |
| 2016-09-13 | use MemPortUtils.memType for DefMemory | Donggyu Kim |
| 2016-09-13 | remove Utils.{mapr, get_name} and fix spaces | Donggyu Kim |
| 2016-09-13 | MemPortUtils: return correct memory types | Donggyu Kim |
| 2016-09-13 | clean up MemUtils | Donggyu Kim |
| 2016-09-12 | Add legalization of pad operation on literals. | Jack |
| 2016-09-12 | Cast bit select of SInt in PadWidths to SInt | Jack |
| 2016-09-12 | Legalize bit select. Run Legalize after PadWidths. | Jack |
| 2016-09-12 | Change Legalize Connect to respect SInt | Jack |
| 2016-09-12 | Change Legalize Shift Right to respect SInt | jackkoenig |
| 2016-09-12 | Change bitWidth to support ClockType | jackkoenig |
| 2016-09-12 | Add unapply for GroundType | jackkoenig |
| 2016-09-12 | Change Mappers to Value Classes | jackkoenig |
| 2016-09-12 | Rework map functions as class methods | jackkoenig |
| 2016-09-12 | Fixed bug where nodes of Invalids where created | azidar |
| 2016-09-12 | Bug fix -- remove all empty expressions after ReplSeqMem passes (#294) | Angie Wang |
| 2016-09-08 | Revert Expand Whens to process a set of connection lhs | jackkoenig |
| 2016-09-08 | memoize nodes in ExpandWhens | Donggyu Kim |
| 2016-09-08 | remove Utils.{AND, OR, NOT, EQV} | Donggyu Kim |
