diff options
| author | Donggyu | 2016-09-14 14:19:32 -0700 |
|---|---|---|
| committer | GitHub | 2016-09-14 14:19:32 -0700 |
| commit | 2c019e471ca19d472ca0243f206cba42a6d6efa1 (patch) | |
| tree | b600439ab4fe89ce46854252e325a7f66a1c8ed6 /src/main | |
| parent | 47cbab4b19df50eb47954c1ed37d15a339d37f8b (diff) | |
fix enable signal inferecne for smems' read ports (#289)
Diffstat (limited to 'src/main')
| -rw-r--r-- | src/main/scala/firrtl/passes/RemoveCHIRRTL.scala | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala b/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala index 6eeb6e96..485664b4 100644 --- a/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala +++ b/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala @@ -195,6 +195,8 @@ object RemoveCHIRRTL extends Pass { case DefNode(info, name, value) => val valuex = remove_chirrtl_e(MALE)(value) val sx = DefNode(info, name, valuex) + // Check node is used for read port address + remove_chirrtl_e(FEMALE)(Reference(name, value.tpe)) has_read_mport match { case None => sx case Some(en) => Block(Seq(sx, Connect(info, en, one))) |