From 2c019e471ca19d472ca0243f206cba42a6d6efa1 Mon Sep 17 00:00:00 2001
From: Donggyu
Date: Wed, 14 Sep 2016 14:19:32 -0700
Subject: fix enable signal inferecne for smems' read ports (#289)

---
 src/main/scala/firrtl/passes/RemoveCHIRRTL.scala | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'src/main')

diff --git a/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala b/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala
index 6eeb6e96..485664b4 100644
--- a/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala
+++ b/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala
@@ -195,6 +195,8 @@ object RemoveCHIRRTL extends Pass {
       case DefNode(info, name, value) =>
         val valuex = remove_chirrtl_e(MALE)(value)
         val sx = DefNode(info, name, valuex)
+        // Check node is used for read port address
+        remove_chirrtl_e(FEMALE)(Reference(name, value.tpe))
         has_read_mport match {
           case None => sx
           case Some(en) => Block(Seq(sx, Connect(info, en, one)))
-- 
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