| Age | Commit message (Expand) | Author |
|---|
| 2016-08-15 | Remove stanza (#231) | Adam Izraelevitz |
| 2016-02-09 | Added license to FIRRTL files | azidar |
| 2016-02-09 | Added Expand Whens pass | azidar |
| 2016-02-09 | Changed stanza output of UInt/SInt to include widths. Made tests match accord... | azidar |
| 2016-01-28 | Changed rmode to wmode | azidar |
| 2016-01-28 | Changed mod to rem | azidar |
| 2016-01-28 | Updated with new primops. Removed addw,subw,quo,rem,bit. Added head,tail,asCl... | azidar |
| 2016-01-28 | Fixed readwriter syntax, and all printed mstats to use => instead of a colon | azidar |
| 2016-01-28 | Changed register syntax for optional reset and init values | azidar |
| 2016-01-27 | Reworked readwriter types | azidar |
| 2016-01-25 | Added isinvalid and validif | azidar |
| 2016-01-25 | Changed first generated name to use _0 postfix | azidar |
| 2016-01-24 | Added muxing on passive aggregate types | azidar |
| 2016-01-24 | Added DefMemory to CInfer Types | azidar |
| 2016-01-23 | Fixed bug where the write mask wasn't being generated correctly | azidar |
| 2016-01-23 | Changed chirrtl to not require known mask values | azidar |
| 2016-01-20 | WIP, need to update chirrtl with new mask syntax | azidar |
| 2016-01-16 | Added hashed on get flip | azidar |
| 2016-01-16 | Sped up some passes. Added global mname to allow easy per-module hashes for a... | azidar |
| 2016-01-16 | Finished first cut at new firrtl - time for testing! Chirrtl requires masks t... | azidar |
| 2016-01-16 | Fixed a bunch of tests, and minor bugs | azidar |
| 2016-01-16 | WIP Almost there, need to generate enable connections | azidar |
| 2016-01-16 | WIP. Fixed a bunch of tests. Starting on implementing chirrtl, but hit roadbl... | azidar |
| 2016-01-16 | WIP getting through tests | azidar |
| 2016-01-16 | Finished supporting nested accesses. Required some nuianced thinking. Pass al... | azidar |
| 2016-01-16 | WIP, hit semantic bug in WSubAccess | azidar |
| 2016-01-16 | New memory works with verilog. Slowly changing tests and fixing bugs. | azidar |
| 2016-01-16 | WIP. Compiles and almost done with verilog backend. Need to think about emitt... | azidar |
| 2016-01-16 | WIP. Compiles, need to test | azidar |
| 2016-01-16 | WIP | azidar |
| 2016-01-16 | WIP need to correctly output readwrite ports | azidar |
| 2016-01-16 | Finished adding clocks to Stop and Print | azidar |
| 2015-10-30 | Added support for -b <backend> so that specific passes can be run then a back... | jackkoenig |
| 2015-10-14 | Don't emit SystemVerilog keywords | Andrew Waterman |
| 2015-10-07 | Added Printf and Stop to firrtl. #23 #24. | azidar |
| 2015-10-06 | Merge pull request #45 from ucb-bar/change-mem-type | Adam Izraelevitz |
| 2015-10-01 | Changed DefMemory to be a non-vector type with a size member. Necessary for A... | azidar |
| 2015-09-30 | Fixed naming bug where __1 was matching. Caused lots o issues. | azidar |
| 2015-08-26 | Fixed bug where firrtl was incorrectly judging the width of a bigint. #36 #37. | azidar |
| 2015-08-25 | Removed IntWidth, now only use LongWidth. Now do width inference for Constant... | azidar |
| 2015-08-20 | Added Poison node. Includes tests. #26. | azidar |
| 2015-08-20 | Added rsh to BigInt library. Const Prop now works on rsh's on constants. #19. | azidar |
| 2015-08-19 | Switched to new bigint library | azidar |
| 2015-08-04 | Added verilog keywords to uniquify them | azidar |
| 2015-08-04 | Fixed reading from instance's input ports. Fixed unique naming bug. | azidar |
| 2015-08-03 | Changed name mangling to use _ as a delin. Fixed bug in checking for | azidar |
| 2015-08-03 | Fixed performance bug in Split Expressions. Changed delin for connect indexed... | azidar |
| 2015-07-30 | Added module name to error messages. | azidar |
| 2015-07-30 | Added eqv for bitwise equality, and change eq to be arithmetic equality | azidar |
| 2015-07-30 | Updated lots of tests so they pass. Found one bug in expand whens | azidar |
