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path: root/src/main/stanza/ir-utils.stanza
AgeCommit message (Expand)Author
2015-07-21Made things go faster. Still in progress. Expand when now removesAdam Izraelevitz
2015-07-17Datapath compiles with Chisel 2.0 -> FIRRTL -> Verilog!Adam Izraelevitz
2015-07-14Added clock supportazidar
2015-07-14Still partial commit, many tests pass. Many tests fail.azidar
2015-07-14In progress commitazidar
2015-07-02Fixed performance bugs, runs 7x fasterazidar
2015-06-02Changed Core.fir so dshl wasn't huge. Fixed padding pass to preserve correct ...azidar
2015-06-02Added sequential/combinational memories. Started debugging verilog backend. A...azidar
2015-05-27Added sequential memories. mem no longer exists, must declare either cmem or ...azidar
2015-05-27Added external modules. Switched lower firrtl back to wire r; r := Register, ...azidar
2015-05-26Added <>. Added additional checks for primops. Added new chisel3 files.azidar
2015-05-18Big API Change. Pad is no longer supported. Widths of primops can be flexible...azidar
2015-05-15Updated firrtl for its passes to be a bit more modular, and to enable pluggin...azidar
2015-05-13Added source indicators from FIRRTL files. Pass in -p i to get them printed. ...azidar
2015-04-29Added dshl and dshrazidar
2015-04-27Added on-resetazidar
2015-04-24Merge branch 'master' of github.com:ucb-bar/firrtl into parserazidar
2015-04-23Fixed bug in lowering where the arguments to DoPrim and Pad weren't loweredazidar
2015-04-23Fixed bug in map where mems were mysteriously turning into regsazidar
2015-04-23Not finished commmitazidar
2015-04-23Added new parser. Fixed all Tests. Added on-reset to parser, but don't correc...azidar
2015-04-22Switched to stricter primop width constraints. Implemented Pad. Added some mi...azidar
2015-04-20Fixed tests to use new execution arguments. Added and fixed chisel3 bugsazidar
2015-04-17Fixed bug in primop lowering during type inference. Added reduce instructions...azidar
2015-04-16Updated parser to correctly read empty statementsazidar
2015-04-16Merged with new stanzaazidar
2015-04-13Finished Infer Widthsazidar
2015-04-10Almost finished width inference, takes too long/infinite loop for gcdazidar
2015-04-10Updated StanzaPatrick Li
2015-04-09Added more 'fake' tests. infer-widths now collects constraintsazidar
2015-04-08Finished expand whens. started infer widths. added pdf for people to viewazidar
2015-03-27Corrected register init by adding initialization of registers pass after lowe...azidar
2015-03-25Finished expand-whens. Removed letrec also, a while agoazidar
2015-03-25Correctly do when expansion, minus enables and outputting lowered formazidar
2015-03-24Fixed minor bugs, but looks like there is a stanza bug. This blows. And sucks.azidar
2015-03-24With new stanzaazidar
2015-03-23Finished first two parts of expand-whens pass. Fixed inits by adding WRegInit...azidar
2015-03-12Switched bundles from gender to flipazidar
2015-03-11Finished expand accessors pass. Fixed bug in resolve-gender. Added tests, all...azidar
2015-03-05Finished part of infer gender, tests not committedazidar
2015-03-04Changed lots of directions to genders. Started writing infer-gender pass. Doe...azidar
2015-03-04Finished infer-types passazidar
2015-03-03In progress for type inference. Looks like other code is breaking, and i dont...azidar
2015-02-25Added debug print statements to dump fields from nodes, and updated tests to ...azidar
2015-02-20Rewrote the initialize-register pass, now correctly implementedazidar
2015-02-19Added compiler flags to allow tests to select which passes they test.azidar
2015-02-18Reimplemented to-working-ir. Changed Command to Stmt. Modified printing of IR...azidar
2015-02-13First commit.azidar