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AgeCommit message (Expand)Author
2016-02-09Adding ScalaTest for unit testing of Scala FIRRTL. Added a few basic tests fo...Jack
2016-02-09Fix bug in mem serializationJack
2016-02-09Fix start counting from 1 instead of 0 bugJack
2016-02-09Updated SInt/UInt emission to match stanza. Still need to update to new syntax.azidar
2016-02-09Fixed port emissionazidar
2016-02-09Moved passes to new packageazidar
2016-02-09Changed stanza output of UInt/SInt to include widths. Made tests match accord...azidar
2016-02-09Added remove accessesazidar
2016-02-09Restructure passes to be new subpackage with more modular design, add new str...Jack
2016-02-09Fix serialize bugs: WSub(Field|Index|Access) printing extraneous w, module no...Jack
2016-02-09Added expand connect. Resolve now includes to working irazidar
2016-02-09Added resolve gendersazidar
2016-02-09WIP. Finished to working ir, resolve kinds, and infer typesazidar
2016-02-09WIP. Got to-working-ir workingazidar
2016-02-09WIP, nothing works. Starting creating working IR and necessary utilsazidar
2016-01-29Fix no space after "flip" for flipped fields in Scala FIRRTL, also make Scala...Jack
2016-01-29Changed reg syntax to new "with" semantics in Scala FIRRTLJack
2016-01-28Add support for single-line and multi-line scoping to Scala FIRRTL preprocess...Jack
2016-01-28Fixed bug on translating SubAccess concrete syntax to abstract in Scala FIRRTLJack
2016-01-28WIP Added support for mux to Scala FIRRTLjackkoenig
2016-01-28WIP Added support for is invalid and validif to Scala FIRRTLjackkoenig
2016-01-28WIP Added support for stop to Scala FIRRTLjackkoenig
2016-01-28WIP Added support for printf to Scala FIRRTLjackkoenig
2016-01-28WIP: Added support for FIRRTL 0.2.0 Memories to Scala FIRRTLjackkoenig
2016-01-27WIP Moving Scala FIRRTL to match spec 0.2.0. Not everything is implemented (n...jackkoenig
2016-01-16Add warning that -p unusedducky
2016-01-16Clean up old logging remnantsducky
2016-01-16Import a logging library so we don't reinvent the wheel and have implicits fl...ducky
2016-01-16Refactor passes systemducky
2016-01-16Added notes for Richard to work onazidar
2016-01-16Merge branch 'scala' of github.com:ucb-bar/firrtlazidar
2016-01-16Added some commentsazidar
2015-12-11Add a renameall pass that renames nodes according to a user-providedPaul Rigge
2015-12-08Refactored MIDAS code into its own repojackkoenig
2015-12-07Fixed bug, I think transformation works now for the most partjackkoenig
2015-12-07The transformation works! Kind of, it works fine when everything is alwasy re...jackkoenig
2015-12-06Working on generating SimTop, need to figure out how to split the top-level I...jackkoenig
2015-12-04Everything is broken, need Translator to work on files without a circuit, nee...jackkoenig
2015-12-03Some stylistic changes and a couple bugfixes to simulation wrapper generationjackkoenig
2015-12-03New wrapper generator completejackkoenig
2015-12-03Changing simwrapper to group ports that go to different places, not quite the...jackkoenig
2015-12-03Seem to be able to generate simulation wrapper module from DefInstjackkoenig
2015-12-02Added fame transformation and new package, making progressjackkoenig
2015-11-24In process of adding FAME-1 transformation, updated todos in grammar file, up...jackkoenig
2015-11-23Rename Test.scala to Driver.scalajackkoenig
2015-10-15Reorganized Primops (renamed from PrimOps), added maps and functions to conve...Jack
2015-10-15Added infer-types pass, seems to work. Added infer-types error checking, modi...Jack
2015-10-14Modified getType to return Type rather than Option[Type] which makes more sen...Jack
2015-10-14Moved Logger to new private object DebugUtils, changed UInt/SInt value printi...Jack
2015-10-12Added initial support for debug printing for lit based testing, most types of...Jack
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