| Age | Commit message (Collapse) | Author |
|---|
|
Also rename --Wno-scala-version-warning to
--warn:no-scala-version-deprecation and adopt naming convention where
resulting annotation matches the CLI option
|
|
|
|
|
|
* Restore depth-agnostic inlining for simple 'lhs = ref' bool assignments
* Address review comments
* Run scalafmt
|
|
The following conditions must be satisfied to inline:
1. has type Utils.BoolType
2. is bound to a DefNode with name starting with '_'
3. is bound to a DefNode with a source locator that
points at the same file and line number. If it is a MultiInfo source
locator, the set of file and line number pairs must be the same. Source
locators may point to different column numbers.
4. InlineBooleanExpressionsMax has not been exceeded
5. is not a Mux
Also updates the Verilog emitter to break up lines greater than 120 characters
|
|
* Elide emission of literals for async reset in sensitivity lists
* Deprecate LegalizeClocksTransform
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
|
|
|
|
|
|
* Utils: add to_dir helper function
* firrt.SymbolTable trait for scanning declarations
* ir: RefLikeExpression trait to represent SubField, SubIndex, SubAccess and Reference nodes
* add new implementation of the LowerTypes pass
* replace LowerTypes with NewLowerTypes
* remove dependencies on Uniquify
* GroupComponentSpec: GroupComponents is run before lower types
* NewLowerTypes: address Adam's suggestions
* LoweringCompilerSpec: Uniquify was removed and NewLowerTypes
* LowerTypesSpec: add newline at the end of file
* LowerTypesSpec: port Uniquify tests to combined pass
* NewLowerTypes: ensure that internal methods are not visible
* NewLowerTypes: extend DependencyAPIMigration
* NewLowerTypes: lower ports without looking at the body
* LowerTypesSpec: use TransformManager instead of hard coded passes.
* NewLowerTypes: names are already assumed to be part of the namespace
* LowerTypesSpec: test name clashes between ports and nodes, inst, mem
* NewLowerTypes: correctly rename nodes, mems and instances that clash with port names
* NewLowerTypes: Iterable[String] instead of Seq[String] for 2.13
* NewLowerTypes: add a fast path for ground types without renaming
* LowerTypesSpec: remove trailing commans for 2.11
* LowerTypesSpec: explain why there are two
* Uniquify: use loweredName from NewLowerType
* replace old LowerTypes pass with NewLowerTypes pass
* Uniquify: deprecate pass usage
There are some functions that are still used by other passes.
* LowerTypes: InstanceKeyGraph now has a private constructor
* LowerTypes: remove remaining references to NewLowerTypes
* LoweringCompilerSpec: fix transform order to LowerTypes
* SymbolTable: add improvements from PR
* LoweringCompilerSpec: ignore failing CustomTransform tests
|
|
Remove all prerequisites and optionalPrerequisites from
BlackBoxSourceHelper. These were false dependencies that were added
without me actually looking at what the transform does.
BlackBoxSourceHelper is an identity transform that only performs IO
side effects based on Chisel-generated annotations. Therefore this
transform can literally run anytime it wants without consequence.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
|
|
* InstanceKeyGraph: add staticInstanceCount, getGraph and getChildrenInstanceMap
* InstanceKeyGraph: reachableModules, unreachableModules, lowestCommonAncestor and fullHierarchy
* Replace usage of InstanceGraph with InstanceKeyGraph
Also deprecates all unused methods.
* WiringUtils: make new version of sinksToSources package private
This will make our live easier next time we need to change it.
* CircuitGraph: use InstanceKeyGraph
* InstanceKeyGraphSpec: respect maximum line width
* InstanceKeyGraph: make constructor private
* InstanceKeyGraph: move lowestCommonAncestor function to Wiring
* WiringUtils: update deprecation message
|
|
* Avoid repeated inlining in FlattenRegUpdate
When-else structure can lead to the same complex mux structure being
the default on several branches in register update logic. When these are
inlined, it can lead to artifical unreachable branches that show up as
coverage holes in coverage of the emitted Verilog. This commit changes
the inlining logic to prevent inlining any reference expression that
shows up multiple times because this is a common indicator of the
problematic case.
* Add tests for improved register update logic emission
* Improve FlattenRegUpdate comment and add more tests
* [skip formal checks] ICache equivalence check verified locally
|
|
|
|
|
|
|
|
|
|
invalidation (#1797)
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
|
|
* add const prop bitwise reduction equivalence test
* mask negative literals when propagating reduction
* change widths
* get rid of unnecessary if
* add BigInt mask utility
|
|
* ConstProp: test bitwise op of signed literals
* ConstProp: use bit mask for FoldOr/FoldXor
* handle and also
* add UIntLiteral.masked helper
Co-authored-by: Jack Koenig <koenig@sifive.com>
|
|
* dedup: add faster InstanceGraph implementation and use it in dedup
The new implementation takes care not to hash the instance
types contained in DefInstance nodes.
This should make dedup considerably faster.
* FastInstanceGraph: cache vertices for faster findInstancesInHierarchy
* FastInstanceGraph: remove the parent name field since it isn't actually necessary
* FastInstanceGraph -> InstanceKeyGraph
* InstanceGraph: describe performance problems.
* InstanceKeyGraph: turn moduleMap into a def instead of a val
This will make changing implementation details much easier
in the future.
* InstanceKeyGraph: return childInstances as Seq instead of Map
This ensures a deterministic iteration order and it
can easily be turned into a Map for O(1) accesses.
* InstanceKeyGraph: add tests for public methods
* InstanceKeyGraph: group public methods together
* InstanceKeyGraphSpec: fix wording of a comment
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
|
|
* [WIP] Propagate source locators to Verilog if-else emission
* Add and fix tests for reg update info propagation
* Add limited source locator propagation in ConstProp
Support propagating source locators on connections or nodes where the
right-hand side is simply a reference. This case comes up a lot for
registers without a synchronous reset.
node _T_1 = x @[MyFile.scala 12:10]
node _T_2 = _T_1
z <= x
Previousy the source locator would be lost, now the result is:
z <= x @[MyFile.scala 12:10]
* Address review comments
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
|
|
Add an optionalPrerequisiteOf to TopWiringTransform pointing at
LowerTypes.
This fixes a bug where top-wired wire bundles with flips could result
in the top-wired, flattened bundle having every field with an "output"
direction if the TopWiringTransform is moved around in the transform
order (see FIRRTL issue #1744).
Why did this happen?
Fundamentally, this stems from the fact that LowerTypes preserves
bundle direction for ports, but destroys it for wires.
Specifically, The TopWiringTransform creates ports of the "output"
direction that are copies of the underlying type of the component
being top-wired. Before LowerTypes, the type of a bundle has direction
information via flips. After LowerTypes, the lowered ground type does
not have this information. Therefore, all the ports are ground type
outputs. Simply ensuring that TopWiringTransform must run before
LowerTypes avoids this problem.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
|
|
* benchmark: add hot.DedupBenchmark
* dedup: use structural md5 hash instead of agnostify and serialize
* StructuralHash: generate PrimOp LUT
* StructuralHash: change MessageDigestHasher to not be a case class
* StructuralHash: we want Blocks and EmptyStmt to be ignored
* StructuralHash: use SHA-256 instead of MD5
* StructuralHash: clarify extmodule port name agnistification
* StructuralHash: hash the name of width vars instead of trying to agnostify
This should be in line with the old Dedup behavior.
The prior use of n(..) was incorrect since the namespace
of these vars is different from the normal module scope namespace.
* StructuralHash: address Schuyler's review comments
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
|
|
Fix a bug where a type check would always yield true. This caused a
bug where allow/block-list annotations would be incorrectly applied to
all subtypes of ManipulateNames.
The tests are updated to check that this now works.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
|
|
* ConvertAsserts maps each assert into a gated print-and-stop
* ConvertAsserts is an optional prereq of RemoveVerificationStatements
* ConvertAsserts generates Low FIRRTL
* Drop print for asserts that have an empty message
* Fix scaladoc formatting from review
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
|
|
Add a new annotation that stores the resulting name of an allowlist
name to be manipulated.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
|
|
Rewrite of RemoveKeywordCollisions into a more generic
ManipulateNames. The new ManipulateNames transform is abstract in a
'(String, Namespace) => String' method that can be used for arbitrary
manipulation of names in a circuit. The software architecture remains
mostly the same (a rename map is used as the underlying data store).
However, the new ManipulateNames used Target as opposed to Named.
Add the ability for naming to be selectively enabled or disabled via:
- ManipulateNamesAllowlistAnnotation
- ManipulateNamesBlocklistAnnotation
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
|
|
message (#1717)
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
|
|
If a module has ports of type Bundle that are used in aggregate
connections in parent modules, Dedup cannot change the names of the
fields of the Bundle or it would change the semantics of the connection.
Dedup now detects this case and refrains from agnostifying the ports of
such modules to prevent this issue.
|
|
* Add assume, assert, cover statements
* Assert submodule assumptions
* Add warning when removing verification statements
* Remove System Verilog behaviour emitter warning
* Add option to disable AssertSubmoduleAssumptions
* Document verification statements in the spec
The syntax for the new statements is
assert(clk, cond, en, msg)
assume(clk, cond, en, msg)
cover(clk, cond, en, msg)
With assert as a representative example, the semantics is as follows:
`clk` is the clock, `cond` is the expression being asserted, `en` is the
enable signal (if `en` is low then the assert is not checked) and `msg`
is a string message intended to be reported as an error message by the
model checker if the assertion fails.
In the Verilog emitter, the new statements are handled by a new
`formals` map, which groups the statements by clock domain. All model
checking statements are then emitted within the context of an `ifdef
FORMAL` block, which allows model checking tools (like Symbiyosys) to
utilize the statements while keeping them out of synthesis flows.
Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
|
|
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
|
|
{Lower,Upper}CaseNames Transforms (#1651)
* Revert "Add test of {Lower, Upper}CaseNames"
This reverts commit 93c078b8469bc55cd2d33147c33e2b5421fda9d9.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
* Revert "Add --change-name-case <lower|upper> option"
This reverts commit d3ab7e2db66fe3a63778f427dad6c08f64695ba5.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
* Revert "Add features.{LowerCaseNames, UpperCaseNames} transforms"
This reverts commit c8dcdacf313f19a4d0238be694478a325432edd4.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
* Revert "Refactor RemoveKeywordCollisions->ManipulateNames"
This reverts commit c534c5abae7b80a725ec9925569b3383b3c24a34.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
|
|
Fix a performance bug in DedupModules introduced in #1539. Stop
recalculating the same expensive datastructures for each module,
potentially multiple times.
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
|
|
- RenameMap Behavior
-- Prevent transitive renaming A -> B -> C (continueRenaming)
-- Prevent transitive renaming for self-renames
- Target
-- Override toString as serialize for CompleteTarget
-- Expansion of stripHierarchy to enable stripping InstanceTargets to become ModuleTargets
Annotations
-- Bugfix in extractComponents where Products were not iterated over
-- Converts renamed targets to local targets using Target.referringModule to preserve sticky behavior
- Eliminate Target Paths
-- Make DuplicationHelper use LinkedHashMap, as we iterate over its contents and convert to Seq in def makePathless
-- Add DupedResult to map original module to new module targets
-- Update renaming to record a map from all relative instance paths to original module, to new module target
-- Consumes DedupedResult to give better name to new duplicated module if it was originally deduplicated
-- Reorder modules in attempt to preserve original ordering, pre-deduplication
-- Move utility functions to object
-- Bugfix: add self-renames to prevent ofModule _ of target _ cannot be renamed to Vector(_, _, _, ...) errors
- Dedup
-- Changed NoDedupAnnotation to contain ModuleTarget, rather than ModuleName
-- Added DedupedResult to map original module to the duplicate module
-- Consumes DupedResult to pick better name, if it existed
-- Updates renaming to chain the following: instancify deduped modules, remap differently named internal signals, then remap AST modules
-- Move utility functions to object
-- Remove annotations as part of determination of dedup correctness
-- Bugfix: add instance renames so that deduped modules have their instances properly renamed
- Dead Code Elimination
-- Add deletion of ASTModules
- Tests
-- Morphism Spec to ensure Dedup -> EliminateTargetPaths and EliminateTargetPaths -> Dedup patterns work properly
-- Update existing tests to make sure they work properly
-- Add Dedup tests to demonstrate instance renaming bug, EliminateTargetPaths for ofModule rename bug, and update RenameMap tests
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-authored-by: Adam Izraelevitz <adam.izraelevitz@sifive.com>
Co-authored-by: Adam Izraelevitz <azidar@gmail.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
|
|
* Absorb WRef into Reference
* Absorb WSubField into SubField
* Absorb WSubIndex into SubIndex
* Absorb WSubAccess into SubAccess
* Absorb WDefInstance into DefInstance
------------------------- API CHANGE SEVERITY --------------------------
This is projected to not break source-level compatibility with any known
user code. However, it will break *binary* compatibility with all
existing user FIRRTL passes, as is generally allowed with major
releases of FIRRTL.
--------------------------- DESCRIPTION --------------------------------
Previously, there were several nodes in WIR.scala that had a one-to-one
correspondance with existing nodes in the standard firrtl.ir hierarchy.
These nodes would have a case class resembling the corresponding
standard IR node, but with the addition of one or more "analysis"
fields.
Since these fields (such as kind) represent helpful info that can be
invalidated or set to Unknown (e.g. UnknownKind for Kind), it does not
cause any issues to simply include these fields on any in-memory
representation of FIRRTL IR. Although other systems for tracking FIRRTL
analyses have evolved over time, the ubiquity of pattern-matching on
these fields has lead most core and custom transforms to be written
against WIR, rather than IR.
This PR unifies the IRs by adding the fields that would be in an
"augmented" WIR node directly into the corresponding IR node; i.e., the
"type" and "kind" fields from WRef are added directly to the definition
of the Reference case class, while these "repetitive" WIR case classes
are removed entirely.
-------------------- SOURCE-COMPATIBILITY ADAPTERS ---------------------
Several object methods are added to WIR.scala to maintain
source-compatiblity for passes that used WIR. These objects define
factory methods and unapply methods, so passes that relied on implicit
case class factories or pattern matching for the removed WIR types will
remain perfectly source-compatible. However, these do not guarantee
compatibility at the binary level.
The types of the removed WIR case classes are also added as type aliases
to the top-level firrtl package, which allows code that relies on
explicit constructor calls or reflection to retain source-compatibility.
Finally, additional explicit factory methods are added to the companion
objects of the newly-augmented IR case classes, which allows user code
to avoid having to specify any of the new analysis fields. Existing code
that created non-WIR IR nodes will be able to continue using the
previous factory signatures, which will cause all omitted analysis
fields to be set to Unknown.
---------------------- UNMITIGATED API CHANGES -------------------------
While passes that used WIR will be source-compatible with this change,
there is one significant change that affects any pass currently using
non-WIR IR: the signatures of pattern-matching cases for Reference,
SubField, SubIndex, SubAccess, and DefInstance must change to
accommodate the extra fields.
This cannot be worked at the API level due to restrictions on unapply
overloading, but it could theoretically be solved with macros or other
static rewriting. However, only four core transforms (RemoveProto,
ToWorkingIR, Dedup, and RemoveChirrtl) use non-WIR IR, and it is
expected that no user code currently relies on it, so the expected
migration strategy is simply to change the small fraction of code
relying on these nodes.
|
|
* RenameMap: remove implicit rename chaining
* RenameMap: remove trailing comma
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
|
|
|
|
|
|
* Fixes #1561
* Add test for zero-reset reg from #1561
|
|
|
|
|
|
Creates the features package and populates it with two new transforms:
LowerCaseNames and UpperCaseNames. These transforms convert all names
in a FIRRTL circuit to lower case or upper case. This is intended to
help align generated Verilog with the policies of the
company/institution using it.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
squash! Add LowerCaseNames and UpperCaseNames transforms
|
|
Generalize the operations of the RemoveKeywordCollisions transform
into a new ManipulateNames transform. The ManipulateNames transform is
an abstract transform for making conditional modifications to
keywords/names in a FIRRTL circuit.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
|
|
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
|
|
Workaround for https://github.com/verilator/verilator #2300
present in Verilator versions v4.026 - v4.032. This transform turns AND
reductions for expressions > 64-bits into an equality check with all
ones. It is included as a prerequisite for all Verilog emitters.
|
|
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
|
|
This mixes in the new DependencyAPIMigration trait into all Transforms
and Passes. This enables in-tree transforms/passes to build without
deprecation warnings associated with the deprecated CircuitForm.
As a consequence of this, every Transform now has UnknownForm as both
its inputForm and outputForm. This PR modifies legacy Compiler and
testing infrastructure to schedule transforms NOT using
mergeTransforms/getLoweringTransforms (which rely on inputForm and
outputForm not being UnknownForm), but instead using the Dependency
API.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
|
|
* Remove 'gender' as pattern match binding
|
|
|
|
|
