diff options
| author | Schuyler Eldridge | 2020-05-11 19:11:11 -0400 |
|---|---|---|
| committer | Schuyler Eldridge | 2020-05-13 15:57:19 -0400 |
| commit | c8dcdacf313f19a4d0238be694478a325432edd4 (patch) | |
| tree | 76dc16e032e929c6dded521711404ce79db0de3c /src/main/scala/firrtl/transforms | |
| parent | c534c5abae7b80a725ec9925569b3383b3c24a34 (diff) | |
Add features.{LowerCaseNames, UpperCaseNames} transforms
Creates the features package and populates it with two new transforms:
LowerCaseNames and UpperCaseNames. These transforms convert all names
in a FIRRTL circuit to lower case or upper case. This is intended to
help align generated Verilog with the policies of the
company/institution using it.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
squash! Add LowerCaseNames and UpperCaseNames transforms
Diffstat (limited to 'src/main/scala/firrtl/transforms')
| -rw-r--r-- | src/main/scala/firrtl/transforms/ManipulateNames.scala | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/transforms/ManipulateNames.scala b/src/main/scala/firrtl/transforms/ManipulateNames.scala index df6ad177..1d628881 100644 --- a/src/main/scala/firrtl/transforms/ManipulateNames.scala +++ b/src/main/scala/firrtl/transforms/ManipulateNames.scala @@ -6,9 +6,7 @@ import firrtl._ import firrtl.analyses.InstanceGraph import firrtl.annotations.{Named, CircuitName, ModuleName, ComponentName} import firrtl.Mappers._ -import firrtl.options.Dependency import firrtl.passes.PassException -import firrtl.stage.Forms import scala.collection.mutable |