From c8dcdacf313f19a4d0238be694478a325432edd4 Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Mon, 11 May 2020 19:11:11 -0400 Subject: Add features.{LowerCaseNames, UpperCaseNames} transforms Creates the features package and populates it with two new transforms: LowerCaseNames and UpperCaseNames. These transforms convert all names in a FIRRTL circuit to lower case or upper case. This is intended to help align generated Verilog with the policies of the company/institution using it. Signed-off-by: Schuyler Eldridge squash! Add LowerCaseNames and UpperCaseNames transforms --- src/main/scala/firrtl/transforms/ManipulateNames.scala | 2 -- 1 file changed, 2 deletions(-) (limited to 'src/main/scala/firrtl/transforms') diff --git a/src/main/scala/firrtl/transforms/ManipulateNames.scala b/src/main/scala/firrtl/transforms/ManipulateNames.scala index df6ad177..1d628881 100644 --- a/src/main/scala/firrtl/transforms/ManipulateNames.scala +++ b/src/main/scala/firrtl/transforms/ManipulateNames.scala @@ -6,9 +6,7 @@ import firrtl._ import firrtl.analyses.InstanceGraph import firrtl.annotations.{Named, CircuitName, ModuleName, ComponentName} import firrtl.Mappers._ -import firrtl.options.Dependency import firrtl.passes.PassException -import firrtl.stage.Forms import scala.collection.mutable -- cgit v1.2.3