Convert PreservesAll to explicit invalidates=false

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

16 files changed, 55 insertions, 34 deletions

diff --git a/src/main/scala/firrtl/transforms/BlackBoxSourceHelper.scala b/src/main/scala/firrtl/transforms/BlackBoxSourceHelper.scala
index 322634dd..d8d4a12b 100644
--- a/src/main/scala/firrtl/transforms/BlackBoxSourceHelper.scala
+++ b/src/main/scala/firrtl/transforms/BlackBoxSourceHelper.scala
@@ -6,7 +6,6 @@ import java.io.{File, FileNotFoundException, FileInputStream, FileOutputStream,
 
 import firrtl._
 import firrtl.annotations._
-import firrtl.options.PreservesAll
 
 import scala.collection.immutable.ListSet
 
@@ -55,7 +54,7 @@ class BlackBoxNotFoundException(fileName: String, message: String) extends Firrt
   * will set the directory where the Verilog will be written.  This annotation is typically be
   * set by the execution harness, or directly in the tests
   */
-class BlackBoxSourceHelper extends Transform with DependencyAPIMigration with PreservesAll[Transform] {
+class BlackBoxSourceHelper extends Transform with DependencyAPIMigration {
   import BlackBoxSourceHelper._
   private val DefaultTargetDir = new File(".")
 
@@ -65,6 +64,8 @@ class BlackBoxSourceHelper extends Transform with DependencyAPIMigration with Pr
 
   override def optionalPrerequisiteOf = Seq.empty
 
+  override def invalidates(a: Transform) = false
+
   /** Collect BlackBoxHelperAnnos and and find the target dir if specified
     * @param annos a list of generic annotations for this transform
     * @return BlackBoxHelperAnnos and target directory
diff --git a/src/main/scala/firrtl/transforms/CheckCombLoops.scala b/src/main/scala/firrtl/transforms/CheckCombLoops.scala
index 29f9ffdb..dbfd5cf8 100644
--- a/src/main/scala/firrtl/transforms/CheckCombLoops.scala
+++ b/src/main/scala/firrtl/transforms/CheckCombLoops.scala
@@ -12,7 +12,7 @@ import firrtl.annotations._
 import firrtl.Utils.throwInternalError
 import firrtl.graph._
 import firrtl.analyses.InstanceGraph
-import firrtl.options.{Dependency, PreservesAll, RegisteredTransform, ShellOption}
+import firrtl.options.{Dependency, RegisteredTransform, ShellOption}
 
 /**
   * A case class that represents a net in the circuit. This is necessary since combinational loop
@@ -100,8 +100,7 @@ case class CombinationalPath(sink: ReferenceTarget, sources: Seq[ReferenceTarget
   */
 class CheckCombLoops extends Transform
     with RegisteredTransform
-    with DependencyAPIMigration
-    with PreservesAll[Transform] {
+    with DependencyAPIMigration {
 
   override def prerequisites = firrtl.stage.Forms.MidForm ++
     Seq( Dependency(passes.LowerTypes),
@@ -112,6 +111,8 @@ class CheckCombLoops extends Transform
 
   override def optionalPrerequisiteOf = Seq.empty
 
+  override def invalidates(a: Transform) = false
+
   import CheckCombLoops._
 
   val options = Seq(
diff --git a/src/main/scala/firrtl/transforms/CombineCats.scala b/src/main/scala/firrtl/transforms/CombineCats.scala
index 009f52ff..7fa01e46 100644
--- a/src/main/scala/firrtl/transforms/CombineCats.scala
+++ b/src/main/scala/firrtl/transforms/CombineCats.scala
@@ -7,7 +7,6 @@ import firrtl.Mappers._
 import firrtl.PrimOps._
 import firrtl.WrappedExpression._
 import firrtl.annotations.NoTargetAnnotation
-import firrtl.options.PreservesAll
 import firrtl.options.Dependency
 
 import scala.collection.mutable
@@ -53,7 +52,7 @@ object CombineCats {
   * Use [[MaxCatLenAnnotation]] to limit the number of elements that can be concatenated.
   * The default maximum number of elements is 10.
   */
-class CombineCats extends Transform with DependencyAPIMigration with PreservesAll[Transform] {
+class CombineCats extends Transform with DependencyAPIMigration {
 
   override def prerequisites = firrtl.stage.Forms.LowForm ++
     Seq( Dependency(passes.RemoveValidIf),
@@ -67,6 +66,8 @@ class CombineCats extends Transform with DependencyAPIMigration with PreservesAl
     Dependency[SystemVerilogEmitter],
     Dependency[VerilogEmitter] )
 
+  override def invalidates(a: Transform) = false
+
   val defaultMaxCatLen = 10
 
   def execute(state: CircuitState): CircuitState = {
diff --git a/src/main/scala/firrtl/transforms/DeadCodeElimination.scala b/src/main/scala/firrtl/transforms/DeadCodeElimination.scala
index 3ed4dfd9..b8cfa54e 100644
--- a/src/main/scala/firrtl/transforms/DeadCodeElimination.scala
+++ b/src/main/scala/firrtl/transforms/DeadCodeElimination.scala
@@ -10,7 +10,7 @@ import firrtl.analyses.InstanceGraph
 import firrtl.Mappers._
 import firrtl.Utils.{throwInternalError, kind}
 import firrtl.MemoizedHash._
-import firrtl.options.{Dependency, PreservesAll, RegisteredTransform, ShellOption}
+import firrtl.options.{Dependency, RegisteredTransform, ShellOption}
 
 import collection.mutable
 
@@ -32,8 +32,7 @@ import collection.mutable
 class DeadCodeElimination extends Transform
     with ResolvedAnnotationPaths
     with RegisteredTransform
-    with DependencyAPIMigration
-    with PreservesAll[Transform] {
+    with DependencyAPIMigration {
 
   override def prerequisites = firrtl.stage.Forms.LowForm ++
     Seq( Dependency(firrtl.passes.RemoveValidIf),
@@ -54,6 +53,8 @@ class DeadCodeElimination extends Transform
          Dependency(passes.VerilogPrep),
          Dependency[firrtl.AddDescriptionNodes] )
 
+  override def invalidates(a: Transform) = false
+
   val options = Seq(
     new ShellOption[Unit](
       longOption = "no-dce",
diff --git a/src/main/scala/firrtl/transforms/Dedup.scala b/src/main/scala/firrtl/transforms/Dedup.scala
index 7199d63a..04ac968d 100644
--- a/src/main/scala/firrtl/transforms/Dedup.scala
+++ b/src/main/scala/firrtl/transforms/Dedup.scala
@@ -11,7 +11,7 @@ import firrtl.passes.{InferTypes, MemPortUtils}
 import firrtl.Utils.throwInternalError
 import firrtl.annotations.transforms.DupedResult
 import firrtl.annotations.TargetToken.{OfModule, Instance}
-import firrtl.options.{HasShellOptions, PreservesAll, ShellOption}
+import firrtl.options.{HasShellOptions, ShellOption}
 import logger.LazyLogging
 
 // Datastructures
@@ -73,12 +73,14 @@ case class DedupedResult(original: ModuleTarget, duplicate: Option[IsModule], in
   * This transform will also emit [[DedupedResult]] for deduped modules that
   * only have one instance.
   */
-class DedupModules extends Transform with DependencyAPIMigration with PreservesAll[Transform] {
+class DedupModules extends Transform with DependencyAPIMigration {
 
   override def prerequisites = firrtl.stage.Forms.Resolved
 
   override def optionalPrerequisiteOf = Seq.empty
 
+  override def invalidates(a: Transform) = false
+
   /** Deduplicate a Circuit
     * @param state Input Firrtl AST
     * @return A transformed Firrtl AST
diff --git a/src/main/scala/firrtl/transforms/FixAddingNegativeLiteralsTransform.scala b/src/main/scala/firrtl/transforms/FixAddingNegativeLiteralsTransform.scala
index f6990082..a1e49d62 100644
--- a/src/main/scala/firrtl/transforms/FixAddingNegativeLiteralsTransform.scala
+++ b/src/main/scala/firrtl/transforms/FixAddingNegativeLiteralsTransform.scala
@@ -5,7 +5,7 @@ package firrtl.transforms
 import firrtl.{CircuitState, DependencyAPIMigration, Namespace, PrimOps, Transform, Utils, WRef}
 import firrtl.ir._
 import firrtl.Mappers._
-import firrtl.options.{Dependency, PreservesAll}
+import firrtl.options.Dependency
 import firrtl.PrimOps.{Add, AsSInt, Sub, Tail}
 import firrtl.stage.Forms
 
@@ -107,7 +107,7 @@ object FixAddingNegativeLiterals {
   * the literal and thus not all expressions in the add are the same. This is fixed here when we directly
   * subtract the literal instead.
   */
-class FixAddingNegativeLiterals extends Transform with DependencyAPIMigration with PreservesAll[Transform] {
+class FixAddingNegativeLiterals extends Transform with DependencyAPIMigration {
 
   override def prerequisites = Forms.LowFormMinimumOptimized :+ Dependency[BlackBoxSourceHelper]
 
@@ -115,6 +115,8 @@ class FixAddingNegativeLiterals extends Transform with DependencyAPIMigration wi
 
   override def optionalPrerequisiteOf = Seq.empty
 
+  override def invalidates(a: Transform) = false
+
   def execute(state: CircuitState): CircuitState = {
     val modulesx = state.circuit.modules.map(FixAddingNegativeLiterals.fixupModule)
     state.copy(circuit = state.circuit.copy(modules = modulesx))
diff --git a/src/main/scala/firrtl/transforms/Flatten.scala b/src/main/scala/firrtl/transforms/Flatten.scala
index 7a7c7338..cc5b3504 100644
--- a/src/main/scala/firrtl/transforms/Flatten.scala
+++ b/src/main/scala/firrtl/transforms/Flatten.scala
@@ -7,7 +7,6 @@ import firrtl.ir._
 import firrtl.Mappers._
 import firrtl.annotations._
 import scala.collection.mutable
-import firrtl.options.PreservesAll
 import firrtl.passes.{InlineInstances,PassException}
 import firrtl.stage.Forms
 
@@ -24,11 +23,12 @@ case class FlattenAnnotation(target: Named) extends SingleTargetAnnotation[Named
   * @note Flattening a module means inlining all its fully-defined child instances
   * @note Instances of extmodules are not (and cannot be) inlined
   */
-class Flatten extends Transform with DependencyAPIMigration with PreservesAll[Transform] {
+class Flatten extends Transform with DependencyAPIMigration {
 
    override def prerequisites = Forms.LowForm
    override def optionalPrerequisites = Seq.empty
    override def optionalPrerequisiteOf = Forms.LowEmitters
+  override def invalidates(a: Transform) = false
 
    val inlineTransform = new InlineInstances
 
diff --git a/src/main/scala/firrtl/transforms/InlineBitExtractions.scala b/src/main/scala/firrtl/transforms/InlineBitExtractions.scala
index 3f2fcdcd..515bf407 100644
--- a/src/main/scala/firrtl/transforms/InlineBitExtractions.scala
+++ b/src/main/scala/firrtl/transforms/InlineBitExtractions.scala
@@ -5,7 +5,7 @@ package transforms
 
 import firrtl.ir._
 import firrtl.Mappers._
-import firrtl.options.{Dependency, PreservesAll}
+import firrtl.options.Dependency
 import firrtl.PrimOps.{Bits, Head, Tail, Shr}
 import firrtl.Utils.{isBitExtract, isTemp}
 import firrtl.WrappedExpression._
@@ -94,7 +94,7 @@ object InlineBitExtractionsTransform {
 }
 
 /** Inline nodes that are simple bits */
-class InlineBitExtractionsTransform extends Transform with DependencyAPIMigration with PreservesAll[Transform] {
+class InlineBitExtractionsTransform extends Transform with DependencyAPIMigration {
 
   override def prerequisites = firrtl.stage.Forms.LowFormMinimumOptimized ++
     Seq( Dependency[BlackBoxSourceHelper],
@@ -105,6 +105,8 @@ class InlineBitExtractionsTransform extends Transform with DependencyAPIMigratio
 
   override def optionalPrerequisiteOf = Seq.empty
 
+  override def invalidates(a: Transform) = false
+
   def execute(state: CircuitState): CircuitState = {
     val modulesx = state.circuit.modules.map(InlineBitExtractionsTransform.onMod(_))
     state.copy(circuit = state.circuit.copy(modules = modulesx))
diff --git a/src/main/scala/firrtl/transforms/LegalizeClocks.scala b/src/main/scala/firrtl/transforms/LegalizeClocks.scala
index e3185deb..333eb096 100644
--- a/src/main/scala/firrtl/transforms/LegalizeClocks.scala
+++ b/src/main/scala/firrtl/transforms/LegalizeClocks.scala
@@ -3,7 +3,7 @@ package transforms
 
 import firrtl.ir._
 import firrtl.Mappers._
-import firrtl.options.{Dependency, PreservesAll}
+import firrtl.options.Dependency
 import firrtl.Utils.isCast
 
 // Fixup otherwise legal Verilog that lint tools and other tools don't like
@@ -59,7 +59,7 @@ object LegalizeClocksTransform {
 }
 
 /** Ensure Clocks to be emitted are legal Verilog */
-class LegalizeClocksTransform extends Transform with DependencyAPIMigration with PreservesAll[Transform] {
+class LegalizeClocksTransform extends Transform with DependencyAPIMigration {
 
   override def prerequisites = firrtl.stage.Forms.LowFormMinimumOptimized ++
     Seq( Dependency[BlackBoxSourceHelper],
@@ -72,6 +72,8 @@ class LegalizeClocksTransform extends Transform with DependencyAPIMigration with
 
   override def optionalPrerequisiteOf = Seq.empty
 
+  override def invalidates(a: Transform) = false
+
   def execute(state: CircuitState): CircuitState = {
     val modulesx = state.circuit.modules.map(LegalizeClocksTransform.onMod(_))
     state.copy(circuit = state.circuit.copy(modules = modulesx))
diff --git a/src/main/scala/firrtl/transforms/LegalizeReductions.scala b/src/main/scala/firrtl/transforms/LegalizeReductions.scala
index 9446c896..2e60aae7 100644
--- a/src/main/scala/firrtl/transforms/LegalizeReductions.scala
+++ b/src/main/scala/firrtl/transforms/LegalizeReductions.scala
@@ -3,7 +3,7 @@ package transforms
 
 import firrtl.ir._
 import firrtl.Mappers._
-import firrtl.options.{Dependency, PreservesAll}
+import firrtl.options.Dependency
 import firrtl.Utils.BoolType
 
 
@@ -31,7 +31,7 @@ object LegalizeAndReductionsTransform {
   * Workaround a bug in Verilator v4.026 - v4.032 (inclusive).
   * For context, see https://github.com/verilator/verilator/issues/2300
   */
-class LegalizeAndReductionsTransform extends Transform with DependencyAPIMigration with PreservesAll[Transform] {
+class LegalizeAndReductionsTransform extends Transform with DependencyAPIMigration {
 
   override def prerequisites =
     firrtl.stage.Forms.WorkingIR ++
@@ -42,6 +42,8 @@ class LegalizeAndReductionsTransform extends Transform with DependencyAPIMigrati
 
   override def optionalPrerequisiteOf = Nil
 
+  override def invalidates(a: Transform) = false
+
   def execute(state: CircuitState): CircuitState = {
     val modulesx = state.circuit.modules.map(LegalizeAndReductionsTransform.onMod(_))
     state.copy(circuit = state.circuit.copy(modules = modulesx))
diff --git a/src/main/scala/firrtl/transforms/PropagatePresetAnnotations.scala b/src/main/scala/firrtl/transforms/PropagatePresetAnnotations.scala
index e70fa47e..6bc948cd 100644
--- a/src/main/scala/firrtl/transforms/PropagatePresetAnnotations.scala
+++ b/src/main/scala/firrtl/transforms/PropagatePresetAnnotations.scala
@@ -6,7 +6,7 @@ package transforms
 import firrtl.PrimOps._
 import firrtl.annotations._
 import firrtl.ir.{AsyncResetType, _}
-import firrtl.options.{Dependency, PreservesAll}
+import firrtl.options.Dependency
 
 import scala.collection.mutable
 
@@ -36,7 +36,7 @@ object PropagatePresetAnnotations {
   *
   * @note This pass must run before InlineCastsTransform
   */
-class PropagatePresetAnnotations extends Transform with DependencyAPIMigration with PreservesAll[Transform] {
+class PropagatePresetAnnotations extends Transform with DependencyAPIMigration {
 
   override def prerequisites = firrtl.stage.Forms.LowFormMinimumOptimized ++
     Seq( Dependency[BlackBoxSourceHelper],
@@ -47,6 +47,7 @@ class PropagatePresetAnnotations extends Transform with DependencyAPIMigration w
 
   override def optionalPrerequisiteOf = Seq.empty
 
+  override def invalidates(a: Transform) = false
 
   import PropagatePresetAnnotations._
 
diff --git a/src/main/scala/firrtl/transforms/RemoveKeywordCollisions.scala b/src/main/scala/firrtl/transforms/RemoveKeywordCollisions.scala
index c7ed6688..c5f20363 100644
--- a/src/main/scala/firrtl/transforms/RemoveKeywordCollisions.scala
+++ b/src/main/scala/firrtl/transforms/RemoveKeywordCollisions.scala
@@ -10,7 +10,7 @@ import firrtl.ir
 import firrtl.passes.{Uniquify, PassException}
 import firrtl.Utils.v_keywords
 import firrtl.Mappers._
-import firrtl.options.{Dependency, PreservesAll}
+import firrtl.options.Dependency
 
 import scala.collection.mutable
 
@@ -231,7 +231,7 @@ class RemoveKeywordCollisions(keywords: Set[String]) extends Transform with Depe
 }
 
 /** Transform that removes collisions with Verilog keywords */
-class VerilogRename extends RemoveKeywordCollisions(v_keywords) with PreservesAll[Transform] {
+class VerilogRename extends RemoveKeywordCollisions(v_keywords) {
 
   override def prerequisites = firrtl.stage.Forms.LowFormMinimumOptimized ++
     Seq( Dependency[BlackBoxSourceHelper],
@@ -247,4 +247,6 @@ class VerilogRename extends RemoveKeywordCollisions(v_keywords) with PreservesAl
 
   override def optionalPrerequisiteOf = Seq.empty
 
+  override def invalidates(a: Transform) = false
+
 }
diff --git a/src/main/scala/firrtl/transforms/RemoveWires.scala b/src/main/scala/firrtl/transforms/RemoveWires.scala
index cfb4fc54..0504c19d 100644
--- a/src/main/scala/firrtl/transforms/RemoveWires.scala
+++ b/src/main/scala/firrtl/transforms/RemoveWires.scala
@@ -9,7 +9,7 @@ import firrtl.Mappers._
 import firrtl.traversals.Foreachers._
 import firrtl.WrappedExpression._
 import firrtl.graph.{MutableDiGraph, CyclicException}
-import firrtl.options.{Dependency, PreservesAll}
+import firrtl.options.Dependency
 
 import scala.collection.mutable
 import scala.util.{Try, Success, Failure}
@@ -20,7 +20,7 @@ import scala.util.{Try, Success, Failure}
   *  wires have multiple connections that may be impossible to order in a
   *  flow-foward way
   */
-class RemoveWires extends Transform with DependencyAPIMigration with PreservesAll[Transform] {
+class RemoveWires extends Transform with DependencyAPIMigration {
 
   override def prerequisites = firrtl.stage.Forms.MidForm ++
     Seq( Dependency(passes.LowerTypes),
@@ -32,6 +32,8 @@ class RemoveWires extends Transform with DependencyAPIMigration with PreservesAl
 
   override def optionalPrerequisiteOf = Seq.empty
 
+  override def invalidates(a: Transform) = false
+
   // Extract all expressions that are references to a Node, Wire, or Reg
   // Since we are operating on LowForm, they can only be WRefs
   private def extractNodeWireRegRefs(expr: Expression): Seq[WRef] = {
diff --git a/src/main/scala/firrtl/transforms/RenameModules.scala b/src/main/scala/firrtl/transforms/RenameModules.scala
index 3015ebf7..edd9fefb 100644
--- a/src/main/scala/firrtl/transforms/RenameModules.scala
+++ b/src/main/scala/firrtl/transforms/RenameModules.scala
@@ -5,7 +5,6 @@ package firrtl.transforms
 import firrtl.analyses.{InstanceGraph, ModuleNamespaceAnnotation}
 import firrtl.ir._
 import firrtl._
-import firrtl.options.PreservesAll
 import firrtl.stage.Forms
 
 import scala.collection.mutable
@@ -14,11 +13,12 @@ import scala.collection.mutable
   *
   * using namespace created by [[analyses.GetNamespace]], create unique names for modules
   */
-class RenameModules extends Transform with DependencyAPIMigration with PreservesAll[Transform] {
+class RenameModules extends Transform with DependencyAPIMigration {
 
   override def prerequisites = Forms.LowForm
   override def optionalPrerequisites = Seq.empty
   override def optionalPrerequisiteOf = Forms.LowEmitters
+  override def invalidates(a: Transform) = false
 
   def collectNameMapping(namespace: Namespace, moduleNameMap: mutable.HashMap[String, String])(mod: DefModule): Unit = {
     val newName = namespace.newName(mod.name)
diff --git a/src/main/scala/firrtl/transforms/ReplaceTruncatingArithmetic.scala b/src/main/scala/firrtl/transforms/ReplaceTruncatingArithmetic.scala
index 9699d012..a93087b9 100644
--- a/src/main/scala/firrtl/transforms/ReplaceTruncatingArithmetic.scala
+++ b/src/main/scala/firrtl/transforms/ReplaceTruncatingArithmetic.scala
@@ -7,7 +7,7 @@ import firrtl.ir._
 import firrtl.Mappers._
 import firrtl.PrimOps._
 import firrtl.WrappedExpression._
-import firrtl.options.{Dependency, PreservesAll}
+import firrtl.options.Dependency
 
 import scala.collection.mutable
 
@@ -77,7 +77,7 @@ object ReplaceTruncatingArithmetic {
   * @note This replaces some FIRRTL primops with ops that are not actually legal FIRRTL. They are
   * useful for emission to languages that support non-expanding arithmetic (like Verilog)
   */
-class ReplaceTruncatingArithmetic extends Transform with DependencyAPIMigration with PreservesAll[Transform] {
+class ReplaceTruncatingArithmetic extends Transform with DependencyAPIMigration {
 
   override def prerequisites = firrtl.stage.Forms.LowFormMinimumOptimized ++
     Seq( Dependency[BlackBoxSourceHelper],
@@ -87,6 +87,8 @@ class ReplaceTruncatingArithmetic extends Transform with DependencyAPIMigration
 
   override def optionalPrerequisiteOf = Seq.empty
 
+  override def invalidates(a: Transform) = false
+
   def execute(state: CircuitState): CircuitState = {
     val modulesx = state.circuit.modules.map(ReplaceTruncatingArithmetic.onMod(_))
     state.copy(circuit = state.circuit.copy(modules = modulesx))
diff --git a/src/main/scala/firrtl/transforms/SimplifyMems.scala b/src/main/scala/firrtl/transforms/SimplifyMems.scala
index 37302f45..a056c7da 100644
--- a/src/main/scala/firrtl/transforms/SimplifyMems.scala
+++ b/src/main/scala/firrtl/transforms/SimplifyMems.scala
@@ -9,7 +9,6 @@ import firrtl.annotations._
 import firrtl.passes._
 import firrtl.passes.memlib._
 import firrtl.stage.Forms
-import firrtl.options.PreservesAll
 import scala.collection.mutable
 
 import AnalysisUtils._
@@ -19,11 +18,12 @@ import ResolveMaskGranularity._
 /**
   * Lowers memories without splitting them, but without the complexity of ReplaceMemMacros
   */
-class SimplifyMems extends Transform with DependencyAPIMigration with PreservesAll[Transform] {
+class SimplifyMems extends Transform with DependencyAPIMigration {
 
   override def prerequisites = Forms.MidForm
   override def optionalPrerequisites = Seq.empty
   override def optionalPrerequisiteOf = Forms.MidEmitters
+  override def invalidates(a: Transform) = false
 
   def onModule(c: Circuit, renames: RenameMap)(m: DefModule): DefModule = {
     val moduleNS = Namespace(m)