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2020-03-30Don't use postfix operator in transforms.FlattenSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-03-26Eliminate warnings on `sbt doc` and `sbt unidoc` (#1470)Chick Markley
* Eliminate warnings on `sbt doc` and `sbt unidoc` - removed toFirrtl reference on MultiTargetAnnotation - lots of places where package path has to be added to comment references - Change to use `/** text starts here` convention when wrong in comment with a doc fix. - Did not exhaustively change these - Wrestled doc example in RenderDiGraph#renderNode, not sure if I won - Cleaned up InferWidths & CatchExceptions imports - Added missing license message to a couple of files. - fixed a couple of stale parameter names in scaladoc - Added @unchecked to stop erasure warning in Emitting where emission annotations are collected - Change types to [_] on match in RenameMap#recordAll to fix erasure warning * Where possible change [[firrtl.ir.X]] to [[firrtl.ir.X X]] for better display in scaladoc Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-03-17Add method to CheckCompLoops which returns its full netlist (#1458)David Biancolin
2020-03-12Add Support for FPGA Bitstream Preset-registers (#1050)John's Brew
Introduce Preset Register Specialized Emission - Introduce EmissionOption trait - Introduce PresetAnnotation & PresetRegAnnotation - Enable the collection of Annotations in the Emitter - Introduce collection mechanism for EmissionOptions in the Emitter - Add PropagatePresetAnnotation transform to annotate register for emission and clean-up the useless reset tree (no DCE involved) - Add corresponding tests spec and tester Co-authored-by: Jack Koenig <koenig@sifive.com>
2020-03-11Don't const-prop a register's self-init (#1441)Albert Magyar
* Fixes #1214 Co-authored-by: Jack Koenig <koenig@sifive.com>
2020-03-11Migrate to DependencyAPISchuyler Eldridge
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: Albert Magyar <albert.magyar@gmail.com> Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-03-09Provide an annotation mix-in that marks RTs as dontTouch (#1433)David Biancolin
* Provide an annotation mix-in that marks RTs as dontTouch * Update src/main/scala/firrtl/transforms/OptimizationAnnotations.scala Co-Authored-By: Albert Magyar <albert.magyar@gmail.com> * Update src/test/scala/firrtlTests/DCETests.scala Co-Authored-By: Albert Magyar <albert.magyar@gmail.com> * Update src/main/scala/firrtl/transforms/OptimizationAnnotations.scala * Update OptimizationAnnotations.scala Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
2020-03-04Incorporate new AddNot formal regression testAlbert Magyar
* Feedback from @jackkoening * Merge into same stage as Ops to avoid Travis delays
2020-03-04Revert "Verilog emitter transform InlineNots (#1270)"Albert Magyar
This reverts commit f77487d37bd7c61be231a8000a3197d37cf55499.
2020-02-18Remove last connect semantics from reset inference (#1396)Jack Koenig
* Revert "Infer resets last connect semantics (#1291)" * Fix handling of invalidated and undriven components of type Reset * Run CheckTypes after InferResets * Make reset inference bidirectional on connect * Support AsyncResetType in RemoveValidIf * Fix InferResets for parent constraints on child ports * Apply suggestions from code review * Add ScalaDoc to InferResets Co-authored-by: Albert Magyar <albert.magyar@gmail.com> Co-authored-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
2020-02-13Constant prop binary PrimOps with matching argumentsAlbert Magyar
* Add SimplifyBinaryOp trait * Add extra functionality to comparison folding * Add tests * Fix comments from review
2020-02-12Fixing lint error: x + -1 (#1374)Adam Izraelevitz
* Generates lint-clean Verilog for the case: x + -1 ...where x is anything and 1 is any literal. Master behavior: input x : SInt<8> output z : SInt<9> z <= add(x, SInt(-2)) generates assign z = $signed(x) + -8'sh2; After this PR: assign z = $signed(x) - 8'sh2; If the literal is the maximum possible literal, a special case is triggered to properly trim the resulting subtraction. Input: input x : SInt<2> output z : SInt<3> z <= add(x, SInt(-2)) now generates (after this PR) assign z = $signed(x) - 3'sh2; * Updated documentation * Change ArrayBuffer to ListBuffer * Change name to minNegValue * Remove mutable public interfaces Co-authored-by: Albert Magyar <albert.magyar@gmail.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-02-07Refactor handling of reg const prop entries to cover more casesAlbert Magyar
2020-02-06Better register const prop through speculative de-optimizationAlbert Magyar
* Fixes #1240 * Add failing reg const prop test case from #1240
2020-02-06Add constant prop to async regs (#1355)Adam Izraelevitz
* Add constant prop to async regs * Added another test of no reset value but constant assignment * Clarify name of updateNodeMap * Update constant assignment of async reset to not be inferred as a latch, works with donttouch * Revert "Update constant assignment of async reset to not be inferred as a latch, works with donttouch" This reverts commit 952bf38127cb32f814496a2b4b3bfb173d532728.
2020-02-03Dedup: check if moduleOpt exists before getting (#1323)Albert Chen
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-01-20clean up warnings: trim unused imports (#1315)John Ingalls
2020-01-15Verilog emitter transform InlineBitExtractions (#1296)John Ingalls
* transform InlineBitExtractions * InlineNotsTransform, InlineBitExtractionsTransform: inputForm/outputForm = UnknownForm * clean up some minor redundancies from Adam review * clarifications from Seldrige review
2020-01-07Fix literals cast to Clocks in Print and StopJack Koenig
Many tools don't except 'always @(posedge 1'h0)' so we assign the literal to a wire and use that as the posedge target.
2020-01-07Remove unnecessary $signed casts for PrimOps in Verilog EmitterJack Koenig
[skip formal checks] Adds new InlineCastsTransform to the VerilogEmitter which removes Statements that do nothing but cast by inlining the cast Expression
2020-01-07Remove unnecessary casts in Constant PropagationJack Koenig
2020-01-06Verilog emitter transform InlineNots (#1270)John Ingalls
[skip formal checks] * ConstProp FoldEqual/FoldNotEqual propagate boolean (non-)equality with true/false * transform InlineNots * transform back-to-back Nots into straight rename * swap mux with inverted select Co-authored-by: Jack Koenig <jack.koenig3@gmail.com>
2019-12-30Minor code cleansup in InferResetsJack Koenig
* Move Map lookup into closure so it only occurs if necessary * Replace gender with flow and improve code clarity
2019-12-30Respect last connect semantics in InferResetsJack Koenig
InferResets will now support last connect semantics (within the same scope) when determining the concrete reset type for components of type Reset. This only includes *unconditional* last connects; it remains illegal to drive a component of type Reset with different concrete types under differing when conditions. For example, the following is now legal: input a : UInt<1> input b : AsyncReset output z : Reset z <= a z <= b The second connect will when and z will be of type AsyncReset. The following remains illegal: input a : UInt<1> input b : AsyncReset input c : UInt<1> output z : Reset z <= a when c : z <= b This commit also ensures that components of type Reset with no drivers (or only invalidation) default to type UInt<1>. This fixes a bug where the transform would crash with such input.
2019-11-04Ignore extmodule instances in Flatten (#1218)Albert Magyar
* Closes #1162 * Instances of extmodules remain in the final hierarchy * Extmodule definitions are not renamed or duplicated * The rest of the pass may proceed as normal
2019-10-24Enhance CheckCombLoops errors with connection infoAlbert Magyar
* Closes #1203
2019-10-08Make TopWiringTransform idempotentSchuyler Eldridge
This changes TopWiringTransform to remove TopWiringAnnotations after it runs. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-10-07Absorb some instance analysis into InstanceGraph, use safer boxed Strings ↵Albert Magyar
(#1186) * Replace instance analysis code with InstanceGraph API calls * Add convenience implicits for using TargetTokens as safe boxed strings
2019-09-16Rename gender to flowSchuyler Eldridge
The following names are changed: - gender -> flow - Gender -> Flow - MALE -> SourceFlow - FEMALE -> SinkFlow - BIGENDER -> DuplexFlow - UNKNOWNGENDER -> UnknownFlow Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-09-12Add space, s/Github/GitHub/ in DontTouchException (#1177)Schuyler Eldridge
Adds a space to correct in an exception message. Corrects capitalization in Github to it's official name (GitHub) and adds a link to file an issue. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-09-05Filter out more filename extensions for blackbox source headers (#1134)Albert Magyar
2019-08-19Refactor exceptions to remove stack trace from user errors (#1157)Jack Koenig
2019-08-13Infer reset (#1068)Jack Koenig
* Add abstract "Reset" which can be inferred to AsyncReset or UInt<1> * Enhance async reset initial value literal check to support aggregates
2019-08-07Improve RemoveReset handling of invalid initsSchuyler Eldridge
This modifies RemoveReset to NOT generate a mux for invalid (IsInvalid) inits. In the case of an invalid init, the reset is converted to a self-connect and no mux is generated. This is implemented as a new, initial pass over the module to populate a set of all invalid signals. During the subsequent, circuit-modifying pass, this invalid set is queried to special case the handling of invalid inits. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-30Fix "since" deprecation, should be "1.2" not "1.3" (#1139)Schuyler Eldridge
- Fixes BlackBoxSourceHelper deprecation "since"
2019-07-25Allow name of blackbox resource .f file to change from static value (#1129)Albert Magyar
* Allow name of blackbox resource .f file to change from static value * Restore fileListName as a deprecated def per Jack's feedback * Support both local and absolute paths for .f resource files
2019-07-24Add ExpandConnects to TopWiringTransform fixup (#1135)Schuyler Eldridge
This fixes a bug in the TopWiringTransform when wiring aggregates by adding ExpandConnects to its list of fixup passes. TopWiringTransform is MidForm => MidForm, but when wiring aggregates, it will output bulk connects. This violates the MidForm prerequisite that ExpandConnects has run. Symptomatically, this will manifest as match errors in LowerTypes if a user tries to use the TopWiringTransform on aggregates. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-23more constprop on muxes (#1052)Donggyu Kim
2019-07-19Add SimplifyMems transform to lower memories without splitting (#1111)Albert Magyar
* Add SimplifyMems transform to lower memories without splitting * Remove spurious anonymous function
2019-07-08Remove some warnings (#1118)Leway Colin
2019-06-28Remove deprecated ComponentName from CombinationalPath annotation (#1107)Albert Magyar
2019-06-18Use scalafix to remove unused import and deprecated procedure syntax (#1074)Leway Colin
* Add sbt-scalafix * Add scalafix guide to README * Remove Unused Import * Remove deprecated procedure syntax
2019-05-09Bugfix: GroupComponents (#1082)Adam Izraelevitz
* Added test to GroupComponentsSpec demonstrating bug * Added bugfix to GroupComponents for invalid ports of grouped instances
2019-05-04Add register init to RemoveWires dependencies (#1078)Schuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-04-29Update NoCircuitDedupAnnotation so it's available from firrtl.stage.FirrtlMainJim Lawson
2019-04-25Add ShellOption, DeletedWrapperSchuyler Eldridge
Abstracts away option writing such that users no longer have to understand scopt semantics. This adds a ShellOption class and a HasShellOptions trait for something which provides one or more ShellOptions. This refactors the FIRRTL codebase to use this style of option specification. Adds and uses DeletedWrapper to automatically generate DeletedAnnotations. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-03-29Faster reg constprop (#1067)Albert Magyar
* Improve memoization for register const prop
2019-03-26DCE printf and stop statements with constant-0 enablesAndrew Waterman
This gets rid of about 10% of the generated Verilog in the rocket-chip default config.
2019-02-27Add --nodedup option to facilitate FIRRTL to verilog regression testing. (#1035)Jim Lawson
* Add --nodedup option to facilitate FIRRTL to verilog regression testing. * Short-circuit the DedupModules transform if NoCircuitDedupAnnotation exists.
2019-02-25Fix almost all Scaladoc warningsSchuyler Eldridge
This fixes all Scaladoc warnings except for those trying to link to Java. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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