| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2021-12-21 | Remove some warnings (#2448) | Jack Koenig | |
| * Fix unreachable code warning by changing match order Simulation Statements did not previously extend IsDeclaration, but now they do so their match blocks need to be above IsDeclaration. * Handle MemoryNoInit case in RtlilEmitter * Remove use of deprecated logToFile * Fix uses of LegalizeClocksTransform Replaced all uses of LegalizeClocksTransform with LegalizeClocksAndAsyncResetsTransform. * Remove use of CircuitForm in ZeroWidth | |||
| 2021-11-22 | remove firrtl.transforms.InlineAcrossCastsTransform. (#2424) | Jiuyang Liu | |
| Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | |||
 |
index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
| aboutsummaryrefslogtreecommitdiff |