sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Collapse)	Author
2016-10-23	Fix bitmask (#346)	Angie Wang
	* toBitMask cat direction should be consistent with data * minor comment updates * moved remaining mem passes/utils to memlib * changed again so that data, mask are consistent. data element 0, bit 0 = LSB (on RHS) when concatenated
2016-10-11	Scala style cleanup take 5 (#324)	Chick Markley
	* working through variable shrouding * working through variable shrouding * working through variable shadowing * working through variable shadowing hmm there are some very fragile match {} in Passes * working through variable shadowing hmm there are some very fragile match {} in Passes * working through variable shadowing * working through variable shadowing * working through variable shadowing * working through variable shadowing * working through variable shadowing * working through variable shadowing * working through variable shadowing * working through variable shadowing * Fixes suggested by Adam
2016-09-27	remove unnecessary parentheses	chick

2016-09-27	enclosing block redundant	chick

2016-09-27	No return type for implicit function	chick

2016-09-25	offload latency pipe generation for memories from VerilogEmitter	Donggyu Kim
	discussed with @azidar