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Fix bugs related to arithmetic ops inlined into a mux leg. Add formal
equivalence checks to lock in this behavior.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
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* rearrange passes to enable optimized firrtl emission
* Support ConstProp on padded arguments to comparisons with literals
* Move shr legalization logic into ConstProp
Continue calling ConstProp of shr in Legalize.
Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
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This adds missing invalidations to four transforms:
- ExpandConnects
- RemoveAccesses
- SplitExpressions
- VerilogMemDelays
This necessarily updates test cases which expect exact transform
orders to reflect the new order.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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This mixes in the new DependencyAPIMigration trait into all Transforms
and Passes. This enables in-tree transforms/passes to build without
deprecation warnings associated with the deprecated CircuitForm.
As a consequence of this, every Transform now has UnknownForm as both
its inputForm and outputForm. This PR modifies legacy Compiler and
testing infrastructure to schedule transforms NOT using
mergeTransforms/getLoweringTransforms (which rely on inputForm and
outputForm not being UnknownForm), but instead using the Dependency
API.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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The following names are changed:
- gender -> flow
- Gender -> Flow
- MALE -> SourceFlow
- FEMALE -> SinkFlow
- BIGENDER -> DuplexFlow
- UNKNOWNGENDER -> UnknownFlow
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Replace with more sensible comment to see LICENSE rather than including the
whole license in every file
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* working through variable shrouding
* working through variable shrouding
* working through variable shadowing
* working through variable shadowing
hmm there are some very fragile match {} in Passes
* working through variable shadowing
hmm there are some very fragile match {} in Passes
* working through variable shadowing
* working through variable shadowing
* working through variable shadowing
* working through variable shadowing
* working through variable shadowing
* working through variable shadowing
* working through variable shadowing
* working through variable shadowing
* Fixes suggested by Adam
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example 1 s"${x}"
example 2 case blah => { ??? }
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Changed code from match statements in Mappers.scala to methods on the various
IR classes. This allows custom IR nodes to implement the mapper functions and
thus work (ie. not match error) when map is called on them.
This also should have a marginal performance increase because of use of virtual
function calls rather than match statements.
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remove unnecessary functions & change spaces
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Indentation support for the ANTLR parser
- some clean-up of the parser code (TODO: file input could be improved, more clean-up)
- get rid of Translator and specify all syntactic rules in antlr4 grammer
- support for else-when shorthand in the grammar
- rename Begin to Block which makes more sense
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trait AST -> abstract class FirrtlNode
Move all IR to new package ir
Add import of firrtl.ir._
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trait Stmt -> abstract class Statement (to match Expression)
abbrev. exp -> expr
BulkConnect -> PartialConnect
camelCase things that were snake_case
case class Empty() -> case object EmptyStmt
Change >120 character Statements to multiline
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trait Module -> abstract class DefModule
InModule -> Module (match concrete syntax)
ExModule -> ExtModule (match concrete syntax)
Add simple scaladoc for each one
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