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* Utils: add to_dir helper function
* firrt.SymbolTable trait for scanning declarations
* ir: RefLikeExpression trait to represent SubField, SubIndex, SubAccess and Reference nodes
* add new implementation of the LowerTypes pass
* replace LowerTypes with NewLowerTypes
* remove dependencies on Uniquify
* GroupComponentSpec: GroupComponents is run before lower types
* NewLowerTypes: address Adam's suggestions
* LoweringCompilerSpec: Uniquify was removed and NewLowerTypes
* LowerTypesSpec: add newline at the end of file
* LowerTypesSpec: port Uniquify tests to combined pass
* NewLowerTypes: ensure that internal methods are not visible
* NewLowerTypes: extend DependencyAPIMigration
* NewLowerTypes: lower ports without looking at the body
* LowerTypesSpec: use TransformManager instead of hard coded passes.
* NewLowerTypes: names are already assumed to be part of the namespace
* LowerTypesSpec: test name clashes between ports and nodes, inst, mem
* NewLowerTypes: correctly rename nodes, mems and instances that clash with port names
* NewLowerTypes: Iterable[String] instead of Seq[String] for 2.13
* NewLowerTypes: add a fast path for ground types without renaming
* LowerTypesSpec: remove trailing commans for 2.11
* LowerTypesSpec: explain why there are two
* Uniquify: use loweredName from NewLowerType
* replace old LowerTypes pass with NewLowerTypes pass
* Uniquify: deprecate pass usage
There are some functions that are still used by other passes.
* LowerTypes: InstanceKeyGraph now has a private constructor
* LowerTypes: remove remaining references to NewLowerTypes
* LoweringCompilerSpec: fix transform order to LowerTypes
* SymbolTable: add improvements from PR
* LoweringCompilerSpec: ignore failing CustomTransform tests
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* [WIP] Propagate source locators to Verilog if-else emission
* Add and fix tests for reg update info propagation
* Add limited source locator propagation in ConstProp
Support propagating source locators on connections or nodes where the
right-hand side is simply a reference. This case comes up a lot for
registers without a synchronous reset.
node _T_1 = x @[MyFile.scala 12:10]
node _T_2 = _T_1
z <= x
Previousy the source locator would be lost, now the result is:
z <= x @[MyFile.scala 12:10]
* Address review comments
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* RemoveAccess: update gender to flow
* ExpandWhens: update female to sink
* RemoveCHIRRTL: female -> sink, male -> source
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* Add assume, assert, cover statements
* Assert submodule assumptions
* Add warning when removing verification statements
* Remove System Verilog behaviour emitter warning
* Add option to disable AssertSubmoduleAssumptions
* Document verification statements in the spec
The syntax for the new statements is
assert(clk, cond, en, msg)
assume(clk, cond, en, msg)
cover(clk, cond, en, msg)
With assert as a representative example, the semantics is as follows:
`clk` is the clock, `cond` is the expression being asserted, `en` is the
enable signal (if `en` is low then the assert is not checked) and `msg`
is a string message intended to be reported as an error message by the
model checker if the assertion fails.
In the Verilog emitter, the new statements are handled by a new
`formals` map, which groups the statements by clock domain. All model
checking statements are then emitted within the context of an `ifdef
FORMAL` block, which allows model checking tools (like Symbiyosys) to
utilize the statements while keeping them out of synthesis flows.
Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
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Use WrappedExpression instead of MemoizedHash. The benefit of memoizing
the hash pales in comparison to the cost of hashing deeply nested Types
in the AST.
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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This mixes in the new DependencyAPIMigration trait into all Transforms
and Passes. This enables in-tree transforms/passes to build without
deprecation warnings associated with the deprecated CircuitForm.
As a consequence of this, every Transform now has UnknownForm as both
its inputForm and outputForm. This PR modifies legacy Compiler and
testing infrastructure to schedule transforms NOT using
mergeTransforms/getLoweringTransforms (which rely on inputForm and
outputForm not being UnknownForm), but instead using the Dependency
API.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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The following names are changed:
- gender -> flow
- Gender -> Flow
- MALE -> SourceFlow
- FEMALE -> SinkFlow
- BIGENDER -> DuplexFlow
- UNKNOWNGENDER -> UnknownFlow
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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* Add sbt-scalafix
* Add scalafix guide to README
* Remove Unused Import
* Remove deprecated procedure syntax
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* Don't create nodes to hold Muxes with >0 void cases
* Added test case demonstrating void error
* Memoize intermediate expression when checking for WVoid-ness
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This fixes all Scaladoc warnings except for those trying to link to
Java.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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It is O(n) and every use is in an O(n) iteration resulting in O(n^2).
Same information can be extracted from create_exps which happens to also
be called at every use of get_flip.
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This enables the pattern of attaching "through" a wire to give better
Verilog that also works in Verilator
Use WrappedExpression when combining attaches in ExpandWhens
to ensure no duplication of references in resulting, combined attaches
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* Collects Infos found for symbols
* Merges multiple sources for symbol into MultiInfo
* Restores these Infos on connect statements.
* Add test showing preserved Infos
* Changed ++ methods on the Info sub-classes
* Ignore NoInfo being added
* Fixed way adding was implemented in MultiInfo
* Made InfoMap a class which defines the default value function
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* Catch exceptions and convert to internal error.
We need to update the displayed message to incorporate a line number and text to be used for the issue.
* Cleanup exception handling/throwing.
Re-throw expected (or uncorrectable exceptions).
Provide Utils.getThrowable() to get the first (eldest) or last throwable in the chain.
Update tests to conform to FreeSpec protocol.
* Minor cleanup
Admit we've updated some deprecated ScalaTest methods.
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Also add tests for what should happen to 'is invalid' in ExpandWhens
Fixes #606
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* Rework Attach to work on arbitrary Analog hierarchies
If there are zero or one Analog sources in an Attach (source meaning
wire or parent module port), then the Attach will be emitted as a simple
point to point connection. In the general case, alias is used for
simulation while forwards and backwards assigns for synthesis. Verilator
does not currently support the general case so an `ifdef Verilator
`error is emitted.
* Add helper functions for creating WRef from Reg and Wire
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Replace with more sensible comment to see LICENSE rather than including the
whole license in every file
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* working through variable shrouding
* working through variable shrouding
* working through variable shadowing
* working through variable shadowing
hmm there are some very fragile match {} in Passes
* working through variable shadowing
hmm there are some very fragile match {} in Passes
* working through variable shadowing
* working through variable shadowing
* working through variable shadowing
* working through variable shadowing
* working through variable shadowing
* working through variable shadowing
* working through variable shadowing
* working through variable shadowing
* Fixes suggested by Adam
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* Spec features added: AnalogType and Attach
AnalogType(width: Width):
- Concrete syntax:
wire x: AnalogType<10>
- New groundtype, very restricted in use cases.
- Can only declare ports and wires with Analog type
- Analog types are never equivalent, thus if x and y have Analog
types: x <= y is never legal.
Attach(info: Info, source: Expression, exprs: Seq[Expression]):
- Concrete syntax:
attach x to (y, z)
- New statement
- Source can be any groundtyped expression (UInt, SInt, Analog, Clock)
- Exprs must have an Analog type reference an instance port
- Source and exprs must have identical widths
Included WDefInstanceConnector to enable emission of Verilog inout
Should be mostly feature complete.
Need to update spec if PR gets accepted.
* Fixed bug where invalidated ports aren't handled
* Bugfix for VerilogPrep
Intermediate wires for invalidated instance ports were not invalidated
* Bugfix: calling create_exp with name/tpe
Returns unknown gender, which was passing through
Caused temporary wire to not be declared
Because Verilog is dumb, undeclared wires are assumed to be 1bit signals
* Addressed donggyukim's style comments
* Reworked pass to only allow analog types in attach
Restrict source to be only wire or port kind
Much simpler implementation, almost identical functionality
Clearer semantics (i think?)
* Fixup bugs from pulling in new changes from master
* comments for type eqs and small style fixes
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Despite the fact that LinkedHashMaps preserve insertion order in traversal, it
appears that .keys and .keySet return Sets that do not provide the same
guarantee
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hidden const props not desirable
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* Added RemoveEmpty.scala, which removes Empty and nested Blocks
* Reused squashEmpty from ExpandWhens by moving it to Utils
* Squash EmptyStmts in ExpandWhens correctly
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Indentation support for the ANTLR parser
- some clean-up of the parser code (TODO: file input could be improved, more clean-up)
- get rid of Translator and specify all syntactic rules in antlr4 grammer
- support for else-when shorthand in the grammar
- rename Begin to Block which makes more sense
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trait AST -> abstract class FirrtlNode
Move all IR to new package ir
Add import of firrtl.ir._
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trait Stmt -> abstract class Statement (to match Expression)
abbrev. exp -> expr
BulkConnect -> PartialConnect
camelCase things that were snake_case
case class Empty() -> case object EmptyStmt
Change >120 character Statements to multiline
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Add simple documentation
Flip -> Orientation
trait Orientation -> abstract class Orientation
Orientation case objects to upper camel case
REVERSE -> Flip
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trait Module -> abstract class DefModule
InModule -> Module (match concrete syntax)
ExModule -> ExtModule (match concrete syntax)
Add simple scaladoc for each one
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Fixes #113 and Fixes #150
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