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path: root/src/main/scala/firrtl/passes/Checks.scala
AgeCommit message (Collapse)Author
2020-04-13Split Checks into separate filesAlbert Magyar
2020-04-06Remove deprecated ResolveGenders and CheckGendersAlbert Magyar
* Remove few remaining uses of these passes from FIRRTL codebase
2020-03-16Check for collision of defnames with Module namesAlbert Magyar
* Fixes #1096
2020-03-16Check for module name conflictsAlbert Magyar
* Fixes #1436
2020-03-11Migrate to DependencyAPISchuyler Eldridge
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: Albert Magyar <albert.magyar@gmail.com> Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-03-06Check sign of primop constants where appropriate (#1421)Albert Magyar
* Avoid IndexOutOfBoundsException when Bits has too few consts * Check for negative consts in all relevant primops * Use BigInt for all checks on primop constants
2020-03-03Fix error message for NegWidthException (#1418)Albert Magyar
2020-01-20clean up warnings: trim unused imports (#1315)John Ingalls
2019-10-18Upstream intervals (#870)Adam Izraelevitz
Major features: - Added Interval type, as well as PrimOps asInterval, clip, wrap, and sqz. - Changed PrimOp names: bpset -> setp, bpshl -> incp, bpshr -> decp - Refactored width/bound inferencer into a separate constraint solver - Added transforms to infer, trim, and remove interval bounds - Tests for said features Plan to be released with 1.3
2019-09-16Deprecate Gender and add implicit Flow conversionSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-09-16Rename gender to flowSchuyler Eldridge
The following names are changed: - gender -> flow - Gender -> Flow - MALE -> SourceFlow - FEMALE -> SinkFlow - BIGENDER -> DuplexFlow - UNKNOWNGENDER -> UnknownFlow Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-08-13Infer reset (#1068)Jack Koenig
* Add abstract "Reset" which can be inferred to AsyncReset or UInt<1> * Enhance async reset initial value literal check to support aggregates
2019-08-09Remove unused CheckHighFormLike.IllegalChirrtlMemException (#1151)Albert Magyar
2019-08-07Check mems for legal latencies; ban zero write latency. (#1147)Albert Magyar
* Check mems for legal latencies; ban zero write latency. * Trigger
2019-08-07DRY check chirrtl (#1148)Albert Magyar
* Avoid redundancy between CheckChirrtl and CheckHighForm, add more checks * Add test case for illegal Chirrtl memory in HighForm
2019-07-08Remove some warnings (#1118)Leway Colin
2019-06-18Use scalafix to remove unused import and deprecated procedure syntax (#1074)Leway Colin
* Add sbt-scalafix * Add scalafix guide to README * Remove Unused Import * Remove deprecated procedure syntax
2019-02-25Run CheckHighForm after all non-emitter transforms in firrtl tests (#548)Jack Koenig
* Run CheckHighForm after all non-emitter transforms in firrtl tests * Remove shlw from checks.scala * Removed mistake in fix * Fix FirrtlSpec fix
2019-02-25Detect and error on registers with flip in type (#1031)Albert Magyar
2019-02-14Asynchronous Reset (#1011)Jack Koenig
Fixes #219 * Adds AsyncResetType (similar to ClockType) * Registers with reset signal of type AsyncResetType are async reset registers * Registers with async reset can only be reset to literal values * Add initialization logic for async reset registers
2018-11-29Replace Mappers with Foreachers in several passes (#954)Albert Magyar
2018-11-27Add foreach as alternative to map (#952)Adam Izraelevitz
* Added Foreachers * Changed CheckTypes to use foreach * Check widths now uses foreach * Finished merge, added foreachers to added stmts * Address reviewer feedback
2018-09-26Enforce port uniqueness in Chirrtl/High ChecksSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-03-27Change throwInternalError to use a String instead of Option[String] (#777)Jack Koenig
2018-03-01[name change] Use LsbLargerThanMsbException (#740)Schuyler Eldridge
Use the standard convention of 'XxYyException' for the previously named LsbLargerThanMsb Exception. h/t @kevintownsend Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-02-22Add tests for #702. Adds Utility functions. Allows clock muxing in FIRRTL, ↵Adam Izraelevitz
but not Emitter. (#717)
2018-02-21Change primop arg type (#587)Adam Izraelevitz
* Changed primops to not accept mixed-type args * Changed return type of sub of two uints to uint * Added negative tests * Removed rocket.fir. Manually changed RocketCore to not mix mul arg types. Added integration tests * Clarified test description and remove println * Fixed use of throwInternalError
2018-02-08CheckHighForm should check that Bits MSB >= LSB (#738)Schuyler Eldridge
Fixes #700 Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2017-12-20Verify shl/shr amount is > 0 (#710)Jim Lawson
Fixes #527
2017-09-22Fix string lit (#663)Jack Koenig
Refactor StringLit to use String instead of Array[Byte]
2017-05-11Refactor WIR WSub{Field,Index,Access} - rename exp -> expr #521 (#586)Jim Lawson
2017-05-03Add checks on register clock and reset types (#33) (#553)Albert Magyar
Remove infix notation on calls with side effects.
2017-03-23Pass now subclasses Transform (#477)Adam Izraelevitz
2017-02-14Add support for Analog types in partial connect (#435)Jack Koenig
Also add support for width inference
2017-02-07Rework Attach to work on arbitrary Analog hierarchies (#415)Jack Koenig
* Rework Attach to work on arbitrary Analog hierarchies If there are zero or one Analog sources in an Attach (source meaning wire or parent module port), then the Attach will be emitted as a simple point to point connection. In the general case, alias is used for simulation while forwards and backwards assigns for synthesis. Verilator does not currently support the general case so an `ifdef Verilator `error is emitted. * Add helper functions for creating WRef from Reg and Wire
2016-12-13Move CheckWidths to its own filejackkoenig
2016-12-07Bugfix: add Neg to high form check (#384)Adam Izraelevitz
2016-12-05Add check for muxing between clocks (#360)Jack Koenig
Also run CheckTypes after ExpandWhens Fixes #330
2016-11-09Added optimizations to for better width inferenceazidar
Also added exceptions for uninferred widths when checking DoPrim width legality to not trigger compiler error
2016-11-04Cleanup license at top of every file (#364)Jack Koenig
Replace with more sensible comment to see LICENSE rather than including the whole license in every file
2016-11-01Fix Match Error in Check Types on Partial Connect (#359)Jack Koenig
Fixes #329
2016-10-17Add fixed point type (#322)Adam Izraelevitz
* WIP: Adding FixedType to Firrtl proper Got simple example running through width inference Checks should be ok Need to look into FixedLiteral more * Added simple test for fixed types * Added asFixedPoint to primops * Added tail case for FixedType * Added ConvertFixedToSInt.scala Added pass to MiddleToLowerFirrtl transform * Replace AsFixedType with AsSInt in fixed removal * Bugfix: constant from asFixed not deleted * Added unit test for bulk connect * Fixed partial connect bug #241 * Fixed missing case for FixedPoint in legalizeConnect * Add FixedMathSpec that demonstrates some problems with FixedPointMath * Fixed test and ConvertToSInt to pass. Negative binary points not easily supported, needs much more time to implement. * Refactored checking neg widths Make checking for negative binary points easier * Added tests for inferring many FixedType ops shl, shr, cat, bits, head, tail, setbp, shiftbp * Handle bpshl, bpshr, bpset in ConvertFixedToSInt Changed name from shiftbp -> bpshl, bpshr Change name from setbp -> bpset Added more tests * Added set binary point test that fails * Added simple test for zero binary point * gitignore fixes for antlr intermediate dir and intellij dir * removed unused imports retool the fixed point with zero binary point test * simplified example of inability to set binary point to zero * Temporary fix for zero-width binary point This fix allows for all widths to be zero, but since this is a feature I am working on next, I'm not going to bother with a more stringent check. * change version for dsp tools * Removed extra temporary file * Fixed merge bug * Fixed another merge bug * Removed commented out/unrelated files * Removed snake case
2016-10-11Scala style cleanup take 5 (#324)Chick Markley
* working through variable shrouding * working through variable shrouding * working through variable shadowing * working through variable shadowing hmm there are some very fragile match {} in Passes * working through variable shadowing hmm there are some very fragile match {} in Passes * working through variable shadowing * working through variable shadowing * working through variable shadowing * working through variable shadowing * working through variable shadowing * working through variable shadowing * working through variable shadowing * working through variable shadowing * Fixes suggested by Adam
2016-09-27remove unnecessary parentheseschick
2016-09-26Added max width check to dshl shift amount (#318)Adam Izraelevitz
Address #297
2016-09-25Spec features added: AnalogType and Attach (#295)Adam Izraelevitz
* Spec features added: AnalogType and Attach AnalogType(width: Width): - Concrete syntax: wire x: AnalogType<10> - New groundtype, very restricted in use cases. - Can only declare ports and wires with Analog type - Analog types are never equivalent, thus if x and y have Analog types: x <= y is never legal. Attach(info: Info, source: Expression, exprs: Seq[Expression]): - Concrete syntax: attach x to (y, z) - New statement - Source can be any groundtyped expression (UInt, SInt, Analog, Clock) - Exprs must have an Analog type reference an instance port - Source and exprs must have identical widths Included WDefInstanceConnector to enable emission of Verilog inout Should be mostly feature complete. Need to update spec if PR gets accepted. * Fixed bug where invalidated ports aren't handled * Bugfix for VerilogPrep Intermediate wires for invalidated instance ports were not invalidated * Bugfix: calling create_exp with name/tpe Returns unknown gender, which was passing through Caused temporary wire to not be declared Because Verilog is dumb, undeclared wires are assumed to be 1bit signals * Addressed donggyukim's style comments * Reworked pass to only allow analog types in attach Restrict source to be only wire or port kind Much simpler implementation, almost identical functionality Clearer semantics (i think?) * Fixup bugs from pulling in new changes from master * comments for type eqs and small style fixes
2016-09-25remove unnecessary blockschick
example 1 s"${x}" example 2 case blah => { ??? }
2016-09-25Use empty-parens as appropriate for f: => Unit callschick
2016-09-23use .count instead of filter and sizechick
2016-09-13use case object for Kind (#267)Donggyu
use case object for Kind
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