aboutsummaryrefslogtreecommitdiff
path: root/src/main/scala/firrtl/passes/CheckWidths.scala
AgeCommit message (Collapse)Author
2022-12-150-bit literals (#2544)Kevin Laeufer
* allow for zero-width integer literals * CheckWidths: ensure that width is non-negative
2021-04-22Fix CheckWidths error message for uninferred width (#2196)Fabian Schuiki
Looks like a typo/auto-merge hiccup.
2021-02-01Deprecate ToWorkingIR (#2028)Schuyler Eldridge
* Deprecate firrtl.passes.ToWorkingIR Deprecate ToWorkingIR as it is now an identity transform. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> * Deprecate firrtl.stage.Forms.WorkingIR Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> * Switch from Forms.WorkingIR to Forms.MinimalHighForm Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> Co-authored-by: Jack Koenig <koenig@sifive.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-09-16Change to Apache 2.0 License (#1901)Chick Markley
2020-08-14All of src/ formatted with scalafmtchick
2020-07-28Fix incorrect error message (#1795)Andrew Waterman
dshl amount must be < 20 bits, not <= 20 bits. Resolves #1794
2020-06-22Convert PreservesAll to explicit invalidates=falseSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-06-03Use recursive-then-iterative approach for check_width_eAlbert Magyar
* Avoid excessively deep recursion * Avoid overhead of DFS for shallow expression trees * Reduce work: skip expressions that cannot contain error-containing subtrees * Review feedback: added commentary to explain new check_widths_e structure
2020-04-22s/dependents/optionalPrerequisiteOf/Schuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-04-22Mixin DependencyAPIMigration to all TransformsSchuyler Eldridge
This mixes in the new DependencyAPIMigration trait into all Transforms and Passes. This enables in-tree transforms/passes to build without deprecation warnings associated with the deprecated CircuitForm. As a consequence of this, every Transform now has UnknownForm as both its inputForm and outputForm. This PR modifies legacy Compiler and testing infrastructure to schedule transforms NOT using mergeTransforms/getLoweringTransforms (which rely on inputForm and outputForm not being UnknownForm), but instead using the Dependency API. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-04-20Avoid using infix for mutable append in CheckWidthsAlbert Magyar
2020-04-20Ensure arguments to asClock / asAsyncReset are single-bitAlbert Magyar
2020-03-11Migrate to DependencyAPISchuyler Eldridge
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: Albert Magyar <albert.magyar@gmail.com> Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-01-15improve the tail ir usability. (#1241)Sequencer
Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2019-10-18Upstream intervals (#870)Adam Izraelevitz
Major features: - Added Interval type, as well as PrimOps asInterval, clip, wrap, and sqz. - Changed PrimOp names: bpset -> setp, bpshl -> incp, bpshr -> decp - Refactored width/bound inferencer into a separate constraint solver - Added transforms to infer, trim, and remove interval bounds - Tests for said features Plan to be released with 1.3
2019-08-13Infer reset (#1068)Jack Koenig
* Add abstract "Reset" which can be inferred to AsyncReset or UInt<1> * Enhance async reset initial value literal check to support aggregates
2019-06-18Use scalafix to remove unused import and deprecated procedure syntax (#1074)Leway Colin
* Add sbt-scalafix * Add scalafix guide to README * Remove Unused Import * Remove deprecated procedure syntax
2019-02-14Asynchronous Reset (#1011)Jack Koenig
Fixes #219 * Adds AsyncResetType (similar to ClockType) * Registers with reset signal of type AsyncResetType are async reset registers * Registers with async reset can only be reset to literal values * Add initialization logic for async reset registers
2018-11-27Add foreach as alternative to map (#952)Adam Izraelevitz
* Added Foreachers * Changed CheckTypes to use foreach * Check widths now uses foreach * Finished merge, added foreachers to added stmts * Address reviewer feedback
2018-11-05Better error message for UninferredWidth exceptionSchuyler Eldridge
This changes the CheckTypes.UniferredWidth exception to include the pretty printed Target that was uninferred and suggests to the user that they may have forgotten to assign to it. This changes the CheckTypes pass to communicate the necessary Target information during AST traversal such that when an uninferred width is found, the Target is known and available. This also adds one test checking the message of the UniferredWidth exception. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-03-27Change throwInternalError to use a String instead of Option[String] (#777)Jack Koenig
2018-02-21Change primop arg type (#587)Adam Izraelevitz
* Changed primops to not accept mixed-type args * Changed return type of sub of two uints to uint * Added negative tests * Removed rocket.fir. Manually changed RocketCore to not mix mul arg types. Added integration tests * Clarified test description and remove println * Fixed use of throwInternalError
2018-02-16Replacematcherror - catch exceptions and convert to internal error. (#424)Jim Lawson
* Catch exceptions and convert to internal error. We need to update the displayed message to incorporate a line number and text to be used for the issue. * Cleanup exception handling/throwing. Re-throw expected (or uncorrectable exceptions). Provide Utils.getThrowable() to get the first (eldest) or last throwable in the chain. Update tests to conform to FreeSpec protocol. * Minor cleanup Admit we've updated some deprecated ScalaTest methods.
2017-05-03Add checks on register clock and reset types (#33) (#553)Albert Magyar
Remove infix notation on calls with side effects.
2017-03-23Pass now subclasses Transform (#477)Adam Izraelevitz
2017-03-09Sint tests and change in serialization (#456)Adam Izraelevitz
SInt representation is no longer 2's complement, but instead a positive number (hex or base 10) that is optionally preceded by a sign (-+).
2017-02-07Rework Attach to work on arbitrary Analog hierarchies (#415)Jack Koenig
* Rework Attach to work on arbitrary Analog hierarchies If there are zero or one Analog sources in an Attach (source meaning wire or parent module port), then the Attach will be emitted as a simple point to point connection. In the general case, alias is used for simulation while forwards and backwards assigns for synthesis. Verilator does not currently support the general case so an `ifdef Verilator `error is emitted. * Add helper functions for creating WRef from Reg and Wire
2016-12-13Add MaxWidth of 1,000,000 bitsjackkoenig
Also base max dshl check on MaxWidth instead of just 31 bits Resolves #320
2016-12-13Move CheckWidths to its own filejackkoenig
generated by cgit v1.2.3 (git 2.25.1) at 2026-02-26 18:38:54 +0000