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Fix an OG bug where Andr, Orr, and Xorr would accept an arbitrary number
of operands. Verilog emission doesn't support this and will silently
drop all operands after the first. E.g., "andr(a, b)" would emit as
"&a". After this commit, "andr(a, b)" will be rejected by checking
passes.
For archaeological purposes, this appears to have been the behavior
dating back to when this was added in d2d3260a.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
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* firrtl: add optional statement labels for stop, printf, assert, assume and cover
* test: parsing of statement labels
* ir: ensure that name is properly retained
* SymbolTable: add support for labled statements
* test: parsing statement labels
* test: lower types name collisions with named statements
* ignore empty names
* Inline: deal with named and unnamed statements
* RemoveWires: treat stop, printf and verification statements as "others"
* test: fix InlineInstance tests
* DeadCodeEliminations: statements are now als declarations
* CheckHighForm: ensure that statement names are not used as references
* CheckSpec: throw error if statement name collides
* add pass to automatically add missing statement names
* check: make sure that two statements cannot have the same name
* stmtLabel -> stmtName
* scalafmt
* add statement names to spec
* spec: meta data -> metadata
* EnsureStatementNames: explain naming algorithm
* remove returns
* better namespace use
* ir: add CanBeReferenced trait
* ir: add newline as jack requested
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* Deprecate firrtl.passes.ToWorkingIR
Deprecate ToWorkingIR as it is now an identity transform.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
* Deprecate firrtl.stage.Forms.WorkingIR
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
* Switch from Forms.WorkingIR to Forms.MinimalHighForm
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* Utils: add to_dir helper function
* firrt.SymbolTable trait for scanning declarations
* ir: RefLikeExpression trait to represent SubField, SubIndex, SubAccess and Reference nodes
* add new implementation of the LowerTypes pass
* replace LowerTypes with NewLowerTypes
* remove dependencies on Uniquify
* GroupComponentSpec: GroupComponents is run before lower types
* NewLowerTypes: address Adam's suggestions
* LoweringCompilerSpec: Uniquify was removed and NewLowerTypes
* LowerTypesSpec: add newline at the end of file
* LowerTypesSpec: port Uniquify tests to combined pass
* NewLowerTypes: ensure that internal methods are not visible
* NewLowerTypes: extend DependencyAPIMigration
* NewLowerTypes: lower ports without looking at the body
* LowerTypesSpec: use TransformManager instead of hard coded passes.
* NewLowerTypes: names are already assumed to be part of the namespace
* LowerTypesSpec: test name clashes between ports and nodes, inst, mem
* NewLowerTypes: correctly rename nodes, mems and instances that clash with port names
* NewLowerTypes: Iterable[String] instead of Seq[String] for 2.13
* NewLowerTypes: add a fast path for ground types without renaming
* LowerTypesSpec: remove trailing commans for 2.11
* LowerTypesSpec: explain why there are two
* Uniquify: use loweredName from NewLowerType
* replace old LowerTypes pass with NewLowerTypes pass
* Uniquify: deprecate pass usage
There are some functions that are still used by other passes.
* LowerTypes: InstanceKeyGraph now has a private constructor
* LowerTypes: remove remaining references to NewLowerTypes
* LoweringCompilerSpec: fix transform order to LowerTypes
* SymbolTable: add improvements from PR
* LoweringCompilerSpec: ignore failing CustomTransform tests
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* Use signed output in LargeParamExecutionTest
Change the Verilog used in LargeParamExecutionTest to match its
ExtModule specification. An ExtModule with an SInt port should map to
a separate Verilog module with a signed port and this is disjoint from
an ExtModule with a UInt port.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
* Error on ExtModules w/ same defname, diff. ports
Adds a high form check to ensure that external modules that have the
same defname also have exactly the same ports.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* See #1505
* Inferred mports are implicitly added to scope of their parent mem
* This allows current chisel3 emission to work with new scope checks
* This may change in a future refactor of CHIRRTL memory ports
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* Fixes #1505
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Expression Types are derived. They cannot cause the errors detected by
CheckHighFormLike independently of the user-specified types that remain
chedked. This speeds up CheckChirrtl and CheckHighForm substantially.
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Don't serialize Expressions unless there is an error
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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This mixes in the new DependencyAPIMigration trait into all Transforms
and Passes. This enables in-tree transforms/passes to build without
deprecation warnings associated with the deprecated CircuitForm.
As a consequence of this, every Transform now has UnknownForm as both
its inputForm and outputForm. This PR modifies legacy Compiler and
testing infrastructure to schedule transforms NOT using
mergeTransforms/getLoweringTransforms (which rely on inputForm and
outputForm not being UnknownForm), but instead using the Dependency
API.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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