| Age | Commit message (Collapse) | Author |
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emission-options flags swapped to match their functionality
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* Add option to disable random mem/reg init
Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
* fix for code review.
Co-authored-by: SharzyL <me@sharzy.in>
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* Added RTLIL Backend.
* Add test for Rtlil Backend, fix per-module file emission, scalafmt, and apply bugfixes for inconsistencies found during testing.
* Fix build on scala 2.13
* Add additional equivalence test, make some bugfixes and perf opts to the emitter.
* Final changes as requested by Kevin, code cleanup, add support for formal cells.
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* Add compiler option (`-p`) to emit individual module protobufs
* Implement multi module combination when reading directory of protobufs
Co-authored-by: Jack Koenig <koenig@sifive.com>
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This will make it easier for formal verification
libraries to make use of these emitters.
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* rearrange passes to enable optimized firrtl emission
* Support ConstProp on padded arguments to comparisons with literals
* Move shr legalization logic into ConstProp
Continue calling ConstProp of shr in Legalize.
Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
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* Add Protocol Buffer emission export
This adds infrastructure and annotations that let a user emit a FIRRTL
circuit as a Protocol Buffer.
Fixes #1696.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
* fixup! Add Protocol Buffer emission export
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Add a compiler/emitter that can target minimal high form. This will
produce output that only has CHIRRTL constructs removed.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
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* split big Emitter to submodules.
* fix all deprecated warning.
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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The following conditions must be satisfied to inline:
1. has type Utils.BoolType
2. is bound to a DefNode with name starting with '_'
3. is bound to a DefNode with a source locator that
points at the same file and line number. If it is a MultiInfo source
locator, the set of file and line number pairs must be the same. Source
locators may point to different column numbers.
4. InlineBooleanExpressionsMax has not been exceeded
5. is not a Mux
Also updates the Verilog emitter to break up lines greater than 120 characters
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This adds an experimental new SMTLib and Btor2 emitter
that converts a firrtl module into a format
suitable for open source model checkers.
The format generally follows the behavior of yosys'
write_smt2 and write_btor commands.
To generate btor2 for the module in m.fir run
> ./utils/bin/firrtl -i m.fir -E experimental-btor2
for SMT:
> ./utils/bin/firrtl -i m.fir -E experimental-smt2
If you have a design with multiple clocks
or an asynchronous reset, try out the new StutteringClockTransform.
You can designate any input of type Clock to be your
global simulation clock using the new GlobalClockAnnotation.
If your toplevel module instantiates submodules,
you need to inline them if you want the submodule
logic to be included in the formal model.
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* Transform, not run in LegalizeAndReduction test
Switch from using FirrtlStage.transform to FirrtlStage.run in one
test. The latter is problematic as it doesn't include wrappers or
pre/post phases which are how things will work in the future for doing
file writing (via HowToSerialize ideas).
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
* Use execute in FIRRTL testing infra (not run)
Changes the FirrtlStage method in FIRRTL testing infrastructure from
"run" (which does not include Stage-global Phases) to "execute" (which
does).
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
* Add HowToSerialize Annotation mix-in
This adds an Annotation mix-in, HowToSerialize, that allows an
annotation to declare how it should be serialized to a file. The
mix-in is abstract in a baseFileName and a suffix (used to generate a
filename), a howToSerialize method (defining the string contents of
the file), and a howToResume method (that defines a replacement for
the file-serialized annotation that allows this to be resumed) [^1].
A default implementation for generating a filename (called filename)
is defined that will put the baseFileName+suffix file in the target
directory. This can be overridden by the annotation if desired.
[^1]: When an annotation is serialized to a file, it should be removed
from the emitted JSON-serialized annotations. The howToResume method
defines a way of adding replacement annotations to the JSON-serialized
annotations that tell a downstream tool how to find the serialized
file. E.g., if a FIRRTL circuit is written to a file, this could be
used to add a FirrtlFileAnnotation defining the location of the new
file.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
* Handle HowToSerialize in WriteOutputAnnotations
This extends firrtl.options.phase.WriteOutputAnnotations to serialize
HowToSerialize annotations to files.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
* Test HowToSerialize in WriteOutputAnnotationsSpec
This adds tests of the HowToSerialize mix-in inside the
WriteOutputAnnotationsSpec.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
* [skip chisel tests] Migrate to HowToSerialize
This migrates EmittedAnnotations (and its children) to mixin the
HowToSerialize trait. This enables this annotations to be
automatically written to files via WriteOutputAnnotations
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
* Deprecated firrtl.stage.phases.WriteEmitted
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
* Use streams in HowToSerialize
This converts the HowToSerialize trait to use a Stream[Char] when
defining how an annotation should be serialized.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
* Switch from Stream[Char] to Stream[Byte]
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
* Change howToSerialize method to Iterable
Change the type of the HowToSerialize.howToSerialize method from a
stream to an iterable. Using the latter (the superset of both lazy
streams and non-lazy things like String) avoids problems with users
having to choose laziness when they already have an eager object.
In effect, this makes the API more general.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
* Add Scaladoc to HowToSerialize trait
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
* Change HowToSerialize to CustomFileEmission
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
* Add default implementation of replacements
Add a default implementation of CustomFileEmission.replacements.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
* Avoid unnecessary 2x monad in CustomFileEmission
Change the type of CustomFileEmission.replacements from
Option[AnnotationSeq] to AnnotationSeq. The latter has all the
properties of the former that I'm trying to express here: (1) can
emptiness and (2) monadicity (if the AnnotationSeq is converted to a
sequence first). The latter property is exploited in the
WriteOutputAnnotations phase to concisely flatMap over the annotations
and doing the double-monad is unnecessary.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
* Restrict CustomFileEmission filename API
Change the API of CustomFileEmission to use a final def for the actual
filename. The baseFileName is then made a method with an AnnotationSeq
parameter to allow the filename to change as a function of other
annotations, e.g., by an output circuit annotation.
By restricting this API, we have more control over the default
behavior of where things are written using the fixed behavior of the
filename method---files will always be written using the behavior that
StageOptions define. Previously, if users want customized behavior,
they would need to duplicate this StageOptions functionality (and
likely subtly deviate from the standard behavior and introduce
problems with their build).
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
* Add file conflict behavior for CustomFileEmission
Set behavior of file conflicts in CustomFileEmission to be the
following: No two annotations in the same annotation sequence can
serialize to the same file during the WriteOutputAnnotations phase.
However, if the output annotation file already exists, it will be
overwritten.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
* Return relative path from getBuildFileName
Change FirrtlOptions.getBuildFileName to simply serialize the
underlying Java File instead of converting this to its canonical path.
This should improve the relocatability of files produced by the
CustomFileEmission API.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
* Normalize paths in StageOptions.getBuildFile
Normalize paths inside the getBuildFileName utility of StageOptions.
Add a check to prevent a null pointer dereference.
Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
* Refer to CustomFIleEmission in deprecation message
Co-authored-by: Jack Koenig <koenig@sifive.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
* Simplify CustomFileEmission toBytes implementation
Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
* Use toBytes, not getBytes, in CustomFileEmission
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
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* ir: use Serializer.serialize where possible
* ir.Serializer: serialize MultiInfo correctly
* ir.Serializer: empty body needs to result in a skip statement
The firrtl grammar requires at least one statement.
* ir.Serializer: correctly serialize fixed point types and literals
* Serializer: change Seq -> Iterable in order to be Scala 2.13 compatible
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Extending HashMap is discouraged.
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Move new transforms, recently added, into existing or new sets of
transforms (defined in firrtl.stage.Forms).
One transform is a mandatory low FIRRTL optimization:
- firrtl.transforms.LegalizeAndReductionsTransform
Previously, this was included as a prerequisite of all Verilog
emitters (minimum, normal, and SystemVerilog).
Two transforms associated with converting and removing the new
verification statements are moved into a new set of transforms,
AssertsRemoved:
- firrtl.transforms.formal.ConvertAsserts
- firrtl.transforms.formal.RemoveVerificationStatements
Previously, these transforms were directly added as prerequisites to
the minimum Verilog and normal Verilog emitter, but not the
SystemVerilog emitter.
The designation of inputForm=LowForm for legacy, custom transforms is
updated to include assertion removal transforms as part of their
optionalPrerequisites. This has the effect of continuing to cause
inputForm=LowForm transforms to run as late as possible (right before
the low FIRRTL, minimum Verilog, Verilog, or SystemVeriog emitter).
Tests are updated to reflect the new order in both CustomTransformSpec
and LoweringCompilersSpec.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* add sign-extend const-prop test
* Emitter: don't wrap Neg operand in concat
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* test const prop of addition of negative literals
* Emitter: handle minimum negative values correctly
* update expected verilog in AsyncResetSpec
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* [WIP] Propagate source locators to Verilog if-else emission
* Add and fix tests for reg update info propagation
* Add limited source locator propagation in ConstProp
Support propagating source locators on connections or nodes where the
right-hand side is simply a reference. This case comes up a lot for
registers without a synchronous reset.
node _T_1 = x @[MyFile.scala 12:10]
node _T_2 = _T_1
z <= x
Previousy the source locator would be lost, now the result is:
z <= x @[MyFile.scala 12:10]
* Address review comments
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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This should speed up the common case
as the compiler never operates on the
unescaped string.
The new escape function also fixes a bug
where ']' was not escaped even though it
is the delimiting character for FileInfo.
In order to maintain backwards
compatibility for the ProtoBuf format,
this patch adds escape/unescape calls
when going from/to protobuf format.
For better performance we should consider
changing the protobuf format.
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Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* Add assume, assert, cover statements
* Assert submodule assumptions
* Add warning when removing verification statements
* Remove System Verilog behaviour emitter warning
* Add option to disable AssertSubmoduleAssumptions
* Document verification statements in the spec
The syntax for the new statements is
assert(clk, cond, en, msg)
assume(clk, cond, en, msg)
cover(clk, cond, en, msg)
With assert as a representative example, the semantics is as follows:
`clk` is the clock, `cond` is the expression being asserted, `en` is the
enable signal (if `en` is low then the assert is not checked) and `msg`
is a string message intended to be reported as an error message by the
model checker if the assertion fails.
In the Verilog emitter, the new statements are handled by a new
`formals` map, which groups the statements by clock domain. All model
checking statements are then emitted within the context of an `ifdef
FORMAL` block, which allows model checking tools (like Symbiyosys) to
utilize the statements while keeping them out of synthesis flows.
Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
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* Support Memory Initialization for Simulation and FPGA Flows
This adds a minimal annotation that allows users to
influence if memories are randomly initialized,
if all entries are initialized to the same scalar or
if each entry should be initialized to a different value.
We use the init block in order to initialize memories
which is supported by verilator as well as yosys
and has previously been used to randomize the initial
memory contents.
* LowerTypes: error when trying to split up a memory with MemoryInitAnnotation
Currently the MemoryInitAnnotation only works for
ground-type memories.
We catch misuse of this annotation at the point of
the firrtl compiler at which memories on non-ground type
get split up, i.e., the LowerTypes transform.
Chisel should try to prevent annotating non-ground
type memories in the frontend, but it is nice to
have an additional check.
* MemoryInitSpec: test JSON deserialization
* MemoryInitAnnotation: split up into three different annotations instead of exposing MemoryInitValue
Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* Add attributes, ifdefs to emitter.
* Make ifdef API a little cleaner.
* Remove references to ifdefs.
* Remove more of the ifdef stuff I missed
* Fix up failing tests
* Add multiple attribute test case
* Remove tpe as a parameter from Annotations.
Some general refactoring.
* Add some documentation.
* Incorporate some feedback
* Expand some spaghetti code, add comments
* Fix type signature by removing it
* bug fix in test
* Fix unchecked type parameter matches in AddDescriptionNodes.
* use target to replace name
Co-authored-by: Paul Rigge <rigge@berkeley.edu>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* Absorb WRef into Reference
* Absorb WSubField into SubField
* Absorb WSubIndex into SubIndex
* Absorb WSubAccess into SubAccess
* Absorb WDefInstance into DefInstance
------------------------- API CHANGE SEVERITY --------------------------
This is projected to not break source-level compatibility with any known
user code. However, it will break *binary* compatibility with all
existing user FIRRTL passes, as is generally allowed with major
releases of FIRRTL.
--------------------------- DESCRIPTION --------------------------------
Previously, there were several nodes in WIR.scala that had a one-to-one
correspondance with existing nodes in the standard firrtl.ir hierarchy.
These nodes would have a case class resembling the corresponding
standard IR node, but with the addition of one or more "analysis"
fields.
Since these fields (such as kind) represent helpful info that can be
invalidated or set to Unknown (e.g. UnknownKind for Kind), it does not
cause any issues to simply include these fields on any in-memory
representation of FIRRTL IR. Although other systems for tracking FIRRTL
analyses have evolved over time, the ubiquity of pattern-matching on
these fields has lead most core and custom transforms to be written
against WIR, rather than IR.
This PR unifies the IRs by adding the fields that would be in an
"augmented" WIR node directly into the corresponding IR node; i.e., the
"type" and "kind" fields from WRef are added directly to the definition
of the Reference case class, while these "repetitive" WIR case classes
are removed entirely.
-------------------- SOURCE-COMPATIBILITY ADAPTERS ---------------------
Several object methods are added to WIR.scala to maintain
source-compatiblity for passes that used WIR. These objects define
factory methods and unapply methods, so passes that relied on implicit
case class factories or pattern matching for the removed WIR types will
remain perfectly source-compatible. However, these do not guarantee
compatibility at the binary level.
The types of the removed WIR case classes are also added as type aliases
to the top-level firrtl package, which allows code that relies on
explicit constructor calls or reflection to retain source-compatibility.
Finally, additional explicit factory methods are added to the companion
objects of the newly-augmented IR case classes, which allows user code
to avoid having to specify any of the new analysis fields. Existing code
that created non-WIR IR nodes will be able to continue using the
previous factory signatures, which will cause all omitted analysis
fields to be set to Unknown.
---------------------- UNMITIGATED API CHANGES -------------------------
While passes that used WIR will be source-compatible with this change,
there is one significant change that affects any pass currently using
non-WIR IR: the signatures of pattern-matching cases for Reference,
SubField, SubIndex, SubAccess, and DefInstance must change to
accommodate the extra fields.
This cannot be worked at the API level due to restrictions on unapply
overloading, but it could theoretically be solved with macros or other
static rewriting. However, only four core transforms (RemoveProto,
ToWorkingIR, Dedup, and RemoveChirrtl) use non-WIR IR, and it is
expected that no user code currently relies on it, so the expected
migration strategy is simply to change the small fraction of code
relying on these nodes.
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* Move reg/mem initializations to end of module
* Add comment before reg/mem init if inits exist
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* consolidated wire <type> x; assign x = y; to wire <type> x = y;
* Remove dead code from Emitter.scala
Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
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* adding init macros
* fix missing tick
* adding more documentation; fixing up emitter tests
* adding initial-guarding macro test
* prefixing macros with FIRRTL
* cleanup
* typo fix
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Workaround for https://github.com/verilator/verilator #2300
present in Verilator versions v4.026 - v4.032. This transform turns AND
reductions for expressions > 64-bits into an equality check with all
ones. It is included as a prerequisite for all Verilog emitters.
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* Emitter: add declare functions ifdef guard
* Emitter: add ifdef initials
* Emitter: add comments, cleanup
* Emitter: changes from code review
- make new methods private
- use .withDefault
- remove empty initial block
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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This mixes in the new DependencyAPIMigration trait into all Transforms
and Passes. This enables in-tree transforms/passes to build without
deprecation warnings associated with the deprecated CircuitForm.
As a consequence of this, every Transform now has UnknownForm as both
its inputForm and outputForm. This PR modifies legacy Compiler and
testing infrastructure to schedule transforms NOT using
mergeTransforms/getLoweringTransforms (which rely on inputForm and
outputForm not being UnknownForm), but instead using the Dependency
API.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Fixes a bug where an Emitter was only checking for the presence of an
EmitCircuitAnnotation or EmitAllModulesAnnotation to control its
emission flavor (one-file-per-module or one-file). This changes the
check to ensure that the class of emitter matches that of the
annotation. This allows for correct behavior when mixing different
emitters, e.g., -E high -e middle.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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* Eliminate warnings on `sbt doc` and `sbt unidoc`
- removed toFirrtl reference on MultiTargetAnnotation
- lots of places where package path has to be added to comment references
- Change to use `/** text starts here` convention when wrong in comment with a doc fix.
- Did not exhaustively change these
- Wrestled doc example in RenderDiGraph#renderNode, not sure if I won
- Cleaned up InferWidths & CatchExceptions imports
- Added missing license message to a couple of files.
- fixed a couple of stale parameter names in scaladoc
- Added @unchecked to stop erasure warning in Emitting where emission annotations are collected
- Change types to [_] on match in RenameMap#recordAll to fix erasure warning
* Where possible change [[firrtl.ir.X]] to [[firrtl.ir.X X]] for better display in scaladoc
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Introduce Preset Register Specialized Emission
- Introduce EmissionOption trait
- Introduce PresetAnnotation & PresetRegAnnotation
- Enable the collection of Annotations in the Emitter
- Introduce collection mechanism for EmissionOptions in the Emitter
- Add PropagatePresetAnnotation transform to annotate register for emission and clean-up the useless reset tree (no DCE involved)
- Add corresponding tests spec and tester
Co-authored-by: Jack Koenig <koenig@sifive.com>
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Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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This reverts commit f77487d37bd7c61be231a8000a3197d37cf55499.
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* Generates lint-clean Verilog for the case: x + -1
...where x is anything and 1 is any literal.
Master behavior:
input x : SInt<8>
output z : SInt<9>
z <= add(x, SInt(-2))
generates
assign z = $signed(x) + -8'sh2;
After this PR:
assign z = $signed(x) - 8'sh2;
If the literal is the maximum possible literal, a special case is triggered to properly trim the resulting subtraction.
Input:
input x : SInt<2>
output z : SInt<3>
z <= add(x, SInt(-2))
now generates (after this PR)
assign z = $signed(x) - 3'sh2;
* Updated documentation
* Change ArrayBuffer to ListBuffer
* Change name to minNegValue
* Remove mutable public interfaces
Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* transform InlineBitExtractions
* InlineNotsTransform, InlineBitExtractionsTransform: inputForm/outputForm = UnknownForm
* clean up some minor redundancies from Adam review
* clarifications from Seldrige review
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