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path: root/src/main/scala/firrtl/Emitter.scala
AgeCommit message (Expand)Author
2022-01-25emission-options flags swapped (#2472)Andrea Nardi
2021-12-27disable random should not contain useInitAsPreset. (#2449)Jiuyang Liu
2021-11-19Disable random init (#2396)Jiuyang Liu
2021-09-29Add RTLIL Backend. (#2331)Nicolas Machado
2021-09-08Multi protobuf module emission and consumption (#2344)Jared Barocsi
2021-08-10[smt] make SMTLib + Btor2 emitters public objects (#2326)Kevin Laeufer
2021-08-02add emitter for optimized low firrtl (#2304)Kevin Laeufer
2021-06-17Add Protocol Buffer emission (#2271)Schuyler Eldridge
2021-06-14Add -X mhigh compiler for minimal high form (#2268)Schuyler Eldridge
2020-11-10Refactor emiter (#1879)Jiuyang Liu
2020-09-16Change to Apache 2.0 License (#1901)Chick Markley
2020-08-31Emitter: add missing parenthesize calls (#1874)Albert Chen
2020-08-26Emit parentheses in Verilog for nested unary ops (#1865)Jack Koenig
2020-08-25Inline Boolean Expressions (#1817)Albert Chen
2020-08-14All of src/ formatted with scalafmtchick
2020-08-15experimental SMTLib and btor2 emitter (#1826)Kevin Laeufer
2020-08-11File Serialization of Annotations (#1277)Schuyler Eldridge
2020-07-30ir: use Serializer.serialize where possible (#1809)Kevin Laeufer
2020-07-29[2.13] fix legacy procedure syntaxKevin Laeufer
2020-07-29[2.13] EmissionOptionMap now uses a HashMap instead of extending itKevin Laeufer
2020-07-29[2.13] replace `= Unit` with `= ()`Kevin Laeufer
2020-07-29[2.13] convert toSeq and toMap where necessary to compileKevin Laeufer
2020-07-25Integrate new transforms with firrtl.stage.Forms (#1754)Schuyler Eldridge
2020-07-24Fix sign extension issue in Emitter (#1785)Albert Chen
2020-07-23Update negative literal emission (#1782)Albert Chen
2020-07-17Propagate source locators to register update always blocks (#1743)Jack Koenig
2020-07-15ir: store FileInfo string in escaped format (#1690)Kevin Laeufer
2020-07-07verification: emit mesage as Verilog comment (#1712)Kevin Laeufer
2020-06-26Enable ConvertAsserts in default Verilog compilerAlbert Magyar
2020-06-23Basic model checking API (#1653)Tom Alcorn
2020-06-22Support Memory Initialization for Simulation and FPGA Flows (#1645)Kevin Laeufer
2020-06-22recore of Attributes (#1643)Jiuyang Liu
2020-05-26[API change] Absorb repetitive WIR nodes into IRAlbert Magyar
2020-05-14Move Reg/Mem initializations to end of module (#1613)Deborah Soung
2020-05-13consolidated wire+assign to just wire, with expression inlined (#1600)Murali Vijayaraghavan
2020-05-05before/after initial block macros (#1550)Deborah Soung
2020-05-04Add LegalizeAndReductionsTransformJack Koenig
2020-05-01Emitter: guard _RAND_* declarations with ifdef (#1548)Albert Chen
2020-04-22s/dependents/optionalPrerequisiteOf/Schuyler Eldridge
2020-04-22Mixin DependencyAPIMigration to all TransformsSchuyler Eldridge
2020-04-13Check EmitAnnotation class before emittingSchuyler Eldridge
2020-04-13move asyncInitials inside initial block RANDOMIZE ifdef (#1510)John Ingalls
2020-03-26Eliminate warnings on `sbt doc` and `sbt unidoc` (#1470)Chick Markley
2020-03-12Add Support for FPGA Bitstream Preset-registers (#1050)John's Brew
2020-03-11Migrate to DependencyAPISchuyler Eldridge
2020-03-04Revert "Verilog emitter transform InlineNots (#1270)"Albert Magyar
2020-02-12Fixing lint error: x + -1 (#1374)Adam Izraelevitz
2020-02-06Emit 'else' case for trivial-valued async reset regs to avoid latches (#1359)Albert Magyar
2020-01-21Refactoring checkCatArgumentLegality (#1317)Derek Pappas
2020-01-15Verilog emitter transform InlineBitExtractions (#1296)John Ingalls
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