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2021-03-03Fix ProtoBuf conversions for Verification IR (#2100)Deborah Soung
2020-09-16Change to Apache 2.0 License (#1901)Chick Markley
2020-06-23Basic model checking API (#1653)Tom Alcorn
* Add assume, assert, cover statements * Assert submodule assumptions * Add warning when removing verification statements * Remove System Verilog behaviour emitter warning * Add option to disable AssertSubmoduleAssumptions * Document verification statements in the spec The syntax for the new statements is assert(clk, cond, en, msg) assume(clk, cond, en, msg) cover(clk, cond, en, msg) With assert as a representative example, the semantics is as follows: `clk` is the clock, `cond` is the expression being asserted, `en` is the enable signal (if `en` is low then the assert is not checked) and `msg` is a string message intended to be reported as an error message by the model checker if the assertion fails. In the Verilog emitter, the new statements are handled by a new `formals` map, which groups the statements by clock domain. All model checking statements are then emitted within the context of an `ifdef FORMAL` block, which allows model checking tools (like Symbiyosys) to utilize the statements while keeping them out of synthesis flows. Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
2019-10-18Upstream intervals (#870)Adam Izraelevitz
Major features: - Added Interval type, as well as PrimOps asInterval, clip, wrap, and sqz. - Changed PrimOp names: bpset -> setp, bpshl -> incp, bpshr -> decp - Refactored width/bound inferencer into a separate constraint solver - Added transforms to infer, trim, and remove interval bounds - Tests for said features Plan to be released with 1.3
2019-09-30Improve read-under-write parameter supportAlbert Magyar
* Make the read-under-write (RUW) parameter typesafe * Add RUW support to the FIRRTL proto and CHIRRTL grammar
2019-08-13Infer reset (#1068)Jack Koenig
* Add abstract "Reset" which can be inferred to AsyncReset or UInt<1> * Enhance async reset initial value literal check to support aggregates
2019-04-22Change Memory Depth to a BigInt (#1075)Jack Koenig
2019-02-14Asynchronous Reset (#1011)Jack Koenig
Fixes #219 * Adds AsyncResetType (similar to ClockType) * Registers with reset signal of type AsyncResetType are async reset registers * Registers with async reset can only be reset to literal values * Add initialization logic for async reset registers
2018-06-28Protobuf (#832)Jack Koenig
Add support for ProtoBuf serialization and deserialization * Add support for additional features in .proto description Features added: Info, Fixed[Type|Literal], AnalogType, Attach, Params * Add support for .pb input files This involves an API change where FIRRTL no longer implicitly adds .fir to input file names
2018-03-19Adding the firrtl proto. (#746)Kevin Townsend
* Adding the firrtl proto. * .