Protobuf (#832)

Add support for ProtoBuf serialization and deserialization

* Add support for additional features in .proto description

Features added: Info, Fixed[Type|Literal], AnalogType, Attach, Params

* Add support for .pb input files

This involves an API change where FIRRTL no longer implicitly adds .fir
to input file names

1 files changed, 55 insertions, 3 deletions

diff --git a/src/main/proto/firrtl.proto b/src/main/proto/firrtl.proto
index 3e2d848c..7be042ab 100644
--- a/src/main/proto/firrtl.proto
+++ b/src/main/proto/firrtl.proto
@@ -34,9 +34,15 @@ message Firrtl {
     oneof source_info {
       None none = 1;
       Position position = 2;
+      string text = 3;
     }
   }
 
+  message BigInt {
+    // 2's complement binary representation
+    bytes value = 1;
+  }
+
   message Top {
     // Required.
     string name = 1;
@@ -49,9 +55,20 @@ message Firrtl {
 
   message Module {
     message ExternalModule {
+      message Parameter {
+        string id = 1;
+        oneof value {
+          BigInt integer = 2;
+          double double = 3;
+          string string = 4;
+          string raw_string = 5;
+        }
+      }
       // Required.
       string id = 1;
       repeated Port port = 2;
+      string defined_name = 3;
+      repeated Parameter parameter = 4;
     }
 
     message UserModule {
@@ -100,6 +117,7 @@ message Firrtl {
       uint32 read_latency = 5;
       repeated string reader_id = 6;
       repeated string writer_id = 7;
+      repeated string readwriter_id = 8;
     }
 
     message CMemory {
@@ -107,6 +125,8 @@ message Firrtl {
       string id = 1;
       // Required.
       Type.VectorType type = 2;
+      // Required.
+      bool sync_read = 3;
     }
 
     message Instance {
@@ -141,7 +161,7 @@ message Firrtl {
 
     message Printf {
       // Required.
-      bytes value = 1;
+      string value = 1;
       repeated Expression arg = 2;
       // Required.
       Expression clk = 3;
@@ -195,6 +215,10 @@ message Firrtl {
       Expression expression = 5;
     }
 
+    message Attach {
+      repeated Expression expression = 1;
+    }
+
     // Required.
     oneof statement {
       Wire wire = 1;
@@ -211,6 +235,7 @@ message Firrtl {
       PartialConnect partial_connect = 16;
       IsInvalid is_invalid = 17;
       MemoryPort memory_port = 18;
+      Attach attach = 20;
     }
 
     SourceInfo source_info = 19;
@@ -256,13 +281,24 @@ message Firrtl {
       uint32 size = 2;
     }
 
+    message FixedType {
+      Width width = 1;
+      Width point = 2;
+    }
+
+    message AnalogType {
+      Width width = 3;
+    }
+
     // Required.
     oneof type {
       UIntType uint_type = 2;
       SIntType sint_type = 3;
       ClockType clock_type = 4;
-      RecordType record_type = 5;
+      BundleType bundle_type = 5;
       VectorType vector_type = 6;
+      FixedType fixed_type = 7;
+      AnalogType analog_type = 8;
     }
   }
 
@@ -306,6 +342,12 @@ message Firrtl {
       Width width = 2;
     }
 
+    message FixedLiteral {
+      BigInt value = 1;
+      Width width = 2;
+      Width point = 3;
+    }
+
     message ValidIf {
       // Required.
       Expression condition = 1;
@@ -376,6 +418,13 @@ message Firrtl {
         OP_AS_UINT = 28;
         OP_AS_SINT = 29;
         OP_EXTRACT_BITS = 30;
+        OP_AS_CLOCK = 31;
+        OP_AS_FIXED_POINT = 32;
+        OP_AND_REDUCE = 33;
+        OP_OR_REDUCE = 34;
+        OP_SHIFT_BINARY_POINT_LEFT = 35;
+        OP_SHIFT_BINARY_POINT_RIGHT = 36;
+        OP_SET_BINARY_POINT = 37;
       }
 
       // Required.
@@ -384,13 +433,16 @@ message Firrtl {
       repeated IntegerLiteral const = 3;
     }
 
+    reserved 5;
+
     // Required.
     oneof expression {
       Reference reference = 1;
       UIntLiteral uint_literal = 2;
       SIntLiteral sint_literal = 3;
+      FixedLiteral fixed_literal = 11;
       ValidIf valid_if = 4;
-      ExtractBits extract_bits = 5;
+      //ExtractBits extract_bits = 5;
       Mux mux = 6;
       SubField sub_field = 7;
       SubIndex sub_index = 8;