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AgeCommit message (Expand)Author
2016-01-16WIPazidar
2016-01-16WIP need to correctly output readwrite portsazidar
2015-10-06Updated spec to mention sign extending widths of operand inputsazidar
2015-09-24Added poison node to specazidar
2015-09-01Added cases of undefined behavior for cmem and smemazidar
2015-08-31Changed Bulk to Partial, <> to <-, and := to <=azidar
2015-08-31Updated specazidar
2015-07-23Updated specazidar
2015-07-22Minor updates to specazidar
2015-07-14Still partial commit, many tests pass. Many tests fail.azidar
2015-06-30Updated TODO. Ran spelling/grammar check on specazidar
2015-06-29Fixed minor typos. As of now, the finished version for internal feedback.azidar
2015-06-26Changed clock from port kind to typeazidar
2015-06-26Finished draft of Version 0.1.3. Ready for comments.azidar
2015-06-23More updates to specazidar
2015-06-22Updated spec to remove Register,WritePort,ReadPort,RdWrPort,biaccessorsazidar
2015-06-12Added more changes to specazidar
2015-06-12Major revisions to spec. Bumped to v0.1.2azidar
2015-06-05Added most recent pdfazidar
2015-05-26Added <>. Added additional checks for primops. Added new chisel3 files.azidar
2015-05-18Big API Change. Pad is no longer supported. Widths of primops can be flexible...azidar
2015-05-13Updated Spec. Added scoped-reg which exposes on-reset bug. Fixed lowering bugazidar
2015-04-15Finished flo backend. Restructured todo listazidar
2015-04-08Finished expand whens. started infer widths. added pdf for people to viewazidar
2015-03-10Finished resolve gendersazidar
2015-03-04Finished infer-types passazidar
2015-03-03In progress for type inference. Looks like other code is breaking, and i dont...azidar
2015-03-03Updated TODO and specazidar
2015-03-02Updated spec to have primops changes.azidar
2015-02-27Updated spec to have new primopsazidar
2015-02-13First commit.azidar
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