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| author | azidar | 2015-11-06 09:51:59 -0800 |
|---|---|---|
| committer | azidar | 2016-01-16 14:28:16 -0800 |
| commit | ffa090c10d6210395e3f304e56008e2183a85698 (patch) | |
| tree | 25fce98795c897f655a4e6dd2f2ebf866e9c3049 /spec | |
| parent | 407200e46de9a97f8a88c210e3b0e7d6d38f307b (diff) | |
WIP
Diffstat (limited to 'spec')
| -rw-r--r-- | spec/spec.tex | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/spec/spec.tex b/spec/spec.tex index 4f146552..09fed6b7 100644 --- a/spec/spec.tex +++ b/spec/spec.tex @@ -990,8 +990,8 @@ The output width of a dynamic shift left operation is the width of the original \[ \begin{array}{rll} \kws{primop} & \kws{Resultant Type} & \kws{Resultant Width} \\ -\kws{dshr}(\pds{op}:UInt, \pds{op2}:UInt) & UInt & width(op) \\ -\kws{dshr}(\pds{op}:SInt, \pds{op2}:UInt) & SInt & width(op) \\ +\kws{dshr}(\pds{op1}:UInt, \pds{op2}:UInt) & UInt & width(op1) \\ +\kws{dshr}(\pds{op1}:SInt, \pds{op2}:UInt) & SInt & width(op1) \\ \end{array} \] The shift right operation accepts either an unsigned or a signed integer, plus a non-negative integer literal specifying the number of bits to shift. |