sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Collapse)	Author
2020-09-16	Change to Apache 2.0 License (#1901)	Chick Markley

2020-03-04	Incorporate new AddNot formal regression test	Albert Magyar
	* Feedback from @jackkoening * Merge into same stage as Ops to avoid Travis delays
2020-02-13	Add Ops equiv check to stress degenerate binary op ConstProp	Albert Magyar
	* Send in the Yosys
2019-03-29	Faster reg constprop (#1067)	Albert Magyar
	* Improve memoization for register const prop
2018-02-21	Change primop arg type (#587)	Adam Izraelevitz
	* Changed primops to not accept mixed-type args * Changed return type of sub of two uints to uint * Added negative tests * Removed rocket.fir. Manually changed RocketCore to not mix mul arg types. Added integration tests * Clarified test description and remove println * Fixed use of throwInternalError
2017-12-12	Refactor formal equivalence CI test	Jack Koenig
	Make the check script allow different designs Add FPU, ICache, and RocketCore to regress and use instead of Rob for CI equivalence check
2017-03-15	Use newer rocket regression spec without comb loop	Albert Magyar

2016-09-14	Added Rob.fir for regression testing (#258)	Donggyu

2016-02-25	Remove brittle rocket comparison to expected verilog test.	jackkoenig

2016-02-24	Make rocket-golden.v match output of #75	jackkoenig

2016-02-23	Add rocket regression, just runs rocket.fir through Verilog compiler and ↵	Jack
	compares to expected Verilog. Uses ScalaTest. Should be eventually replaced with actual simulation of rocket-chip
2016-02-09	CHIRRTL passes work, parser is updated	azidar

2016-02-09	Added rocket minus chirrtl features	azidar

2016-01-28	Update rocket regression	Andrew Waterman

2016-01-23	Update rocket regression	Andrew Waterman

2016-01-16	WIP need to correctly output readwrite ports	azidar

2015-08-26	Added regression test	azidar