diff options
| author | Albert Magyar | 2019-03-29 17:09:57 -0700 |
|---|---|---|
| committer | GitHub | 2019-03-29 17:09:57 -0700 |
| commit | 9535e03020c6e654dae3ce7e95f4d8649405ce3d (patch) | |
| tree | d926ac7d29ac2ee6eec3d21193eb73a0a9dbdb79 /regress | |
| parent | 883548c673ef6496c3b281b0011153a11541584d (diff) | |
Faster reg constprop (#1067)
* Improve memoization for register const prop
Diffstat (limited to 'regress')
| -rw-r--r-- | regress/HwachaSequencer.fir | 6777 |
1 files changed, 6777 insertions, 0 deletions
diff --git a/regress/HwachaSequencer.fir b/regress/HwachaSequencer.fir new file mode 100644 index 00000000..b217c810 --- /dev/null +++ b/regress/HwachaSequencer.fir @@ -0,0 +1,6777 @@ +circuit HwachaSequencer : + module HwachaSequencer : + input clock : Clock + input reset : UInt<1> + output io : {flip op : {flip ready : UInt<1>, valid : UInt<1>, bits : {fn : {union : UInt<10>}, sreg : {ss1 : UInt<64>, ss2 : UInt<64>, ss3 : UInt<64>}, base : {vp : {id : UInt<4>, valid : UInt<1>, scalar : UInt<1>, pred : UInt<1>}, vs1 : {id : UInt<8>, valid : UInt<1>, scalar : UInt<1>, pred : UInt<1>, prec : UInt<2>}, vs2 : {id : UInt<8>, valid : UInt<1>, scalar : UInt<1>, pred : UInt<1>, prec : UInt<2>}, vs3 : {id : UInt<8>, valid : UInt<1>, scalar : UInt<1>, pred : UInt<1>, prec : UInt<2>}, vd : {id : UInt<8>, valid : UInt<1>, scalar : UInt<1>, pred : UInt<1>, prec : UInt<2>}}, reg : {vp : {id : UInt<8>}, vs1 : {id : UInt<8>}, vs2 : {id : UInt<8>}, vs3 : {id : UInt<8>}, vd : {id : UInt<8>}}, active : {vint : UInt<1>, vipred : UInt<1>, vimul : UInt<1>, vidiv : UInt<1>, vfma : UInt<1>, vfdiv : UInt<1>, vfcmp : UInt<1>, vfconv : UInt<1>, vrpred : UInt<1>, vrfirst : UInt<1>, vamo : UInt<1>, vldx : UInt<1>, vstx : UInt<1>, vld : UInt<1>, vst : UInt<1>}}}, master : {state : {valid : UInt<1>[8], e : {fn : {union : UInt<10>}, sreg : {ss1 : UInt<64>, ss2 : UInt<64>, ss3 : UInt<64>}, base : {vp : {id : UInt<4>, valid : UInt<1>, scalar : UInt<1>, pred : UInt<1>}, vs1 : {id : UInt<8>, valid : UInt<1>, scalar : UInt<1>, pred : UInt<1>, prec : UInt<2>}, vs2 : {id : UInt<8>, valid : UInt<1>, scalar : UInt<1>, pred : UInt<1>, prec : UInt<2>}, vs3 : {id : UInt<8>, valid : UInt<1>, scalar : UInt<1>, pred : UInt<1>, prec : UInt<2>}, vd : {id : UInt<8>, valid : UInt<1>, scalar : UInt<1>, pred : UInt<1>, prec : UInt<2>}}, rate : UInt<1>, active : {viu : UInt<1>, vipu : UInt<1>, vimu : UInt<1>, vidu : UInt<1>, vfmu : UInt<1>, vfdu : UInt<1>, vfcu : UInt<1>, vfvu : UInt<1>, vrpu : UInt<1>, vrfu : UInt<1>, vpu : UInt<1>, vgu : UInt<1>, vcu : UInt<1>, vlu : UInt<1>, vsu : UInt<1>, vqu : UInt<1>}, raw : UInt<1>[8], war : UInt<1>[8], waw : UInt<1>[8], last : UInt<1>, rports : UInt<2>, wport : {sram : UInt<4>, pred : UInt<3>}}[8], head : UInt<3>}, update : {valid : UInt<1>[8], reg : {vp : {id : UInt<8>}, vs1 : {id : UInt<8>}, vs2 : {id : UInt<8>}, vs3 : {id : UInt<8>}, vd : {id : UInt<8>}}[8]}, flip clear : UInt<1>[8]}, pending : {mem : UInt<1>, all : UInt<1>}, vf : {flip stop : UInt<1>, last : UInt<1>}, counters : {memoryUOps : UInt<3>, arithUOps : UInt<3>, predUOps : UInt<3>}, debug : {head : UInt<3>, tail : UInt<3>, maybe_full : UInt<1>, empty : UInt<4>}} + + clock is invalid + reset is invalid + io is invalid + wire _T : UInt<1>[8] @[compatibility.scala 120:12] + _T is invalid @[compatibility.scala 120:12] + _T[0] <= UInt<1>("h00") @[compatibility.scala 120:12] + _T[1] <= UInt<1>("h00") @[compatibility.scala 120:12] + _T[2] <= UInt<1>("h00") @[compatibility.scala 120:12] + _T[3] <= UInt<1>("h00") @[compatibility.scala 120:12] + _T[4] <= UInt<1>("h00") @[compatibility.scala 120:12] + _T[5] <= UInt<1>("h00") @[compatibility.scala 120:12] + _T[6] <= UInt<1>("h00") @[compatibility.scala 120:12] + _T[7] <= UInt<1>("h00") @[compatibility.scala 120:12] + reg v : UInt<1>[8], clock with : (reset => (reset, _T)) @[sequencer-master.scala 107:14] + reg e : {fn : {union : UInt<10>}, sreg : {ss1 : UInt<64>, ss2 : UInt<64>, ss3 : UInt<64>}, base : {vp : {id : UInt<4>, valid : UInt<1>, scalar : UInt<1>, pred : UInt<1>}, vs1 : {id : UInt<8>, valid : UInt<1>, scalar : UInt<1>, pred : UInt<1>, prec : UInt<2>}, vs2 : {id : UInt<8>, valid : UInt<1>, scalar : UInt<1>, pred : UInt<1>, prec : UInt<2>}, vs3 : {id : UInt<8>, valid : UInt<1>, scalar : UInt<1>, pred : UInt<1>, prec : UInt<2>}, vd : {id : UInt<8>, valid : UInt<1>, scalar : UInt<1>, pred : UInt<1>, prec : UInt<2>}}, rate : UInt<1>, active : {viu : UInt<1>, vipu : UInt<1>, vimu : UInt<1>, vidu : UInt<1>, vfmu : UInt<1>, vfdu : UInt<1>, vfcu : UInt<1>, vfvu : UInt<1>, vrpu : UInt<1>, vrfu : UInt<1>, vpu : UInt<1>, vgu : UInt<1>, vcu : UInt<1>, vlu : UInt<1>, vsu : UInt<1>, vqu : UInt<1>}, raw : UInt<1>[8], war : UInt<1>[8], waw : UInt<1>[8], last : UInt<1>, rports : UInt<2>, wport : {sram : UInt<4>, pred : UInt<3>}}[8], clock @[sequencer-master.scala 109:14] + reg maybe_full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[sequencer-master.scala 111:23] + reg head : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[sequencer-master.scala 112:17] + reg tail : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[sequencer-master.scala 113:17] + io.master.state.valid <- v @[sequencer-master.scala 115:25] + io.master.state.e <- e @[sequencer-master.scala 116:21] + io.master.state.head <= head @[sequencer-master.scala 117:24] + wire _T_1 : UInt<1>[8] @[sequencer-master.scala 125:27] + _T_1 is invalid @[sequencer-master.scala 125:27] + wire _T_2 : UInt<1>[8][8] @[sequencer-master.scala 126:24] + _T_2 is invalid @[sequencer-master.scala 126:24] + wire _T_3 : UInt<1>[8][8] @[sequencer-master.scala 127:24] + _T_3 is invalid @[sequencer-master.scala 127:24] + wire _T_4 : UInt<1>[8][8] @[sequencer-master.scala 128:24] + _T_4 is invalid @[sequencer-master.scala 128:24] + node _T_5 = and(v[0], e[0].base.vd.valid) @[sequencer-master.scala 136:44] + node _T_6 = and(_T_5, io.op.bits.base.vp.valid) @[sequencer-master.scala 137:32] + node _T_7 = eq(e[0].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_8 = and(_T_7, e[0].base.vd.scalar) @[types-vxu.scala 119:37] + node _T_9 = eq(_T_8, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_10 = and(_T_6, _T_9) @[sequencer-master.scala 137:62] + node _T_11 = eq(io.op.bits.base.vp.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_12 = and(_T_11, io.op.bits.base.vp.scalar) @[types-vxu.scala 119:37] + node _T_13 = eq(_T_12, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_14 = and(_T_10, _T_13) @[sequencer-master.scala 138:39] + node _T_15 = eq(e[0].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_16 = eq(e[0].base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_17 = and(_T_15, _T_16) @[types-vxu.scala 120:37] + node _T_18 = eq(io.op.bits.base.vp.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_19 = eq(io.op.bits.base.vp.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_20 = and(_T_18, _T_19) @[types-vxu.scala 120:37] + node _T_21 = and(_T_17, _T_20) @[sequencer-master.scala 139:39] + node _T_22 = and(e[0].base.vd.pred, io.op.bits.base.vp.pred) @[sequencer-master.scala 140:37] + node _T_23 = or(_T_21, _T_22) @[sequencer-master.scala 139:75] + node _T_24 = and(_T_14, _T_23) @[sequencer-master.scala 138:76] + node _T_25 = eq(e[0].base.vd.id, io.op.bits.base.vp.id) @[sequencer-master.scala 141:29] + node _T_26 = and(_T_24, _T_25) @[sequencer-master.scala 140:72] + node _T_27 = and(v[1], e[1].base.vd.valid) @[sequencer-master.scala 136:44] + node _T_28 = and(_T_27, io.op.bits.base.vp.valid) @[sequencer-master.scala 137:32] + node _T_29 = eq(e[1].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_30 = and(_T_29, e[1].base.vd.scalar) @[types-vxu.scala 119:37] + node _T_31 = eq(_T_30, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_32 = and(_T_28, _T_31) @[sequencer-master.scala 137:62] + node _T_33 = eq(io.op.bits.base.vp.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_34 = and(_T_33, io.op.bits.base.vp.scalar) @[types-vxu.scala 119:37] + node _T_35 = eq(_T_34, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_36 = and(_T_32, _T_35) @[sequencer-master.scala 138:39] + node _T_37 = eq(e[1].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_38 = eq(e[1].base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_39 = and(_T_37, _T_38) @[types-vxu.scala 120:37] + node _T_40 = eq(io.op.bits.base.vp.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_41 = eq(io.op.bits.base.vp.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_42 = and(_T_40, _T_41) @[types-vxu.scala 120:37] + node _T_43 = and(_T_39, _T_42) @[sequencer-master.scala 139:39] + node _T_44 = and(e[1].base.vd.pred, io.op.bits.base.vp.pred) @[sequencer-master.scala 140:37] + node _T_45 = or(_T_43, _T_44) @[sequencer-master.scala 139:75] + node _T_46 = and(_T_36, _T_45) @[sequencer-master.scala 138:76] + node _T_47 = eq(e[1].base.vd.id, io.op.bits.base.vp.id) @[sequencer-master.scala 141:29] + node _T_48 = and(_T_46, _T_47) @[sequencer-master.scala 140:72] + node _T_49 = and(v[2], e[2].base.vd.valid) @[sequencer-master.scala 136:44] + node _T_50 = and(_T_49, io.op.bits.base.vp.valid) @[sequencer-master.scala 137:32] + node _T_51 = eq(e[2].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_52 = and(_T_51, e[2].base.vd.scalar) @[types-vxu.scala 119:37] + node _T_53 = eq(_T_52, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_54 = and(_T_50, _T_53) @[sequencer-master.scala 137:62] + node _T_55 = eq(io.op.bits.base.vp.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_56 = and(_T_55, io.op.bits.base.vp.scalar) @[types-vxu.scala 119:37] + node _T_57 = eq(_T_56, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_58 = and(_T_54, _T_57) @[sequencer-master.scala 138:39] + node _T_59 = eq(e[2].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_60 = eq(e[2].base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_61 = and(_T_59, _T_60) @[types-vxu.scala 120:37] + node _T_62 = eq(io.op.bits.base.vp.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_63 = eq(io.op.bits.base.vp.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_64 = and(_T_62, _T_63) @[types-vxu.scala 120:37] + node _T_65 = and(_T_61, _T_64) @[sequencer-master.scala 139:39] + node _T_66 = and(e[2].base.vd.pred, io.op.bits.base.vp.pred) @[sequencer-master.scala 140:37] + node _T_67 = or(_T_65, _T_66) @[sequencer-master.scala 139:75] + node _T_68 = and(_T_58, _T_67) @[sequencer-master.scala 138:76] + node _T_69 = eq(e[2].base.vd.id, io.op.bits.base.vp.id) @[sequencer-master.scala 141:29] + node _T_70 = and(_T_68, _T_69) @[sequencer-master.scala 140:72] + node _T_71 = and(v[3], e[3].base.vd.valid) @[sequencer-master.scala 136:44] + node _T_72 = and(_T_71, io.op.bits.base.vp.valid) @[sequencer-master.scala 137:32] + node _T_73 = eq(e[3].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_74 = and(_T_73, e[3].base.vd.scalar) @[types-vxu.scala 119:37] + node _T_75 = eq(_T_74, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_76 = and(_T_72, _T_75) @[sequencer-master.scala 137:62] + node _T_77 = eq(io.op.bits.base.vp.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_78 = and(_T_77, io.op.bits.base.vp.scalar) @[types-vxu.scala 119:37] + node _T_79 = eq(_T_78, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_80 = and(_T_76, _T_79) @[sequencer-master.scala 138:39] + node _T_81 = eq(e[3].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_82 = eq(e[3].base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_83 = and(_T_81, _T_82) @[types-vxu.scala 120:37] + node _T_84 = eq(io.op.bits.base.vp.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_85 = eq(io.op.bits.base.vp.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_86 = and(_T_84, _T_85) @[types-vxu.scala 120:37] + node _T_87 = and(_T_83, _T_86) @[sequencer-master.scala 139:39] + node _T_88 = and(e[3].base.vd.pred, io.op.bits.base.vp.pred) @[sequencer-master.scala 140:37] + node _T_89 = or(_T_87, _T_88) @[sequencer-master.scala 139:75] + node _T_90 = and(_T_80, _T_89) @[sequencer-master.scala 138:76] + node _T_91 = eq(e[3].base.vd.id, io.op.bits.base.vp.id) @[sequencer-master.scala 141:29] + node _T_92 = and(_T_90, _T_91) @[sequencer-master.scala 140:72] + node _T_93 = and(v[4], e[4].base.vd.valid) @[sequencer-master.scala 136:44] + node _T_94 = and(_T_93, io.op.bits.base.vp.valid) @[sequencer-master.scala 137:32] + node _T_95 = eq(e[4].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_96 = and(_T_95, e[4].base.vd.scalar) @[types-vxu.scala 119:37] + node _T_97 = eq(_T_96, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_98 = and(_T_94, _T_97) @[sequencer-master.scala 137:62] + node _T_99 = eq(io.op.bits.base.vp.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_100 = and(_T_99, io.op.bits.base.vp.scalar) @[types-vxu.scala 119:37] + node _T_101 = eq(_T_100, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_102 = and(_T_98, _T_101) @[sequencer-master.scala 138:39] + node _T_103 = eq(e[4].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_104 = eq(e[4].base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_105 = and(_T_103, _T_104) @[types-vxu.scala 120:37] + node _T_106 = eq(io.op.bits.base.vp.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_107 = eq(io.op.bits.base.vp.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_108 = and(_T_106, _T_107) @[types-vxu.scala 120:37] + node _T_109 = and(_T_105, _T_108) @[sequencer-master.scala 139:39] + node _T_110 = and(e[4].base.vd.pred, io.op.bits.base.vp.pred) @[sequencer-master.scala 140:37] + node _T_111 = or(_T_109, _T_110) @[sequencer-master.scala 139:75] + node _T_112 = and(_T_102, _T_111) @[sequencer-master.scala 138:76] + node _T_113 = eq(e[4].base.vd.id, io.op.bits.base.vp.id) @[sequencer-master.scala 141:29] + node _T_114 = and(_T_112, _T_113) @[sequencer-master.scala 140:72] + node _T_115 = and(v[5], e[5].base.vd.valid) @[sequencer-master.scala 136:44] + node _T_116 = and(_T_115, io.op.bits.base.vp.valid) @[sequencer-master.scala 137:32] + node _T_117 = eq(e[5].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_118 = and(_T_117, e[5].base.vd.scalar) @[types-vxu.scala 119:37] + node _T_119 = eq(_T_118, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_120 = and(_T_116, _T_119) @[sequencer-master.scala 137:62] + node _T_121 = eq(io.op.bits.base.vp.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_122 = and(_T_121, io.op.bits.base.vp.scalar) @[types-vxu.scala 119:37] + node _T_123 = eq(_T_122, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_124 = and(_T_120, _T_123) @[sequencer-master.scala 138:39] + node _T_125 = eq(e[5].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_126 = eq(e[5].base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_127 = and(_T_125, _T_126) @[types-vxu.scala 120:37] + node _T_128 = eq(io.op.bits.base.vp.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_129 = eq(io.op.bits.base.vp.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_130 = and(_T_128, _T_129) @[types-vxu.scala 120:37] + node _T_131 = and(_T_127, _T_130) @[sequencer-master.scala 139:39] + node _T_132 = and(e[5].base.vd.pred, io.op.bits.base.vp.pred) @[sequencer-master.scala 140:37] + node _T_133 = or(_T_131, _T_132) @[sequencer-master.scala 139:75] + node _T_134 = and(_T_124, _T_133) @[sequencer-master.scala 138:76] + node _T_135 = eq(e[5].base.vd.id, io.op.bits.base.vp.id) @[sequencer-master.scala 141:29] + node _T_136 = and(_T_134, _T_135) @[sequencer-master.scala 140:72] + node _T_137 = and(v[6], e[6].base.vd.valid) @[sequencer-master.scala 136:44] + node _T_138 = and(_T_137, io.op.bits.base.vp.valid) @[sequencer-master.scala 137:32] + node _T_139 = eq(e[6].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_140 = and(_T_139, e[6].base.vd.scalar) @[types-vxu.scala 119:37] + node _T_141 = eq(_T_140, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_142 = and(_T_138, _T_141) @[sequencer-master.scala 137:62] + node _T_143 = eq(io.op.bits.base.vp.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_144 = and(_T_143, io.op.bits.base.vp.scalar) @[types-vxu.scala 119:37] + node _T_145 = eq(_T_144, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_146 = and(_T_142, _T_145) @[sequencer-master.scala 138:39] + node _T_147 = eq(e[6].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_148 = eq(e[6].base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_149 = and(_T_147, _T_148) @[types-vxu.scala 120:37] + node _T_150 = eq(io.op.bits.base.vp.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_151 = eq(io.op.bits.base.vp.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_152 = and(_T_150, _T_151) @[types-vxu.scala 120:37] + node _T_153 = and(_T_149, _T_152) @[sequencer-master.scala 139:39] + node _T_154 = and(e[6].base.vd.pred, io.op.bits.base.vp.pred) @[sequencer-master.scala 140:37] + node _T_155 = or(_T_153, _T_154) @[sequencer-master.scala 139:75] + node _T_156 = and(_T_146, _T_155) @[sequencer-master.scala 138:76] + node _T_157 = eq(e[6].base.vd.id, io.op.bits.base.vp.id) @[sequencer-master.scala 141:29] + node _T_158 = and(_T_156, _T_157) @[sequencer-master.scala 140:72] + node _T_159 = and(v[7], e[7].base.vd.valid) @[sequencer-master.scala 136:44] + node _T_160 = and(_T_159, io.op.bits.base.vp.valid) @[sequencer-master.scala 137:32] + node _T_161 = eq(e[7].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_162 = and(_T_161, e[7].base.vd.scalar) @[types-vxu.scala 119:37] + node _T_163 = eq(_T_162, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_164 = and(_T_160, _T_163) @[sequencer-master.scala 137:62] + node _T_165 = eq(io.op.bits.base.vp.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_166 = and(_T_165, io.op.bits.base.vp.scalar) @[types-vxu.scala 119:37] + node _T_167 = eq(_T_166, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_168 = and(_T_164, _T_167) @[sequencer-master.scala 138:39] + node _T_169 = eq(e[7].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_170 = eq(e[7].base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_171 = and(_T_169, _T_170) @[types-vxu.scala 120:37] + node _T_172 = eq(io.op.bits.base.vp.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_173 = eq(io.op.bits.base.vp.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_174 = and(_T_172, _T_173) @[types-vxu.scala 120:37] + node _T_175 = and(_T_171, _T_174) @[sequencer-master.scala 139:39] + node _T_176 = and(e[7].base.vd.pred, io.op.bits.base.vp.pred) @[sequencer-master.scala 140:37] + node _T_177 = or(_T_175, _T_176) @[sequencer-master.scala 139:75] + node _T_178 = and(_T_168, _T_177) @[sequencer-master.scala 138:76] + node _T_179 = eq(e[7].base.vd.id, io.op.bits.base.vp.id) @[sequencer-master.scala 141:29] + node _T_180 = and(_T_178, _T_179) @[sequencer-master.scala 140:72] + wire _T_181 : UInt<1>[8] @[sequencer-master.scala 136:12] + _T_181 is invalid @[sequencer-master.scala 136:12] + _T_181[0] <= _T_26 @[sequencer-master.scala 136:12] + _T_181[1] <= _T_48 @[sequencer-master.scala 136:12] + _T_181[2] <= _T_70 @[sequencer-master.scala 136:12] + _T_181[3] <= _T_92 @[sequencer-master.scala 136:12] + _T_181[4] <= _T_114 @[sequencer-master.scala 136:12] + _T_181[5] <= _T_136 @[sequencer-master.scala 136:12] + _T_181[6] <= _T_158 @[sequencer-master.scala 136:12] + _T_181[7] <= _T_180 @[sequencer-master.scala 136:12] + node _T_182 = and(v[0], e[0].base.vd.valid) @[sequencer-master.scala 136:44] + node _T_183 = and(_T_182, io.op.bits.base.vs1.valid) @[sequencer-master.scala 137:32] + node _T_184 = eq(e[0].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_185 = and(_T_184, e[0].base.vd.scalar) @[types-vxu.scala 119:37] + node _T_186 = eq(_T_185, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_187 = and(_T_183, _T_186) @[sequencer-master.scala 137:62] + node _T_188 = eq(io.op.bits.base.vs1.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_189 = and(_T_188, io.op.bits.base.vs1.scalar) @[types-vxu.scala 119:37] + node _T_190 = eq(_T_189, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_191 = and(_T_187, _T_190) @[sequencer-master.scala 138:39] + node _T_192 = eq(e[0].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_193 = eq(e[0].base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_194 = and(_T_192, _T_193) @[types-vxu.scala 120:37] + node _T_195 = eq(io.op.bits.base.vs1.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_196 = eq(io.op.bits.base.vs1.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_197 = and(_T_195, _T_196) @[types-vxu.scala 120:37] + node _T_198 = and(_T_194, _T_197) @[sequencer-master.scala 139:39] + node _T_199 = and(e[0].base.vd.pred, io.op.bits.base.vs1.pred) @[sequencer-master.scala 140:37] + node _T_200 = or(_T_198, _T_199) @[sequencer-master.scala 139:75] + node _T_201 = and(_T_191, _T_200) @[sequencer-master.scala 138:76] + node _T_202 = eq(e[0].base.vd.id, io.op.bits.base.vs1.id) @[sequencer-master.scala 141:29] + node _T_203 = and(_T_201, _T_202) @[sequencer-master.scala 140:72] + node _T_204 = and(v[1], e[1].base.vd.valid) @[sequencer-master.scala 136:44] + node _T_205 = and(_T_204, io.op.bits.base.vs1.valid) @[sequencer-master.scala 137:32] + node _T_206 = eq(e[1].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_207 = and(_T_206, e[1].base.vd.scalar) @[types-vxu.scala 119:37] + node _T_208 = eq(_T_207, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_209 = and(_T_205, _T_208) @[sequencer-master.scala 137:62] + node _T_210 = eq(io.op.bits.base.vs1.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_211 = and(_T_210, io.op.bits.base.vs1.scalar) @[types-vxu.scala 119:37] + node _T_212 = eq(_T_211, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_213 = and(_T_209, _T_212) @[sequencer-master.scala 138:39] + node _T_214 = eq(e[1].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_215 = eq(e[1].base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_216 = and(_T_214, _T_215) @[types-vxu.scala 120:37] + node _T_217 = eq(io.op.bits.base.vs1.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_218 = eq(io.op.bits.base.vs1.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_219 = and(_T_217, _T_218) @[types-vxu.scala 120:37] + node _T_220 = and(_T_216, _T_219) @[sequencer-master.scala 139:39] + node _T_221 = and(e[1].base.vd.pred, io.op.bits.base.vs1.pred) @[sequencer-master.scala 140:37] + node _T_222 = or(_T_220, _T_221) @[sequencer-master.scala 139:75] + node _T_223 = and(_T_213, _T_222) @[sequencer-master.scala 138:76] + node _T_224 = eq(e[1].base.vd.id, io.op.bits.base.vs1.id) @[sequencer-master.scala 141:29] + node _T_225 = and(_T_223, _T_224) @[sequencer-master.scala 140:72] + node _T_226 = and(v[2], e[2].base.vd.valid) @[sequencer-master.scala 136:44] + node _T_227 = and(_T_226, io.op.bits.base.vs1.valid) @[sequencer-master.scala 137:32] + node _T_228 = eq(e[2].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_229 = and(_T_228, e[2].base.vd.scalar) @[types-vxu.scala 119:37] + node _T_230 = eq(_T_229, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_231 = and(_T_227, _T_230) @[sequencer-master.scala 137:62] + node _T_232 = eq(io.op.bits.base.vs1.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_233 = and(_T_232, io.op.bits.base.vs1.scalar) @[types-vxu.scala 119:37] + node _T_234 = eq(_T_233, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_235 = and(_T_231, _T_234) @[sequencer-master.scala 138:39] + node _T_236 = eq(e[2].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_237 = eq(e[2].base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_238 = and(_T_236, _T_237) @[types-vxu.scala 120:37] + node _T_239 = eq(io.op.bits.base.vs1.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_240 = eq(io.op.bits.base.vs1.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_241 = and(_T_239, _T_240) @[types-vxu.scala 120:37] + node _T_242 = and(_T_238, _T_241) @[sequencer-master.scala 139:39] + node _T_243 = and(e[2].base.vd.pred, io.op.bits.base.vs1.pred) @[sequencer-master.scala 140:37] + node _T_244 = or(_T_242, _T_243) @[sequencer-master.scala 139:75] + node _T_245 = and(_T_235, _T_244) @[sequencer-master.scala 138:76] + node _T_246 = eq(e[2].base.vd.id, io.op.bits.base.vs1.id) @[sequencer-master.scala 141:29] + node _T_247 = and(_T_245, _T_246) @[sequencer-master.scala 140:72] + node _T_248 = and(v[3], e[3].base.vd.valid) @[sequencer-master.scala 136:44] + node _T_249 = and(_T_248, io.op.bits.base.vs1.valid) @[sequencer-master.scala 137:32] + node _T_250 = eq(e[3].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_251 = and(_T_250, e[3].base.vd.scalar) @[types-vxu.scala 119:37] + node _T_252 = eq(_T_251, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_253 = and(_T_249, _T_252) @[sequencer-master.scala 137:62] + node _T_254 = eq(io.op.bits.base.vs1.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_255 = and(_T_254, io.op.bits.base.vs1.scalar) @[types-vxu.scala 119:37] + node _T_256 = eq(_T_255, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_257 = and(_T_253, _T_256) @[sequencer-master.scala 138:39] + node _T_258 = eq(e[3].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_259 = eq(e[3].base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_260 = and(_T_258, _T_259) @[types-vxu.scala 120:37] + node _T_261 = eq(io.op.bits.base.vs1.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_262 = eq(io.op.bits.base.vs1.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_263 = and(_T_261, _T_262) @[types-vxu.scala 120:37] + node _T_264 = and(_T_260, _T_263) @[sequencer-master.scala 139:39] + node _T_265 = and(e[3].base.vd.pred, io.op.bits.base.vs1.pred) @[sequencer-master.scala 140:37] + node _T_266 = or(_T_264, _T_265) @[sequencer-master.scala 139:75] + node _T_267 = and(_T_257, _T_266) @[sequencer-master.scala 138:76] + node _T_268 = eq(e[3].base.vd.id, io.op.bits.base.vs1.id) @[sequencer-master.scala 141:29] + node _T_269 = and(_T_267, _T_268) @[sequencer-master.scala 140:72] + node _T_270 = and(v[4], e[4].base.vd.valid) @[sequencer-master.scala 136:44] + node _T_271 = and(_T_270, io.op.bits.base.vs1.valid) @[sequencer-master.scala 137:32] + node _T_272 = eq(e[4].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_273 = and(_T_272, e[4].base.vd.scalar) @[types-vxu.scala 119:37] + node _T_274 = eq(_T_273, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_275 = and(_T_271, _T_274) @[sequencer-master.scala 137:62] + node _T_276 = eq(io.op.bits.base.vs1.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_277 = and(_T_276, io.op.bits.base.vs1.scalar) @[types-vxu.scala 119:37] + node _T_278 = eq(_T_277, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_279 = and(_T_275, _T_278) @[sequencer-master.scala 138:39] + node _T_280 = eq(e[4].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_281 = eq(e[4].base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_282 = and(_T_280, _T_281) @[types-vxu.scala 120:37] + node _T_283 = eq(io.op.bits.base.vs1.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_284 = eq(io.op.bits.base.vs1.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_285 = and(_T_283, _T_284) @[types-vxu.scala 120:37] + node _T_286 = and(_T_282, _T_285) @[sequencer-master.scala 139:39] + node _T_287 = and(e[4].base.vd.pred, io.op.bits.base.vs1.pred) @[sequencer-master.scala 140:37] + node _T_288 = or(_T_286, _T_287) @[sequencer-master.scala 139:75] + node _T_289 = and(_T_279, _T_288) @[sequencer-master.scala 138:76] + node _T_290 = eq(e[4].base.vd.id, io.op.bits.base.vs1.id) @[sequencer-master.scala 141:29] + node _T_291 = and(_T_289, _T_290) @[sequencer-master.scala 140:72] + node _T_292 = and(v[5], e[5].base.vd.valid) @[sequencer-master.scala 136:44] + node _T_293 = and(_T_292, io.op.bits.base.vs1.valid) @[sequencer-master.scala 137:32] + node _T_294 = eq(e[5].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_295 = and(_T_294, e[5].base.vd.scalar) @[types-vxu.scala 119:37] + node _T_296 = eq(_T_295, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_297 = and(_T_293, _T_296) @[sequencer-master.scala 137:62] + node _T_298 = eq(io.op.bits.base.vs1.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_299 = and(_T_298, io.op.bits.base.vs1.scalar) @[types-vxu.scala 119:37] + node _T_300 = eq(_T_299, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_301 = and(_T_297, _T_300) @[sequencer-master.scala 138:39] + node _T_302 = eq(e[5].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_303 = eq(e[5].base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_304 = and(_T_302, _T_303) @[types-vxu.scala 120:37] + node _T_305 = eq(io.op.bits.base.vs1.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_306 = eq(io.op.bits.base.vs1.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_307 = and(_T_305, _T_306) @[types-vxu.scala 120:37] + node _T_308 = and(_T_304, _T_307) @[sequencer-master.scala 139:39] + node _T_309 = and(e[5].base.vd.pred, io.op.bits.base.vs1.pred) @[sequencer-master.scala 140:37] + node _T_310 = or(_T_308, _T_309) @[sequencer-master.scala 139:75] + node _T_311 = and(_T_301, _T_310) @[sequencer-master.scala 138:76] + node _T_312 = eq(e[5].base.vd.id, io.op.bits.base.vs1.id) @[sequencer-master.scala 141:29] + node _T_313 = and(_T_311, _T_312) @[sequencer-master.scala 140:72] + node _T_314 = and(v[6], e[6].base.vd.valid) @[sequencer-master.scala 136:44] + node _T_315 = and(_T_314, io.op.bits.base.vs1.valid) @[sequencer-master.scala 137:32] + node _T_316 = eq(e[6].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_317 = and(_T_316, e[6].base.vd.scalar) @[types-vxu.scala 119:37] + node _T_318 = eq(_T_317, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_319 = and(_T_315, _T_318) @[sequencer-master.scala 137:62] + node _T_320 = eq(io.op.bits.base.vs1.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_321 = and(_T_320, io.op.bits.base.vs1.scalar) @[types-vxu.scala 119:37] + node _T_322 = eq(_T_321, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_323 = and(_T_319, _T_322) @[sequencer-master.scala 138:39] + node _T_324 = eq(e[6].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_325 = eq(e[6].base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_326 = and(_T_324, _T_325) @[types-vxu.scala 120:37] + node _T_327 = eq(io.op.bits.base.vs1.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_328 = eq(io.op.bits.base.vs1.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_329 = and(_T_327, _T_328) @[types-vxu.scala 120:37] + node _T_330 = and(_T_326, _T_329) @[sequencer-master.scala 139:39] + node _T_331 = and(e[6].base.vd.pred, io.op.bits.base.vs1.pred) @[sequencer-master.scala 140:37] + node _T_332 = or(_T_330, _T_331) @[sequencer-master.scala 139:75] + node _T_333 = and(_T_323, _T_332) @[sequencer-master.scala 138:76] + node _T_334 = eq(e[6].base.vd.id, io.op.bits.base.vs1.id) @[sequencer-master.scala 141:29] + node _T_335 = and(_T_333, _T_334) @[sequencer-master.scala 140:72] + node _T_336 = and(v[7], e[7].base.vd.valid) @[sequencer-master.scala 136:44] + node _T_337 = and(_T_336, io.op.bits.base.vs1.valid) @[sequencer-master.scala 137:32] + node _T_338 = eq(e[7].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_339 = and(_T_338, e[7].base.vd.scalar) @[types-vxu.scala 119:37] + node _T_340 = eq(_T_339, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_341 = and(_T_337, _T_340) @[sequencer-master.scala 137:62] + node _T_342 = eq(io.op.bits.base.vs1.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_343 = and(_T_342, io.op.bits.base.vs1.scalar) @[types-vxu.scala 119:37] + node _T_344 = eq(_T_343, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_345 = and(_T_341, _T_344) @[sequencer-master.scala 138:39] + node _T_346 = eq(e[7].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_347 = eq(e[7].base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_348 = and(_T_346, _T_347) @[types-vxu.scala 120:37] + node _T_349 = eq(io.op.bits.base.vs1.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_350 = eq(io.op.bits.base.vs1.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_351 = and(_T_349, _T_350) @[types-vxu.scala 120:37] + node _T_352 = and(_T_348, _T_351) @[sequencer-master.scala 139:39] + node _T_353 = and(e[7].base.vd.pred, io.op.bits.base.vs1.pred) @[sequencer-master.scala 140:37] + node _T_354 = or(_T_352, _T_353) @[sequencer-master.scala 139:75] + node _T_355 = and(_T_345, _T_354) @[sequencer-master.scala 138:76] + node _T_356 = eq(e[7].base.vd.id, io.op.bits.base.vs1.id) @[sequencer-master.scala 141:29] + node _T_357 = and(_T_355, _T_356) @[sequencer-master.scala 140:72] + wire _T_358 : UInt<1>[8] @[sequencer-master.scala 136:12] + _T_358 is invalid @[sequencer-master.scala 136:12] + _T_358[0] <= _T_203 @[sequencer-master.scala 136:12] + _T_358[1] <= _T_225 @[sequencer-master.scala 136:12] + _T_358[2] <= _T_247 @[sequencer-master.scala 136:12] + _T_358[3] <= _T_269 @[sequencer-master.scala 136:12] + _T_358[4] <= _T_291 @[sequencer-master.scala 136:12] + _T_358[5] <= _T_313 @[sequencer-master.scala 136:12] + _T_358[6] <= _T_335 @[sequencer-master.scala 136:12] + _T_358[7] <= _T_357 @[sequencer-master.scala 136:12] + node _T_359 = and(v[0], e[0].base.vd.valid) @[sequencer-master.scala 136:44] + node _T_360 = and(_T_359, io.op.bits.base.vs2.valid) @[sequencer-master.scala 137:32] + node _T_361 = eq(e[0].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_362 = and(_T_361, e[0].base.vd.scalar) @[types-vxu.scala 119:37] + node _T_363 = eq(_T_362, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_364 = and(_T_360, _T_363) @[sequencer-master.scala 137:62] + node _T_365 = eq(io.op.bits.base.vs2.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_366 = and(_T_365, io.op.bits.base.vs2.scalar) @[types-vxu.scala 119:37] + node _T_367 = eq(_T_366, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_368 = and(_T_364, _T_367) @[sequencer-master.scala 138:39] + node _T_369 = eq(e[0].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_370 = eq(e[0].base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_371 = and(_T_369, _T_370) @[types-vxu.scala 120:37] + node _T_372 = eq(io.op.bits.base.vs2.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_373 = eq(io.op.bits.base.vs2.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_374 = and(_T_372, _T_373) @[types-vxu.scala 120:37] + node _T_375 = and(_T_371, _T_374) @[sequencer-master.scala 139:39] + node _T_376 = and(e[0].base.vd.pred, io.op.bits.base.vs2.pred) @[sequencer-master.scala 140:37] + node _T_377 = or(_T_375, _T_376) @[sequencer-master.scala 139:75] + node _T_378 = and(_T_368, _T_377) @[sequencer-master.scala 138:76] + node _T_379 = eq(e[0].base.vd.id, io.op.bits.base.vs2.id) @[sequencer-master.scala 141:29] + node _T_380 = and(_T_378, _T_379) @[sequencer-master.scala 140:72] + node _T_381 = and(v[1], e[1].base.vd.valid) @[sequencer-master.scala 136:44] + node _T_382 = and(_T_381, io.op.bits.base.vs2.valid) @[sequencer-master.scala 137:32] + node _T_383 = eq(e[1].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_384 = and(_T_383, e[1].base.vd.scalar) @[types-vxu.scala 119:37] + node _T_385 = eq(_T_384, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_386 = and(_T_382, _T_385) @[sequencer-master.scala 137:62] + node _T_387 = eq(io.op.bits.base.vs2.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_388 = and(_T_387, io.op.bits.base.vs2.scalar) @[types-vxu.scala 119:37] + node _T_389 = eq(_T_388, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_390 = and(_T_386, _T_389) @[sequencer-master.scala 138:39] + node _T_391 = eq(e[1].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_392 = eq(e[1].base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_393 = and(_T_391, _T_392) @[types-vxu.scala 120:37] + node _T_394 = eq(io.op.bits.base.vs2.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_395 = eq(io.op.bits.base.vs2.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_396 = and(_T_394, _T_395) @[types-vxu.scala 120:37] + node _T_397 = and(_T_393, _T_396) @[sequencer-master.scala 139:39] + node _T_398 = and(e[1].base.vd.pred, io.op.bits.base.vs2.pred) @[sequencer-master.scala 140:37] + node _T_399 = or(_T_397, _T_398) @[sequencer-master.scala 139:75] + node _T_400 = and(_T_390, _T_399) @[sequencer-master.scala 138:76] + node _T_401 = eq(e[1].base.vd.id, io.op.bits.base.vs2.id) @[sequencer-master.scala 141:29] + node _T_402 = and(_T_400, _T_401) @[sequencer-master.scala 140:72] + node _T_403 = and(v[2], e[2].base.vd.valid) @[sequencer-master.scala 136:44] + node _T_404 = and(_T_403, io.op.bits.base.vs2.valid) @[sequencer-master.scala 137:32] + node _T_405 = eq(e[2].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_406 = and(_T_405, e[2].base.vd.scalar) @[types-vxu.scala 119:37] + node _T_407 = eq(_T_406, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_408 = and(_T_404, _T_407) @[sequencer-master.scala 137:62] + node _T_409 = eq(io.op.bits.base.vs2.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_410 = and(_T_409, io.op.bits.base.vs2.scalar) @[types-vxu.scala 119:37] + node _T_411 = eq(_T_410, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_412 = and(_T_408, _T_411) @[sequencer-master.scala 138:39] + node _T_413 = eq(e[2].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_414 = eq(e[2].base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_415 = and(_T_413, _T_414) @[types-vxu.scala 120:37] + node _T_416 = eq(io.op.bits.base.vs2.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_417 = eq(io.op.bits.base.vs2.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_418 = and(_T_416, _T_417) @[types-vxu.scala 120:37] + node _T_419 = and(_T_415, _T_418) @[sequencer-master.scala 139:39] + node _T_420 = and(e[2].base.vd.pred, io.op.bits.base.vs2.pred) @[sequencer-master.scala 140:37] + node _T_421 = or(_T_419, _T_420) @[sequencer-master.scala 139:75] + node _T_422 = and(_T_412, _T_421) @[sequencer-master.scala 138:76] + node _T_423 = eq(e[2].base.vd.id, io.op.bits.base.vs2.id) @[sequencer-master.scala 141:29] + node _T_424 = and(_T_422, _T_423) @[sequencer-master.scala 140:72] + node _T_425 = and(v[3], e[3].base.vd.valid) @[sequencer-master.scala 136:44] + node _T_426 = and(_T_425, io.op.bits.base.vs2.valid) @[sequencer-master.scala 137:32] + node _T_427 = eq(e[3].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_428 = and(_T_427, e[3].base.vd.scalar) @[types-vxu.scala 119:37] + node _T_429 = eq(_T_428, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_430 = and(_T_426, _T_429) @[sequencer-master.scala 137:62] + node _T_431 = eq(io.op.bits.base.vs2.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_432 = and(_T_431, io.op.bits.base.vs2.scalar) @[types-vxu.scala 119:37] + node _T_433 = eq(_T_432, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_434 = and(_T_430, _T_433) @[sequencer-master.scala 138:39] + node _T_435 = eq(e[3].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_436 = eq(e[3].base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_437 = and(_T_435, _T_436) @[types-vxu.scala 120:37] + node _T_438 = eq(io.op.bits.base.vs2.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_439 = eq(io.op.bits.base.vs2.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_440 = and(_T_438, _T_439) @[types-vxu.scala 120:37] + node _T_441 = and(_T_437, _T_440) @[sequencer-master.scala 139:39] + node _T_442 = and(e[3].base.vd.pred, io.op.bits.base.vs2.pred) @[sequencer-master.scala 140:37] + node _T_443 = or(_T_441, _T_442) @[sequencer-master.scala 139:75] + node _T_444 = and(_T_434, _T_443) @[sequencer-master.scala 138:76] + node _T_445 = eq(e[3].base.vd.id, io.op.bits.base.vs2.id) @[sequencer-master.scala 141:29] + node _T_446 = and(_T_444, _T_445) @[sequencer-master.scala 140:72] + node _T_447 = and(v[4], e[4].base.vd.valid) @[sequencer-master.scala 136:44] + node _T_448 = and(_T_447, io.op.bits.base.vs2.valid) @[sequencer-master.scala 137:32] + node _T_449 = eq(e[4].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_450 = and(_T_449, e[4].base.vd.scalar) @[types-vxu.scala 119:37] + node _T_451 = eq(_T_450, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_452 = and(_T_448, _T_451) @[sequencer-master.scala 137:62] + node _T_453 = eq(io.op.bits.base.vs2.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_454 = and(_T_453, io.op.bits.base.vs2.scalar) @[types-vxu.scala 119:37] + node _T_455 = eq(_T_454, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_456 = and(_T_452, _T_455) @[sequencer-master.scala 138:39] + node _T_457 = eq(e[4].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_458 = eq(e[4].base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_459 = and(_T_457, _T_458) @[types-vxu.scala 120:37] + node _T_460 = eq(io.op.bits.base.vs2.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_461 = eq(io.op.bits.base.vs2.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_462 = and(_T_460, _T_461) @[types-vxu.scala 120:37] + node _T_463 = and(_T_459, _T_462) @[sequencer-master.scala 139:39] + node _T_464 = and(e[4].base.vd.pred, io.op.bits.base.vs2.pred) @[sequencer-master.scala 140:37] + node _T_465 = or(_T_463, _T_464) @[sequencer-master.scala 139:75] + node _T_466 = and(_T_456, _T_465) @[sequencer-master.scala 138:76] + node _T_467 = eq(e[4].base.vd.id, io.op.bits.base.vs2.id) @[sequencer-master.scala 141:29] + node _T_468 = and(_T_466, _T_467) @[sequencer-master.scala 140:72] + node _T_469 = and(v[5], e[5].base.vd.valid) @[sequencer-master.scala 136:44] + node _T_470 = and(_T_469, io.op.bits.base.vs2.valid) @[sequencer-master.scala 137:32] + node _T_471 = eq(e[5].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_472 = and(_T_471, e[5].base.vd.scalar) @[types-vxu.scala 119:37] + node _T_473 = eq(_T_472, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_474 = and(_T_470, _T_473) @[sequencer-master.scala 137:62] + node _T_475 = eq(io.op.bits.base.vs2.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_476 = and(_T_475, io.op.bits.base.vs2.scalar) @[types-vxu.scala 119:37] + node _T_477 = eq(_T_476, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_478 = and(_T_474, _T_477) @[sequencer-master.scala 138:39] + node _T_479 = eq(e[5].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_480 = eq(e[5].base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_481 = and(_T_479, _T_480) @[types-vxu.scala 120:37] + node _T_482 = eq(io.op.bits.base.vs2.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_483 = eq(io.op.bits.base.vs2.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_484 = and(_T_482, _T_483) @[types-vxu.scala 120:37] + node _T_485 = and(_T_481, _T_484) @[sequencer-master.scala 139:39] + node _T_486 = and(e[5].base.vd.pred, io.op.bits.base.vs2.pred) @[sequencer-master.scala 140:37] + node _T_487 = or(_T_485, _T_486) @[sequencer-master.scala 139:75] + node _T_488 = and(_T_478, _T_487) @[sequencer-master.scala 138:76] + node _T_489 = eq(e[5].base.vd.id, io.op.bits.base.vs2.id) @[sequencer-master.scala 141:29] + node _T_490 = and(_T_488, _T_489) @[sequencer-master.scala 140:72] + node _T_491 = and(v[6], e[6].base.vd.valid) @[sequencer-master.scala 136:44] + node _T_492 = and(_T_491, io.op.bits.base.vs2.valid) @[sequencer-master.scala 137:32] + node _T_493 = eq(e[6].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_494 = and(_T_493, e[6].base.vd.scalar) @[types-vxu.scala 119:37] + node _T_495 = eq(_T_494, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_496 = and(_T_492, _T_495) @[sequencer-master.scala 137:62] + node _T_497 = eq(io.op.bits.base.vs2.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_498 = and(_T_497, io.op.bits.base.vs2.scalar) @[types-vxu.scala 119:37] + node _T_499 = eq(_T_498, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_500 = and(_T_496, _T_499) @[sequencer-master.scala 138:39] + node _T_501 = eq(e[6].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_502 = eq(e[6].base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_503 = and(_T_501, _T_502) @[types-vxu.scala 120:37] + node _T_504 = eq(io.op.bits.base.vs2.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_505 = eq(io.op.bits.base.vs2.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_506 = and(_T_504, _T_505) @[types-vxu.scala 120:37] + node _T_507 = and(_T_503, _T_506) @[sequencer-master.scala 139:39] + node _T_508 = and(e[6].base.vd.pred, io.op.bits.base.vs2.pred) @[sequencer-master.scala 140:37] + node _T_509 = or(_T_507, _T_508) @[sequencer-master.scala 139:75] + node _T_510 = and(_T_500, _T_509) @[sequencer-master.scala 138:76] + node _T_511 = eq(e[6].base.vd.id, io.op.bits.base.vs2.id) @[sequencer-master.scala 141:29] + node _T_512 = and(_T_510, _T_511) @[sequencer-master.scala 140:72] + node _T_513 = and(v[7], e[7].base.vd.valid) @[sequencer-master.scala 136:44] + node _T_514 = and(_T_513, io.op.bits.base.vs2.valid) @[sequencer-master.scala 137:32] + node _T_515 = eq(e[7].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_516 = and(_T_515, e[7].base.vd.scalar) @[types-vxu.scala 119:37] + node _T_517 = eq(_T_516, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_518 = and(_T_514, _T_517) @[sequencer-master.scala 137:62] + node _T_519 = eq(io.op.bits.base.vs2.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_520 = and(_T_519, io.op.bits.base.vs2.scalar) @[types-vxu.scala 119:37] + node _T_521 = eq(_T_520, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_522 = and(_T_518, _T_521) @[sequencer-master.scala 138:39] + node _T_523 = eq(e[7].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_524 = eq(e[7].base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_525 = and(_T_523, _T_524) @[types-vxu.scala 120:37] + node _T_526 = eq(io.op.bits.base.vs2.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_527 = eq(io.op.bits.base.vs2.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_528 = and(_T_526, _T_527) @[types-vxu.scala 120:37] + node _T_529 = and(_T_525, _T_528) @[sequencer-master.scala 139:39] + node _T_530 = and(e[7].base.vd.pred, io.op.bits.base.vs2.pred) @[sequencer-master.scala 140:37] + node _T_531 = or(_T_529, _T_530) @[sequencer-master.scala 139:75] + node _T_532 = and(_T_522, _T_531) @[sequencer-master.scala 138:76] + node _T_533 = eq(e[7].base.vd.id, io.op.bits.base.vs2.id) @[sequencer-master.scala 141:29] + node _T_534 = and(_T_532, _T_533) @[sequencer-master.scala 140:72] + wire _T_535 : UInt<1>[8] @[sequencer-master.scala 136:12] + _T_535 is invalid @[sequencer-master.scala 136:12] + _T_535[0] <= _T_380 @[sequencer-master.scala 136:12] + _T_535[1] <= _T_402 @[sequencer-master.scala 136:12] + _T_535[2] <= _T_424 @[sequencer-master.scala 136:12] + _T_535[3] <= _T_446 @[sequencer-master.scala 136:12] + _T_535[4] <= _T_468 @[sequencer-master.scala 136:12] + _T_535[5] <= _T_490 @[sequencer-master.scala 136:12] + _T_535[6] <= _T_512 @[sequencer-master.scala 136:12] + _T_535[7] <= _T_534 @[sequencer-master.scala 136:12] + node _T_536 = and(v[0], e[0].base.vd.valid) @[sequencer-master.scala 136:44] + node _T_537 = and(_T_536, io.op.bits.base.vs3.valid) @[sequencer-master.scala 137:32] + node _T_538 = eq(e[0].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_539 = and(_T_538, e[0].base.vd.scalar) @[types-vxu.scala 119:37] + node _T_540 = eq(_T_539, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_541 = and(_T_537, _T_540) @[sequencer-master.scala 137:62] + node _T_542 = eq(io.op.bits.base.vs3.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_543 = and(_T_542, io.op.bits.base.vs3.scalar) @[types-vxu.scala 119:37] + node _T_544 = eq(_T_543, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_545 = and(_T_541, _T_544) @[sequencer-master.scala 138:39] + node _T_546 = eq(e[0].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_547 = eq(e[0].base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_548 = and(_T_546, _T_547) @[types-vxu.scala 120:37] + node _T_549 = eq(io.op.bits.base.vs3.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_550 = eq(io.op.bits.base.vs3.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_551 = and(_T_549, _T_550) @[types-vxu.scala 120:37] + node _T_552 = and(_T_548, _T_551) @[sequencer-master.scala 139:39] + node _T_553 = and(e[0].base.vd.pred, io.op.bits.base.vs3.pred) @[sequencer-master.scala 140:37] + node _T_554 = or(_T_552, _T_553) @[sequencer-master.scala 139:75] + node _T_555 = and(_T_545, _T_554) @[sequencer-master.scala 138:76] + node _T_556 = eq(e[0].base.vd.id, io.op.bits.base.vs3.id) @[sequencer-master.scala 141:29] + node _T_557 = and(_T_555, _T_556) @[sequencer-master.scala 140:72] + node _T_558 = and(v[1], e[1].base.vd.valid) @[sequencer-master.scala 136:44] + node _T_559 = and(_T_558, io.op.bits.base.vs3.valid) @[sequencer-master.scala 137:32] + node _T_560 = eq(e[1].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_561 = and(_T_560, e[1].base.vd.scalar) @[types-vxu.scala 119:37] + node _T_562 = eq(_T_561, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_563 = and(_T_559, _T_562) @[sequencer-master.scala 137:62] + node _T_564 = eq(io.op.bits.base.vs3.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_565 = and(_T_564, io.op.bits.base.vs3.scalar) @[types-vxu.scala 119:37] + node _T_566 = eq(_T_565, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_567 = and(_T_563, _T_566) @[sequencer-master.scala 138:39] + node _T_568 = eq(e[1].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_569 = eq(e[1].base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_570 = and(_T_568, _T_569) @[types-vxu.scala 120:37] + node _T_571 = eq(io.op.bits.base.vs3.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_572 = eq(io.op.bits.base.vs3.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_573 = and(_T_571, _T_572) @[types-vxu.scala 120:37] + node _T_574 = and(_T_570, _T_573) @[sequencer-master.scala 139:39] + node _T_575 = and(e[1].base.vd.pred, io.op.bits.base.vs3.pred) @[sequencer-master.scala 140:37] + node _T_576 = or(_T_574, _T_575) @[sequencer-master.scala 139:75] + node _T_577 = and(_T_567, _T_576) @[sequencer-master.scala 138:76] + node _T_578 = eq(e[1].base.vd.id, io.op.bits.base.vs3.id) @[sequencer-master.scala 141:29] + node _T_579 = and(_T_577, _T_578) @[sequencer-master.scala 140:72] + node _T_580 = and(v[2], e[2].base.vd.valid) @[sequencer-master.scala 136:44] + node _T_581 = and(_T_580, io.op.bits.base.vs3.valid) @[sequencer-master.scala 137:32] + node _T_582 = eq(e[2].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_583 = and(_T_582, e[2].base.vd.scalar) @[types-vxu.scala 119:37] + node _T_584 = eq(_T_583, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_585 = and(_T_581, _T_584) @[sequencer-master.scala 137:62] + node _T_586 = eq(io.op.bits.base.vs3.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_587 = and(_T_586, io.op.bits.base.vs3.scalar) @[types-vxu.scala 119:37] + node _T_588 = eq(_T_587, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_589 = and(_T_585, _T_588) @[sequencer-master.scala 138:39] + node _T_590 = eq(e[2].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_591 = eq(e[2].base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_592 = and(_T_590, _T_591) @[types-vxu.scala 120:37] + node _T_593 = eq(io.op.bits.base.vs3.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_594 = eq(io.op.bits.base.vs3.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_595 = and(_T_593, _T_594) @[types-vxu.scala 120:37] + node _T_596 = and(_T_592, _T_595) @[sequencer-master.scala 139:39] + node _T_597 = and(e[2].base.vd.pred, io.op.bits.base.vs3.pred) @[sequencer-master.scala 140:37] + node _T_598 = or(_T_596, _T_597) @[sequencer-master.scala 139:75] + node _T_599 = and(_T_589, _T_598) @[sequencer-master.scala 138:76] + node _T_600 = eq(e[2].base.vd.id, io.op.bits.base.vs3.id) @[sequencer-master.scala 141:29] + node _T_601 = and(_T_599, _T_600) @[sequencer-master.scala 140:72] + node _T_602 = and(v[3], e[3].base.vd.valid) @[sequencer-master.scala 136:44] + node _T_603 = and(_T_602, io.op.bits.base.vs3.valid) @[sequencer-master.scala 137:32] + node _T_604 = eq(e[3].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_605 = and(_T_604, e[3].base.vd.scalar) @[types-vxu.scala 119:37] + node _T_606 = eq(_T_605, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_607 = and(_T_603, _T_606) @[sequencer-master.scala 137:62] + node _T_608 = eq(io.op.bits.base.vs3.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_609 = and(_T_608, io.op.bits.base.vs3.scalar) @[types-vxu.scala 119:37] + node _T_610 = eq(_T_609, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_611 = and(_T_607, _T_610) @[sequencer-master.scala 138:39] + node _T_612 = eq(e[3].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_613 = eq(e[3].base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_614 = and(_T_612, _T_613) @[types-vxu.scala 120:37] + node _T_615 = eq(io.op.bits.base.vs3.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_616 = eq(io.op.bits.base.vs3.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_617 = and(_T_615, _T_616) @[types-vxu.scala 120:37] + node _T_618 = and(_T_614, _T_617) @[sequencer-master.scala 139:39] + node _T_619 = and(e[3].base.vd.pred, io.op.bits.base.vs3.pred) @[sequencer-master.scala 140:37] + node _T_620 = or(_T_618, _T_619) @[sequencer-master.scala 139:75] + node _T_621 = and(_T_611, _T_620) @[sequencer-master.scala 138:76] + node _T_622 = eq(e[3].base.vd.id, io.op.bits.base.vs3.id) @[sequencer-master.scala 141:29] + node _T_623 = and(_T_621, _T_622) @[sequencer-master.scala 140:72] + node _T_624 = and(v[4], e[4].base.vd.valid) @[sequencer-master.scala 136:44] + node _T_625 = and(_T_624, io.op.bits.base.vs3.valid) @[sequencer-master.scala 137:32] + node _T_626 = eq(e[4].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_627 = and(_T_626, e[4].base.vd.scalar) @[types-vxu.scala 119:37] + node _T_628 = eq(_T_627, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_629 = and(_T_625, _T_628) @[sequencer-master.scala 137:62] + node _T_630 = eq(io.op.bits.base.vs3.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_631 = and(_T_630, io.op.bits.base.vs3.scalar) @[types-vxu.scala 119:37] + node _T_632 = eq(_T_631, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_633 = and(_T_629, _T_632) @[sequencer-master.scala 138:39] + node _T_634 = eq(e[4].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_635 = eq(e[4].base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_636 = and(_T_634, _T_635) @[types-vxu.scala 120:37] + node _T_637 = eq(io.op.bits.base.vs3.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_638 = eq(io.op.bits.base.vs3.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_639 = and(_T_637, _T_638) @[types-vxu.scala 120:37] + node _T_640 = and(_T_636, _T_639) @[sequencer-master.scala 139:39] + node _T_641 = and(e[4].base.vd.pred, io.op.bits.base.vs3.pred) @[sequencer-master.scala 140:37] + node _T_642 = or(_T_640, _T_641) @[sequencer-master.scala 139:75] + node _T_643 = and(_T_633, _T_642) @[sequencer-master.scala 138:76] + node _T_644 = eq(e[4].base.vd.id, io.op.bits.base.vs3.id) @[sequencer-master.scala 141:29] + node _T_645 = and(_T_643, _T_644) @[sequencer-master.scala 140:72] + node _T_646 = and(v[5], e[5].base.vd.valid) @[sequencer-master.scala 136:44] + node _T_647 = and(_T_646, io.op.bits.base.vs3.valid) @[sequencer-master.scala 137:32] + node _T_648 = eq(e[5].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_649 = and(_T_648, e[5].base.vd.scalar) @[types-vxu.scala 119:37] + node _T_650 = eq(_T_649, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_651 = and(_T_647, _T_650) @[sequencer-master.scala 137:62] + node _T_652 = eq(io.op.bits.base.vs3.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_653 = and(_T_652, io.op.bits.base.vs3.scalar) @[types-vxu.scala 119:37] + node _T_654 = eq(_T_653, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_655 = and(_T_651, _T_654) @[sequencer-master.scala 138:39] + node _T_656 = eq(e[5].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_657 = eq(e[5].base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_658 = and(_T_656, _T_657) @[types-vxu.scala 120:37] + node _T_659 = eq(io.op.bits.base.vs3.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_660 = eq(io.op.bits.base.vs3.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_661 = and(_T_659, _T_660) @[types-vxu.scala 120:37] + node _T_662 = and(_T_658, _T_661) @[sequencer-master.scala 139:39] + node _T_663 = and(e[5].base.vd.pred, io.op.bits.base.vs3.pred) @[sequencer-master.scala 140:37] + node _T_664 = or(_T_662, _T_663) @[sequencer-master.scala 139:75] + node _T_665 = and(_T_655, _T_664) @[sequencer-master.scala 138:76] + node _T_666 = eq(e[5].base.vd.id, io.op.bits.base.vs3.id) @[sequencer-master.scala 141:29] + node _T_667 = and(_T_665, _T_666) @[sequencer-master.scala 140:72] + node _T_668 = and(v[6], e[6].base.vd.valid) @[sequencer-master.scala 136:44] + node _T_669 = and(_T_668, io.op.bits.base.vs3.valid) @[sequencer-master.scala 137:32] + node _T_670 = eq(e[6].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_671 = and(_T_670, e[6].base.vd.scalar) @[types-vxu.scala 119:37] + node _T_672 = eq(_T_671, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_673 = and(_T_669, _T_672) @[sequencer-master.scala 137:62] + node _T_674 = eq(io.op.bits.base.vs3.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_675 = and(_T_674, io.op.bits.base.vs3.scalar) @[types-vxu.scala 119:37] + node _T_676 = eq(_T_675, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_677 = and(_T_673, _T_676) @[sequencer-master.scala 138:39] + node _T_678 = eq(e[6].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_679 = eq(e[6].base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_680 = and(_T_678, _T_679) @[types-vxu.scala 120:37] + node _T_681 = eq(io.op.bits.base.vs3.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_682 = eq(io.op.bits.base.vs3.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_683 = and(_T_681, _T_682) @[types-vxu.scala 120:37] + node _T_684 = and(_T_680, _T_683) @[sequencer-master.scala 139:39] + node _T_685 = and(e[6].base.vd.pred, io.op.bits.base.vs3.pred) @[sequencer-master.scala 140:37] + node _T_686 = or(_T_684, _T_685) @[sequencer-master.scala 139:75] + node _T_687 = and(_T_677, _T_686) @[sequencer-master.scala 138:76] + node _T_688 = eq(e[6].base.vd.id, io.op.bits.base.vs3.id) @[sequencer-master.scala 141:29] + node _T_689 = and(_T_687, _T_688) @[sequencer-master.scala 140:72] + node _T_690 = and(v[7], e[7].base.vd.valid) @[sequencer-master.scala 136:44] + node _T_691 = and(_T_690, io.op.bits.base.vs3.valid) @[sequencer-master.scala 137:32] + node _T_692 = eq(e[7].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_693 = and(_T_692, e[7].base.vd.scalar) @[types-vxu.scala 119:37] + node _T_694 = eq(_T_693, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_695 = and(_T_691, _T_694) @[sequencer-master.scala 137:62] + node _T_696 = eq(io.op.bits.base.vs3.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_697 = and(_T_696, io.op.bits.base.vs3.scalar) @[types-vxu.scala 119:37] + node _T_698 = eq(_T_697, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_699 = and(_T_695, _T_698) @[sequencer-master.scala 138:39] + node _T_700 = eq(e[7].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_701 = eq(e[7].base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_702 = and(_T_700, _T_701) @[types-vxu.scala 120:37] + node _T_703 = eq(io.op.bits.base.vs3.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_704 = eq(io.op.bits.base.vs3.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_705 = and(_T_703, _T_704) @[types-vxu.scala 120:37] + node _T_706 = and(_T_702, _T_705) @[sequencer-master.scala 139:39] + node _T_707 = and(e[7].base.vd.pred, io.op.bits.base.vs3.pred) @[sequencer-master.scala 140:37] + node _T_708 = or(_T_706, _T_707) @[sequencer-master.scala 139:75] + node _T_709 = and(_T_699, _T_708) @[sequencer-master.scala 138:76] + node _T_710 = eq(e[7].base.vd.id, io.op.bits.base.vs3.id) @[sequencer-master.scala 141:29] + node _T_711 = and(_T_709, _T_710) @[sequencer-master.scala 140:72] + wire _T_712 : UInt<1>[8] @[sequencer-master.scala 136:12] + _T_712 is invalid @[sequencer-master.scala 136:12] + _T_712[0] <= _T_557 @[sequencer-master.scala 136:12] + _T_712[1] <= _T_579 @[sequencer-master.scala 136:12] + _T_712[2] <= _T_601 @[sequencer-master.scala 136:12] + _T_712[3] <= _T_623 @[sequencer-master.scala 136:12] + _T_712[4] <= _T_645 @[sequencer-master.scala 136:12] + _T_712[5] <= _T_667 @[sequencer-master.scala 136:12] + _T_712[6] <= _T_689 @[sequencer-master.scala 136:12] + _T_712[7] <= _T_711 @[sequencer-master.scala 136:12] + node _T_713 = and(v[0], e[0].base.vp.valid) @[sequencer-master.scala 136:44] + node _T_714 = and(_T_713, io.op.bits.base.vd.valid) @[sequencer-master.scala 137:32] + node _T_715 = eq(e[0].base.vp.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_716 = and(_T_715, e[0].base.vp.scalar) @[types-vxu.scala 119:37] + node _T_717 = eq(_T_716, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_718 = and(_T_714, _T_717) @[sequencer-master.scala 137:62] + node _T_719 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_720 = and(_T_719, io.op.bits.base.vd.scalar) @[types-vxu.scala 119:37] + node _T_721 = eq(_T_720, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_722 = and(_T_718, _T_721) @[sequencer-master.scala 138:39] + node _T_723 = eq(e[0].base.vp.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_724 = eq(e[0].base.vp.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_725 = and(_T_723, _T_724) @[types-vxu.scala 120:37] + node _T_726 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_727 = eq(io.op.bits.base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_728 = and(_T_726, _T_727) @[types-vxu.scala 120:37] + node _T_729 = and(_T_725, _T_728) @[sequencer-master.scala 139:39] + node _T_730 = and(e[0].base.vp.pred, io.op.bits.base.vd.pred) @[sequencer-master.scala 140:37] + node _T_731 = or(_T_729, _T_730) @[sequencer-master.scala 139:75] + node _T_732 = and(_T_722, _T_731) @[sequencer-master.scala 138:76] + node _T_733 = eq(e[0].base.vp.id, io.op.bits.base.vd.id) @[sequencer-master.scala 141:29] + node _T_734 = and(_T_732, _T_733) @[sequencer-master.scala 140:72] + node _T_735 = and(v[1], e[1].base.vp.valid) @[sequencer-master.scala 136:44] + node _T_736 = and(_T_735, io.op.bits.base.vd.valid) @[sequencer-master.scala 137:32] + node _T_737 = eq(e[1].base.vp.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_738 = and(_T_737, e[1].base.vp.scalar) @[types-vxu.scala 119:37] + node _T_739 = eq(_T_738, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_740 = and(_T_736, _T_739) @[sequencer-master.scala 137:62] + node _T_741 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_742 = and(_T_741, io.op.bits.base.vd.scalar) @[types-vxu.scala 119:37] + node _T_743 = eq(_T_742, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_744 = and(_T_740, _T_743) @[sequencer-master.scala 138:39] + node _T_745 = eq(e[1].base.vp.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_746 = eq(e[1].base.vp.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_747 = and(_T_745, _T_746) @[types-vxu.scala 120:37] + node _T_748 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_749 = eq(io.op.bits.base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_750 = and(_T_748, _T_749) @[types-vxu.scala 120:37] + node _T_751 = and(_T_747, _T_750) @[sequencer-master.scala 139:39] + node _T_752 = and(e[1].base.vp.pred, io.op.bits.base.vd.pred) @[sequencer-master.scala 140:37] + node _T_753 = or(_T_751, _T_752) @[sequencer-master.scala 139:75] + node _T_754 = and(_T_744, _T_753) @[sequencer-master.scala 138:76] + node _T_755 = eq(e[1].base.vp.id, io.op.bits.base.vd.id) @[sequencer-master.scala 141:29] + node _T_756 = and(_T_754, _T_755) @[sequencer-master.scala 140:72] + node _T_757 = and(v[2], e[2].base.vp.valid) @[sequencer-master.scala 136:44] + node _T_758 = and(_T_757, io.op.bits.base.vd.valid) @[sequencer-master.scala 137:32] + node _T_759 = eq(e[2].base.vp.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_760 = and(_T_759, e[2].base.vp.scalar) @[types-vxu.scala 119:37] + node _T_761 = eq(_T_760, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_762 = and(_T_758, _T_761) @[sequencer-master.scala 137:62] + node _T_763 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_764 = and(_T_763, io.op.bits.base.vd.scalar) @[types-vxu.scala 119:37] + node _T_765 = eq(_T_764, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_766 = and(_T_762, _T_765) @[sequencer-master.scala 138:39] + node _T_767 = eq(e[2].base.vp.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_768 = eq(e[2].base.vp.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_769 = and(_T_767, _T_768) @[types-vxu.scala 120:37] + node _T_770 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_771 = eq(io.op.bits.base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_772 = and(_T_770, _T_771) @[types-vxu.scala 120:37] + node _T_773 = and(_T_769, _T_772) @[sequencer-master.scala 139:39] + node _T_774 = and(e[2].base.vp.pred, io.op.bits.base.vd.pred) @[sequencer-master.scala 140:37] + node _T_775 = or(_T_773, _T_774) @[sequencer-master.scala 139:75] + node _T_776 = and(_T_766, _T_775) @[sequencer-master.scala 138:76] + node _T_777 = eq(e[2].base.vp.id, io.op.bits.base.vd.id) @[sequencer-master.scala 141:29] + node _T_778 = and(_T_776, _T_777) @[sequencer-master.scala 140:72] + node _T_779 = and(v[3], e[3].base.vp.valid) @[sequencer-master.scala 136:44] + node _T_780 = and(_T_779, io.op.bits.base.vd.valid) @[sequencer-master.scala 137:32] + node _T_781 = eq(e[3].base.vp.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_782 = and(_T_781, e[3].base.vp.scalar) @[types-vxu.scala 119:37] + node _T_783 = eq(_T_782, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_784 = and(_T_780, _T_783) @[sequencer-master.scala 137:62] + node _T_785 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_786 = and(_T_785, io.op.bits.base.vd.scalar) @[types-vxu.scala 119:37] + node _T_787 = eq(_T_786, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_788 = and(_T_784, _T_787) @[sequencer-master.scala 138:39] + node _T_789 = eq(e[3].base.vp.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_790 = eq(e[3].base.vp.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_791 = and(_T_789, _T_790) @[types-vxu.scala 120:37] + node _T_792 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_793 = eq(io.op.bits.base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_794 = and(_T_792, _T_793) @[types-vxu.scala 120:37] + node _T_795 = and(_T_791, _T_794) @[sequencer-master.scala 139:39] + node _T_796 = and(e[3].base.vp.pred, io.op.bits.base.vd.pred) @[sequencer-master.scala 140:37] + node _T_797 = or(_T_795, _T_796) @[sequencer-master.scala 139:75] + node _T_798 = and(_T_788, _T_797) @[sequencer-master.scala 138:76] + node _T_799 = eq(e[3].base.vp.id, io.op.bits.base.vd.id) @[sequencer-master.scala 141:29] + node _T_800 = and(_T_798, _T_799) @[sequencer-master.scala 140:72] + node _T_801 = and(v[4], e[4].base.vp.valid) @[sequencer-master.scala 136:44] + node _T_802 = and(_T_801, io.op.bits.base.vd.valid) @[sequencer-master.scala 137:32] + node _T_803 = eq(e[4].base.vp.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_804 = and(_T_803, e[4].base.vp.scalar) @[types-vxu.scala 119:37] + node _T_805 = eq(_T_804, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_806 = and(_T_802, _T_805) @[sequencer-master.scala 137:62] + node _T_807 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_808 = and(_T_807, io.op.bits.base.vd.scalar) @[types-vxu.scala 119:37] + node _T_809 = eq(_T_808, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_810 = and(_T_806, _T_809) @[sequencer-master.scala 138:39] + node _T_811 = eq(e[4].base.vp.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_812 = eq(e[4].base.vp.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_813 = and(_T_811, _T_812) @[types-vxu.scala 120:37] + node _T_814 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_815 = eq(io.op.bits.base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_816 = and(_T_814, _T_815) @[types-vxu.scala 120:37] + node _T_817 = and(_T_813, _T_816) @[sequencer-master.scala 139:39] + node _T_818 = and(e[4].base.vp.pred, io.op.bits.base.vd.pred) @[sequencer-master.scala 140:37] + node _T_819 = or(_T_817, _T_818) @[sequencer-master.scala 139:75] + node _T_820 = and(_T_810, _T_819) @[sequencer-master.scala 138:76] + node _T_821 = eq(e[4].base.vp.id, io.op.bits.base.vd.id) @[sequencer-master.scala 141:29] + node _T_822 = and(_T_820, _T_821) @[sequencer-master.scala 140:72] + node _T_823 = and(v[5], e[5].base.vp.valid) @[sequencer-master.scala 136:44] + node _T_824 = and(_T_823, io.op.bits.base.vd.valid) @[sequencer-master.scala 137:32] + node _T_825 = eq(e[5].base.vp.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_826 = and(_T_825, e[5].base.vp.scalar) @[types-vxu.scala 119:37] + node _T_827 = eq(_T_826, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_828 = and(_T_824, _T_827) @[sequencer-master.scala 137:62] + node _T_829 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_830 = and(_T_829, io.op.bits.base.vd.scalar) @[types-vxu.scala 119:37] + node _T_831 = eq(_T_830, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_832 = and(_T_828, _T_831) @[sequencer-master.scala 138:39] + node _T_833 = eq(e[5].base.vp.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_834 = eq(e[5].base.vp.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_835 = and(_T_833, _T_834) @[types-vxu.scala 120:37] + node _T_836 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_837 = eq(io.op.bits.base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_838 = and(_T_836, _T_837) @[types-vxu.scala 120:37] + node _T_839 = and(_T_835, _T_838) @[sequencer-master.scala 139:39] + node _T_840 = and(e[5].base.vp.pred, io.op.bits.base.vd.pred) @[sequencer-master.scala 140:37] + node _T_841 = or(_T_839, _T_840) @[sequencer-master.scala 139:75] + node _T_842 = and(_T_832, _T_841) @[sequencer-master.scala 138:76] + node _T_843 = eq(e[5].base.vp.id, io.op.bits.base.vd.id) @[sequencer-master.scala 141:29] + node _T_844 = and(_T_842, _T_843) @[sequencer-master.scala 140:72] + node _T_845 = and(v[6], e[6].base.vp.valid) @[sequencer-master.scala 136:44] + node _T_846 = and(_T_845, io.op.bits.base.vd.valid) @[sequencer-master.scala 137:32] + node _T_847 = eq(e[6].base.vp.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_848 = and(_T_847, e[6].base.vp.scalar) @[types-vxu.scala 119:37] + node _T_849 = eq(_T_848, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_850 = and(_T_846, _T_849) @[sequencer-master.scala 137:62] + node _T_851 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_852 = and(_T_851, io.op.bits.base.vd.scalar) @[types-vxu.scala 119:37] + node _T_853 = eq(_T_852, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_854 = and(_T_850, _T_853) @[sequencer-master.scala 138:39] + node _T_855 = eq(e[6].base.vp.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_856 = eq(e[6].base.vp.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_857 = and(_T_855, _T_856) @[types-vxu.scala 120:37] + node _T_858 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_859 = eq(io.op.bits.base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_860 = and(_T_858, _T_859) @[types-vxu.scala 120:37] + node _T_861 = and(_T_857, _T_860) @[sequencer-master.scala 139:39] + node _T_862 = and(e[6].base.vp.pred, io.op.bits.base.vd.pred) @[sequencer-master.scala 140:37] + node _T_863 = or(_T_861, _T_862) @[sequencer-master.scala 139:75] + node _T_864 = and(_T_854, _T_863) @[sequencer-master.scala 138:76] + node _T_865 = eq(e[6].base.vp.id, io.op.bits.base.vd.id) @[sequencer-master.scala 141:29] + node _T_866 = and(_T_864, _T_865) @[sequencer-master.scala 140:72] + node _T_867 = and(v[7], e[7].base.vp.valid) @[sequencer-master.scala 136:44] + node _T_868 = and(_T_867, io.op.bits.base.vd.valid) @[sequencer-master.scala 137:32] + node _T_869 = eq(e[7].base.vp.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_870 = and(_T_869, e[7].base.vp.scalar) @[types-vxu.scala 119:37] + node _T_871 = eq(_T_870, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_872 = and(_T_868, _T_871) @[sequencer-master.scala 137:62] + node _T_873 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_874 = and(_T_873, io.op.bits.base.vd.scalar) @[types-vxu.scala 119:37] + node _T_875 = eq(_T_874, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_876 = and(_T_872, _T_875) @[sequencer-master.scala 138:39] + node _T_877 = eq(e[7].base.vp.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_878 = eq(e[7].base.vp.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_879 = and(_T_877, _T_878) @[types-vxu.scala 120:37] + node _T_880 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_881 = eq(io.op.bits.base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_882 = and(_T_880, _T_881) @[types-vxu.scala 120:37] + node _T_883 = and(_T_879, _T_882) @[sequencer-master.scala 139:39] + node _T_884 = and(e[7].base.vp.pred, io.op.bits.base.vd.pred) @[sequencer-master.scala 140:37] + node _T_885 = or(_T_883, _T_884) @[sequencer-master.scala 139:75] + node _T_886 = and(_T_876, _T_885) @[sequencer-master.scala 138:76] + node _T_887 = eq(e[7].base.vp.id, io.op.bits.base.vd.id) @[sequencer-master.scala 141:29] + node _T_888 = and(_T_886, _T_887) @[sequencer-master.scala 140:72] + wire _T_889 : UInt<1>[8] @[sequencer-master.scala 136:12] + _T_889 is invalid @[sequencer-master.scala 136:12] + _T_889[0] <= _T_734 @[sequencer-master.scala 136:12] + _T_889[1] <= _T_756 @[sequencer-master.scala 136:12] + _T_889[2] <= _T_778 @[sequencer-master.scala 136:12] + _T_889[3] <= _T_800 @[sequencer-master.scala 136:12] + _T_889[4] <= _T_822 @[sequencer-master.scala 136:12] + _T_889[5] <= _T_844 @[sequencer-master.scala 136:12] + _T_889[6] <= _T_866 @[sequencer-master.scala 136:12] + _T_889[7] <= _T_888 @[sequencer-master.scala 136:12] + node _T_890 = and(v[0], e[0].base.vs1.valid) @[sequencer-master.scala 136:44] + node _T_891 = and(_T_890, io.op.bits.base.vd.valid) @[sequencer-master.scala 137:32] + node _T_892 = eq(e[0].base.vs1.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_893 = and(_T_892, e[0].base.vs1.scalar) @[types-vxu.scala 119:37] + node _T_894 = eq(_T_893, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_895 = and(_T_891, _T_894) @[sequencer-master.scala 137:62] + node _T_896 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_897 = and(_T_896, io.op.bits.base.vd.scalar) @[types-vxu.scala 119:37] + node _T_898 = eq(_T_897, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_899 = and(_T_895, _T_898) @[sequencer-master.scala 138:39] + node _T_900 = eq(e[0].base.vs1.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_901 = eq(e[0].base.vs1.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_902 = and(_T_900, _T_901) @[types-vxu.scala 120:37] + node _T_903 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_904 = eq(io.op.bits.base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_905 = and(_T_903, _T_904) @[types-vxu.scala 120:37] + node _T_906 = and(_T_902, _T_905) @[sequencer-master.scala 139:39] + node _T_907 = and(e[0].base.vs1.pred, io.op.bits.base.vd.pred) @[sequencer-master.scala 140:37] + node _T_908 = or(_T_906, _T_907) @[sequencer-master.scala 139:75] + node _T_909 = and(_T_899, _T_908) @[sequencer-master.scala 138:76] + node _T_910 = eq(e[0].base.vs1.id, io.op.bits.base.vd.id) @[sequencer-master.scala 141:29] + node _T_911 = and(_T_909, _T_910) @[sequencer-master.scala 140:72] + node _T_912 = and(v[1], e[1].base.vs1.valid) @[sequencer-master.scala 136:44] + node _T_913 = and(_T_912, io.op.bits.base.vd.valid) @[sequencer-master.scala 137:32] + node _T_914 = eq(e[1].base.vs1.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_915 = and(_T_914, e[1].base.vs1.scalar) @[types-vxu.scala 119:37] + node _T_916 = eq(_T_915, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_917 = and(_T_913, _T_916) @[sequencer-master.scala 137:62] + node _T_918 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_919 = and(_T_918, io.op.bits.base.vd.scalar) @[types-vxu.scala 119:37] + node _T_920 = eq(_T_919, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_921 = and(_T_917, _T_920) @[sequencer-master.scala 138:39] + node _T_922 = eq(e[1].base.vs1.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_923 = eq(e[1].base.vs1.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_924 = and(_T_922, _T_923) @[types-vxu.scala 120:37] + node _T_925 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_926 = eq(io.op.bits.base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_927 = and(_T_925, _T_926) @[types-vxu.scala 120:37] + node _T_928 = and(_T_924, _T_927) @[sequencer-master.scala 139:39] + node _T_929 = and(e[1].base.vs1.pred, io.op.bits.base.vd.pred) @[sequencer-master.scala 140:37] + node _T_930 = or(_T_928, _T_929) @[sequencer-master.scala 139:75] + node _T_931 = and(_T_921, _T_930) @[sequencer-master.scala 138:76] + node _T_932 = eq(e[1].base.vs1.id, io.op.bits.base.vd.id) @[sequencer-master.scala 141:29] + node _T_933 = and(_T_931, _T_932) @[sequencer-master.scala 140:72] + node _T_934 = and(v[2], e[2].base.vs1.valid) @[sequencer-master.scala 136:44] + node _T_935 = and(_T_934, io.op.bits.base.vd.valid) @[sequencer-master.scala 137:32] + node _T_936 = eq(e[2].base.vs1.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_937 = and(_T_936, e[2].base.vs1.scalar) @[types-vxu.scala 119:37] + node _T_938 = eq(_T_937, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_939 = and(_T_935, _T_938) @[sequencer-master.scala 137:62] + node _T_940 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_941 = and(_T_940, io.op.bits.base.vd.scalar) @[types-vxu.scala 119:37] + node _T_942 = eq(_T_941, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_943 = and(_T_939, _T_942) @[sequencer-master.scala 138:39] + node _T_944 = eq(e[2].base.vs1.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_945 = eq(e[2].base.vs1.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_946 = and(_T_944, _T_945) @[types-vxu.scala 120:37] + node _T_947 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_948 = eq(io.op.bits.base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_949 = and(_T_947, _T_948) @[types-vxu.scala 120:37] + node _T_950 = and(_T_946, _T_949) @[sequencer-master.scala 139:39] + node _T_951 = and(e[2].base.vs1.pred, io.op.bits.base.vd.pred) @[sequencer-master.scala 140:37] + node _T_952 = or(_T_950, _T_951) @[sequencer-master.scala 139:75] + node _T_953 = and(_T_943, _T_952) @[sequencer-master.scala 138:76] + node _T_954 = eq(e[2].base.vs1.id, io.op.bits.base.vd.id) @[sequencer-master.scala 141:29] + node _T_955 = and(_T_953, _T_954) @[sequencer-master.scala 140:72] + node _T_956 = and(v[3], e[3].base.vs1.valid) @[sequencer-master.scala 136:44] + node _T_957 = and(_T_956, io.op.bits.base.vd.valid) @[sequencer-master.scala 137:32] + node _T_958 = eq(e[3].base.vs1.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_959 = and(_T_958, e[3].base.vs1.scalar) @[types-vxu.scala 119:37] + node _T_960 = eq(_T_959, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_961 = and(_T_957, _T_960) @[sequencer-master.scala 137:62] + node _T_962 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_963 = and(_T_962, io.op.bits.base.vd.scalar) @[types-vxu.scala 119:37] + node _T_964 = eq(_T_963, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_965 = and(_T_961, _T_964) @[sequencer-master.scala 138:39] + node _T_966 = eq(e[3].base.vs1.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_967 = eq(e[3].base.vs1.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_968 = and(_T_966, _T_967) @[types-vxu.scala 120:37] + node _T_969 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_970 = eq(io.op.bits.base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_971 = and(_T_969, _T_970) @[types-vxu.scala 120:37] + node _T_972 = and(_T_968, _T_971) @[sequencer-master.scala 139:39] + node _T_973 = and(e[3].base.vs1.pred, io.op.bits.base.vd.pred) @[sequencer-master.scala 140:37] + node _T_974 = or(_T_972, _T_973) @[sequencer-master.scala 139:75] + node _T_975 = and(_T_965, _T_974) @[sequencer-master.scala 138:76] + node _T_976 = eq(e[3].base.vs1.id, io.op.bits.base.vd.id) @[sequencer-master.scala 141:29] + node _T_977 = and(_T_975, _T_976) @[sequencer-master.scala 140:72] + node _T_978 = and(v[4], e[4].base.vs1.valid) @[sequencer-master.scala 136:44] + node _T_979 = and(_T_978, io.op.bits.base.vd.valid) @[sequencer-master.scala 137:32] + node _T_980 = eq(e[4].base.vs1.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_981 = and(_T_980, e[4].base.vs1.scalar) @[types-vxu.scala 119:37] + node _T_982 = eq(_T_981, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_983 = and(_T_979, _T_982) @[sequencer-master.scala 137:62] + node _T_984 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_985 = and(_T_984, io.op.bits.base.vd.scalar) @[types-vxu.scala 119:37] + node _T_986 = eq(_T_985, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_987 = and(_T_983, _T_986) @[sequencer-master.scala 138:39] + node _T_988 = eq(e[4].base.vs1.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_989 = eq(e[4].base.vs1.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_990 = and(_T_988, _T_989) @[types-vxu.scala 120:37] + node _T_991 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_992 = eq(io.op.bits.base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_993 = and(_T_991, _T_992) @[types-vxu.scala 120:37] + node _T_994 = and(_T_990, _T_993) @[sequencer-master.scala 139:39] + node _T_995 = and(e[4].base.vs1.pred, io.op.bits.base.vd.pred) @[sequencer-master.scala 140:37] + node _T_996 = or(_T_994, _T_995) @[sequencer-master.scala 139:75] + node _T_997 = and(_T_987, _T_996) @[sequencer-master.scala 138:76] + node _T_998 = eq(e[4].base.vs1.id, io.op.bits.base.vd.id) @[sequencer-master.scala 141:29] + node _T_999 = and(_T_997, _T_998) @[sequencer-master.scala 140:72] + node _T_1000 = and(v[5], e[5].base.vs1.valid) @[sequencer-master.scala 136:44] + node _T_1001 = and(_T_1000, io.op.bits.base.vd.valid) @[sequencer-master.scala 137:32] + node _T_1002 = eq(e[5].base.vs1.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1003 = and(_T_1002, e[5].base.vs1.scalar) @[types-vxu.scala 119:37] + node _T_1004 = eq(_T_1003, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_1005 = and(_T_1001, _T_1004) @[sequencer-master.scala 137:62] + node _T_1006 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1007 = and(_T_1006, io.op.bits.base.vd.scalar) @[types-vxu.scala 119:37] + node _T_1008 = eq(_T_1007, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_1009 = and(_T_1005, _T_1008) @[sequencer-master.scala 138:39] + node _T_1010 = eq(e[5].base.vs1.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1011 = eq(e[5].base.vs1.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1012 = and(_T_1010, _T_1011) @[types-vxu.scala 120:37] + node _T_1013 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1014 = eq(io.op.bits.base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1015 = and(_T_1013, _T_1014) @[types-vxu.scala 120:37] + node _T_1016 = and(_T_1012, _T_1015) @[sequencer-master.scala 139:39] + node _T_1017 = and(e[5].base.vs1.pred, io.op.bits.base.vd.pred) @[sequencer-master.scala 140:37] + node _T_1018 = or(_T_1016, _T_1017) @[sequencer-master.scala 139:75] + node _T_1019 = and(_T_1009, _T_1018) @[sequencer-master.scala 138:76] + node _T_1020 = eq(e[5].base.vs1.id, io.op.bits.base.vd.id) @[sequencer-master.scala 141:29] + node _T_1021 = and(_T_1019, _T_1020) @[sequencer-master.scala 140:72] + node _T_1022 = and(v[6], e[6].base.vs1.valid) @[sequencer-master.scala 136:44] + node _T_1023 = and(_T_1022, io.op.bits.base.vd.valid) @[sequencer-master.scala 137:32] + node _T_1024 = eq(e[6].base.vs1.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1025 = and(_T_1024, e[6].base.vs1.scalar) @[types-vxu.scala 119:37] + node _T_1026 = eq(_T_1025, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_1027 = and(_T_1023, _T_1026) @[sequencer-master.scala 137:62] + node _T_1028 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1029 = and(_T_1028, io.op.bits.base.vd.scalar) @[types-vxu.scala 119:37] + node _T_1030 = eq(_T_1029, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_1031 = and(_T_1027, _T_1030) @[sequencer-master.scala 138:39] + node _T_1032 = eq(e[6].base.vs1.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1033 = eq(e[6].base.vs1.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1034 = and(_T_1032, _T_1033) @[types-vxu.scala 120:37] + node _T_1035 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1036 = eq(io.op.bits.base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1037 = and(_T_1035, _T_1036) @[types-vxu.scala 120:37] + node _T_1038 = and(_T_1034, _T_1037) @[sequencer-master.scala 139:39] + node _T_1039 = and(e[6].base.vs1.pred, io.op.bits.base.vd.pred) @[sequencer-master.scala 140:37] + node _T_1040 = or(_T_1038, _T_1039) @[sequencer-master.scala 139:75] + node _T_1041 = and(_T_1031, _T_1040) @[sequencer-master.scala 138:76] + node _T_1042 = eq(e[6].base.vs1.id, io.op.bits.base.vd.id) @[sequencer-master.scala 141:29] + node _T_1043 = and(_T_1041, _T_1042) @[sequencer-master.scala 140:72] + node _T_1044 = and(v[7], e[7].base.vs1.valid) @[sequencer-master.scala 136:44] + node _T_1045 = and(_T_1044, io.op.bits.base.vd.valid) @[sequencer-master.scala 137:32] + node _T_1046 = eq(e[7].base.vs1.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1047 = and(_T_1046, e[7].base.vs1.scalar) @[types-vxu.scala 119:37] + node _T_1048 = eq(_T_1047, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_1049 = and(_T_1045, _T_1048) @[sequencer-master.scala 137:62] + node _T_1050 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1051 = and(_T_1050, io.op.bits.base.vd.scalar) @[types-vxu.scala 119:37] + node _T_1052 = eq(_T_1051, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_1053 = and(_T_1049, _T_1052) @[sequencer-master.scala 138:39] + node _T_1054 = eq(e[7].base.vs1.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1055 = eq(e[7].base.vs1.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1056 = and(_T_1054, _T_1055) @[types-vxu.scala 120:37] + node _T_1057 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1058 = eq(io.op.bits.base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1059 = and(_T_1057, _T_1058) @[types-vxu.scala 120:37] + node _T_1060 = and(_T_1056, _T_1059) @[sequencer-master.scala 139:39] + node _T_1061 = and(e[7].base.vs1.pred, io.op.bits.base.vd.pred) @[sequencer-master.scala 140:37] + node _T_1062 = or(_T_1060, _T_1061) @[sequencer-master.scala 139:75] + node _T_1063 = and(_T_1053, _T_1062) @[sequencer-master.scala 138:76] + node _T_1064 = eq(e[7].base.vs1.id, io.op.bits.base.vd.id) @[sequencer-master.scala 141:29] + node _T_1065 = and(_T_1063, _T_1064) @[sequencer-master.scala 140:72] + wire _T_1066 : UInt<1>[8] @[sequencer-master.scala 136:12] + _T_1066 is invalid @[sequencer-master.scala 136:12] + _T_1066[0] <= _T_911 @[sequencer-master.scala 136:12] + _T_1066[1] <= _T_933 @[sequencer-master.scala 136:12] + _T_1066[2] <= _T_955 @[sequencer-master.scala 136:12] + _T_1066[3] <= _T_977 @[sequencer-master.scala 136:12] + _T_1066[4] <= _T_999 @[sequencer-master.scala 136:12] + _T_1066[5] <= _T_1021 @[sequencer-master.scala 136:12] + _T_1066[6] <= _T_1043 @[sequencer-master.scala 136:12] + _T_1066[7] <= _T_1065 @[sequencer-master.scala 136:12] + node _T_1067 = and(v[0], e[0].base.vs2.valid) @[sequencer-master.scala 136:44] + node _T_1068 = and(_T_1067, io.op.bits.base.vd.valid) @[sequencer-master.scala 137:32] + node _T_1069 = eq(e[0].base.vs2.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1070 = and(_T_1069, e[0].base.vs2.scalar) @[types-vxu.scala 119:37] + node _T_1071 = eq(_T_1070, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_1072 = and(_T_1068, _T_1071) @[sequencer-master.scala 137:62] + node _T_1073 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1074 = and(_T_1073, io.op.bits.base.vd.scalar) @[types-vxu.scala 119:37] + node _T_1075 = eq(_T_1074, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_1076 = and(_T_1072, _T_1075) @[sequencer-master.scala 138:39] + node _T_1077 = eq(e[0].base.vs2.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1078 = eq(e[0].base.vs2.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1079 = and(_T_1077, _T_1078) @[types-vxu.scala 120:37] + node _T_1080 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1081 = eq(io.op.bits.base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1082 = and(_T_1080, _T_1081) @[types-vxu.scala 120:37] + node _T_1083 = and(_T_1079, _T_1082) @[sequencer-master.scala 139:39] + node _T_1084 = and(e[0].base.vs2.pred, io.op.bits.base.vd.pred) @[sequencer-master.scala 140:37] + node _T_1085 = or(_T_1083, _T_1084) @[sequencer-master.scala 139:75] + node _T_1086 = and(_T_1076, _T_1085) @[sequencer-master.scala 138:76] + node _T_1087 = eq(e[0].base.vs2.id, io.op.bits.base.vd.id) @[sequencer-master.scala 141:29] + node _T_1088 = and(_T_1086, _T_1087) @[sequencer-master.scala 140:72] + node _T_1089 = and(v[1], e[1].base.vs2.valid) @[sequencer-master.scala 136:44] + node _T_1090 = and(_T_1089, io.op.bits.base.vd.valid) @[sequencer-master.scala 137:32] + node _T_1091 = eq(e[1].base.vs2.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1092 = and(_T_1091, e[1].base.vs2.scalar) @[types-vxu.scala 119:37] + node _T_1093 = eq(_T_1092, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_1094 = and(_T_1090, _T_1093) @[sequencer-master.scala 137:62] + node _T_1095 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1096 = and(_T_1095, io.op.bits.base.vd.scalar) @[types-vxu.scala 119:37] + node _T_1097 = eq(_T_1096, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_1098 = and(_T_1094, _T_1097) @[sequencer-master.scala 138:39] + node _T_1099 = eq(e[1].base.vs2.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1100 = eq(e[1].base.vs2.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1101 = and(_T_1099, _T_1100) @[types-vxu.scala 120:37] + node _T_1102 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1103 = eq(io.op.bits.base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1104 = and(_T_1102, _T_1103) @[types-vxu.scala 120:37] + node _T_1105 = and(_T_1101, _T_1104) @[sequencer-master.scala 139:39] + node _T_1106 = and(e[1].base.vs2.pred, io.op.bits.base.vd.pred) @[sequencer-master.scala 140:37] + node _T_1107 = or(_T_1105, _T_1106) @[sequencer-master.scala 139:75] + node _T_1108 = and(_T_1098, _T_1107) @[sequencer-master.scala 138:76] + node _T_1109 = eq(e[1].base.vs2.id, io.op.bits.base.vd.id) @[sequencer-master.scala 141:29] + node _T_1110 = and(_T_1108, _T_1109) @[sequencer-master.scala 140:72] + node _T_1111 = and(v[2], e[2].base.vs2.valid) @[sequencer-master.scala 136:44] + node _T_1112 = and(_T_1111, io.op.bits.base.vd.valid) @[sequencer-master.scala 137:32] + node _T_1113 = eq(e[2].base.vs2.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1114 = and(_T_1113, e[2].base.vs2.scalar) @[types-vxu.scala 119:37] + node _T_1115 = eq(_T_1114, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_1116 = and(_T_1112, _T_1115) @[sequencer-master.scala 137:62] + node _T_1117 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1118 = and(_T_1117, io.op.bits.base.vd.scalar) @[types-vxu.scala 119:37] + node _T_1119 = eq(_T_1118, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_1120 = and(_T_1116, _T_1119) @[sequencer-master.scala 138:39] + node _T_1121 = eq(e[2].base.vs2.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1122 = eq(e[2].base.vs2.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1123 = and(_T_1121, _T_1122) @[types-vxu.scala 120:37] + node _T_1124 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1125 = eq(io.op.bits.base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1126 = and(_T_1124, _T_1125) @[types-vxu.scala 120:37] + node _T_1127 = and(_T_1123, _T_1126) @[sequencer-master.scala 139:39] + node _T_1128 = and(e[2].base.vs2.pred, io.op.bits.base.vd.pred) @[sequencer-master.scala 140:37] + node _T_1129 = or(_T_1127, _T_1128) @[sequencer-master.scala 139:75] + node _T_1130 = and(_T_1120, _T_1129) @[sequencer-master.scala 138:76] + node _T_1131 = eq(e[2].base.vs2.id, io.op.bits.base.vd.id) @[sequencer-master.scala 141:29] + node _T_1132 = and(_T_1130, _T_1131) @[sequencer-master.scala 140:72] + node _T_1133 = and(v[3], e[3].base.vs2.valid) @[sequencer-master.scala 136:44] + node _T_1134 = and(_T_1133, io.op.bits.base.vd.valid) @[sequencer-master.scala 137:32] + node _T_1135 = eq(e[3].base.vs2.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1136 = and(_T_1135, e[3].base.vs2.scalar) @[types-vxu.scala 119:37] + node _T_1137 = eq(_T_1136, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_1138 = and(_T_1134, _T_1137) @[sequencer-master.scala 137:62] + node _T_1139 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1140 = and(_T_1139, io.op.bits.base.vd.scalar) @[types-vxu.scala 119:37] + node _T_1141 = eq(_T_1140, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_1142 = and(_T_1138, _T_1141) @[sequencer-master.scala 138:39] + node _T_1143 = eq(e[3].base.vs2.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1144 = eq(e[3].base.vs2.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1145 = and(_T_1143, _T_1144) @[types-vxu.scala 120:37] + node _T_1146 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1147 = eq(io.op.bits.base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1148 = and(_T_1146, _T_1147) @[types-vxu.scala 120:37] + node _T_1149 = and(_T_1145, _T_1148) @[sequencer-master.scala 139:39] + node _T_1150 = and(e[3].base.vs2.pred, io.op.bits.base.vd.pred) @[sequencer-master.scala 140:37] + node _T_1151 = or(_T_1149, _T_1150) @[sequencer-master.scala 139:75] + node _T_1152 = and(_T_1142, _T_1151) @[sequencer-master.scala 138:76] + node _T_1153 = eq(e[3].base.vs2.id, io.op.bits.base.vd.id) @[sequencer-master.scala 141:29] + node _T_1154 = and(_T_1152, _T_1153) @[sequencer-master.scala 140:72] + node _T_1155 = and(v[4], e[4].base.vs2.valid) @[sequencer-master.scala 136:44] + node _T_1156 = and(_T_1155, io.op.bits.base.vd.valid) @[sequencer-master.scala 137:32] + node _T_1157 = eq(e[4].base.vs2.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1158 = and(_T_1157, e[4].base.vs2.scalar) @[types-vxu.scala 119:37] + node _T_1159 = eq(_T_1158, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_1160 = and(_T_1156, _T_1159) @[sequencer-master.scala 137:62] + node _T_1161 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1162 = and(_T_1161, io.op.bits.base.vd.scalar) @[types-vxu.scala 119:37] + node _T_1163 = eq(_T_1162, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_1164 = and(_T_1160, _T_1163) @[sequencer-master.scala 138:39] + node _T_1165 = eq(e[4].base.vs2.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1166 = eq(e[4].base.vs2.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1167 = and(_T_1165, _T_1166) @[types-vxu.scala 120:37] + node _T_1168 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1169 = eq(io.op.bits.base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1170 = and(_T_1168, _T_1169) @[types-vxu.scala 120:37] + node _T_1171 = and(_T_1167, _T_1170) @[sequencer-master.scala 139:39] + node _T_1172 = and(e[4].base.vs2.pred, io.op.bits.base.vd.pred) @[sequencer-master.scala 140:37] + node _T_1173 = or(_T_1171, _T_1172) @[sequencer-master.scala 139:75] + node _T_1174 = and(_T_1164, _T_1173) @[sequencer-master.scala 138:76] + node _T_1175 = eq(e[4].base.vs2.id, io.op.bits.base.vd.id) @[sequencer-master.scala 141:29] + node _T_1176 = and(_T_1174, _T_1175) @[sequencer-master.scala 140:72] + node _T_1177 = and(v[5], e[5].base.vs2.valid) @[sequencer-master.scala 136:44] + node _T_1178 = and(_T_1177, io.op.bits.base.vd.valid) @[sequencer-master.scala 137:32] + node _T_1179 = eq(e[5].base.vs2.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1180 = and(_T_1179, e[5].base.vs2.scalar) @[types-vxu.scala 119:37] + node _T_1181 = eq(_T_1180, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_1182 = and(_T_1178, _T_1181) @[sequencer-master.scala 137:62] + node _T_1183 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1184 = and(_T_1183, io.op.bits.base.vd.scalar) @[types-vxu.scala 119:37] + node _T_1185 = eq(_T_1184, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_1186 = and(_T_1182, _T_1185) @[sequencer-master.scala 138:39] + node _T_1187 = eq(e[5].base.vs2.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1188 = eq(e[5].base.vs2.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1189 = and(_T_1187, _T_1188) @[types-vxu.scala 120:37] + node _T_1190 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1191 = eq(io.op.bits.base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1192 = and(_T_1190, _T_1191) @[types-vxu.scala 120:37] + node _T_1193 = and(_T_1189, _T_1192) @[sequencer-master.scala 139:39] + node _T_1194 = and(e[5].base.vs2.pred, io.op.bits.base.vd.pred) @[sequencer-master.scala 140:37] + node _T_1195 = or(_T_1193, _T_1194) @[sequencer-master.scala 139:75] + node _T_1196 = and(_T_1186, _T_1195) @[sequencer-master.scala 138:76] + node _T_1197 = eq(e[5].base.vs2.id, io.op.bits.base.vd.id) @[sequencer-master.scala 141:29] + node _T_1198 = and(_T_1196, _T_1197) @[sequencer-master.scala 140:72] + node _T_1199 = and(v[6], e[6].base.vs2.valid) @[sequencer-master.scala 136:44] + node _T_1200 = and(_T_1199, io.op.bits.base.vd.valid) @[sequencer-master.scala 137:32] + node _T_1201 = eq(e[6].base.vs2.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1202 = and(_T_1201, e[6].base.vs2.scalar) @[types-vxu.scala 119:37] + node _T_1203 = eq(_T_1202, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_1204 = and(_T_1200, _T_1203) @[sequencer-master.scala 137:62] + node _T_1205 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1206 = and(_T_1205, io.op.bits.base.vd.scalar) @[types-vxu.scala 119:37] + node _T_1207 = eq(_T_1206, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_1208 = and(_T_1204, _T_1207) @[sequencer-master.scala 138:39] + node _T_1209 = eq(e[6].base.vs2.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1210 = eq(e[6].base.vs2.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1211 = and(_T_1209, _T_1210) @[types-vxu.scala 120:37] + node _T_1212 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1213 = eq(io.op.bits.base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1214 = and(_T_1212, _T_1213) @[types-vxu.scala 120:37] + node _T_1215 = and(_T_1211, _T_1214) @[sequencer-master.scala 139:39] + node _T_1216 = and(e[6].base.vs2.pred, io.op.bits.base.vd.pred) @[sequencer-master.scala 140:37] + node _T_1217 = or(_T_1215, _T_1216) @[sequencer-master.scala 139:75] + node _T_1218 = and(_T_1208, _T_1217) @[sequencer-master.scala 138:76] + node _T_1219 = eq(e[6].base.vs2.id, io.op.bits.base.vd.id) @[sequencer-master.scala 141:29] + node _T_1220 = and(_T_1218, _T_1219) @[sequencer-master.scala 140:72] + node _T_1221 = and(v[7], e[7].base.vs2.valid) @[sequencer-master.scala 136:44] + node _T_1222 = and(_T_1221, io.op.bits.base.vd.valid) @[sequencer-master.scala 137:32] + node _T_1223 = eq(e[7].base.vs2.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1224 = and(_T_1223, e[7].base.vs2.scalar) @[types-vxu.scala 119:37] + node _T_1225 = eq(_T_1224, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_1226 = and(_T_1222, _T_1225) @[sequencer-master.scala 137:62] + node _T_1227 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1228 = and(_T_1227, io.op.bits.base.vd.scalar) @[types-vxu.scala 119:37] + node _T_1229 = eq(_T_1228, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_1230 = and(_T_1226, _T_1229) @[sequencer-master.scala 138:39] + node _T_1231 = eq(e[7].base.vs2.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1232 = eq(e[7].base.vs2.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1233 = and(_T_1231, _T_1232) @[types-vxu.scala 120:37] + node _T_1234 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1235 = eq(io.op.bits.base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1236 = and(_T_1234, _T_1235) @[types-vxu.scala 120:37] + node _T_1237 = and(_T_1233, _T_1236) @[sequencer-master.scala 139:39] + node _T_1238 = and(e[7].base.vs2.pred, io.op.bits.base.vd.pred) @[sequencer-master.scala 140:37] + node _T_1239 = or(_T_1237, _T_1238) @[sequencer-master.scala 139:75] + node _T_1240 = and(_T_1230, _T_1239) @[sequencer-master.scala 138:76] + node _T_1241 = eq(e[7].base.vs2.id, io.op.bits.base.vd.id) @[sequencer-master.scala 141:29] + node _T_1242 = and(_T_1240, _T_1241) @[sequencer-master.scala 140:72] + wire _T_1243 : UInt<1>[8] @[sequencer-master.scala 136:12] + _T_1243 is invalid @[sequencer-master.scala 136:12] + _T_1243[0] <= _T_1088 @[sequencer-master.scala 136:12] + _T_1243[1] <= _T_1110 @[sequencer-master.scala 136:12] + _T_1243[2] <= _T_1132 @[sequencer-master.scala 136:12] + _T_1243[3] <= _T_1154 @[sequencer-master.scala 136:12] + _T_1243[4] <= _T_1176 @[sequencer-master.scala 136:12] + _T_1243[5] <= _T_1198 @[sequencer-master.scala 136:12] + _T_1243[6] <= _T_1220 @[sequencer-master.scala 136:12] + _T_1243[7] <= _T_1242 @[sequencer-master.scala 136:12] + node _T_1244 = and(v[0], e[0].base.vs3.valid) @[sequencer-master.scala 136:44] + node _T_1245 = and(_T_1244, io.op.bits.base.vd.valid) @[sequencer-master.scala 137:32] + node _T_1246 = eq(e[0].base.vs3.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1247 = and(_T_1246, e[0].base.vs3.scalar) @[types-vxu.scala 119:37] + node _T_1248 = eq(_T_1247, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_1249 = and(_T_1245, _T_1248) @[sequencer-master.scala 137:62] + node _T_1250 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1251 = and(_T_1250, io.op.bits.base.vd.scalar) @[types-vxu.scala 119:37] + node _T_1252 = eq(_T_1251, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_1253 = and(_T_1249, _T_1252) @[sequencer-master.scala 138:39] + node _T_1254 = eq(e[0].base.vs3.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1255 = eq(e[0].base.vs3.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1256 = and(_T_1254, _T_1255) @[types-vxu.scala 120:37] + node _T_1257 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1258 = eq(io.op.bits.base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1259 = and(_T_1257, _T_1258) @[types-vxu.scala 120:37] + node _T_1260 = and(_T_1256, _T_1259) @[sequencer-master.scala 139:39] + node _T_1261 = and(e[0].base.vs3.pred, io.op.bits.base.vd.pred) @[sequencer-master.scala 140:37] + node _T_1262 = or(_T_1260, _T_1261) @[sequencer-master.scala 139:75] + node _T_1263 = and(_T_1253, _T_1262) @[sequencer-master.scala 138:76] + node _T_1264 = eq(e[0].base.vs3.id, io.op.bits.base.vd.id) @[sequencer-master.scala 141:29] + node _T_1265 = and(_T_1263, _T_1264) @[sequencer-master.scala 140:72] + node _T_1266 = and(v[1], e[1].base.vs3.valid) @[sequencer-master.scala 136:44] + node _T_1267 = and(_T_1266, io.op.bits.base.vd.valid) @[sequencer-master.scala 137:32] + node _T_1268 = eq(e[1].base.vs3.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1269 = and(_T_1268, e[1].base.vs3.scalar) @[types-vxu.scala 119:37] + node _T_1270 = eq(_T_1269, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_1271 = and(_T_1267, _T_1270) @[sequencer-master.scala 137:62] + node _T_1272 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1273 = and(_T_1272, io.op.bits.base.vd.scalar) @[types-vxu.scala 119:37] + node _T_1274 = eq(_T_1273, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_1275 = and(_T_1271, _T_1274) @[sequencer-master.scala 138:39] + node _T_1276 = eq(e[1].base.vs3.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1277 = eq(e[1].base.vs3.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1278 = and(_T_1276, _T_1277) @[types-vxu.scala 120:37] + node _T_1279 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1280 = eq(io.op.bits.base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1281 = and(_T_1279, _T_1280) @[types-vxu.scala 120:37] + node _T_1282 = and(_T_1278, _T_1281) @[sequencer-master.scala 139:39] + node _T_1283 = and(e[1].base.vs3.pred, io.op.bits.base.vd.pred) @[sequencer-master.scala 140:37] + node _T_1284 = or(_T_1282, _T_1283) @[sequencer-master.scala 139:75] + node _T_1285 = and(_T_1275, _T_1284) @[sequencer-master.scala 138:76] + node _T_1286 = eq(e[1].base.vs3.id, io.op.bits.base.vd.id) @[sequencer-master.scala 141:29] + node _T_1287 = and(_T_1285, _T_1286) @[sequencer-master.scala 140:72] + node _T_1288 = and(v[2], e[2].base.vs3.valid) @[sequencer-master.scala 136:44] + node _T_1289 = and(_T_1288, io.op.bits.base.vd.valid) @[sequencer-master.scala 137:32] + node _T_1290 = eq(e[2].base.vs3.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1291 = and(_T_1290, e[2].base.vs3.scalar) @[types-vxu.scala 119:37] + node _T_1292 = eq(_T_1291, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_1293 = and(_T_1289, _T_1292) @[sequencer-master.scala 137:62] + node _T_1294 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1295 = and(_T_1294, io.op.bits.base.vd.scalar) @[types-vxu.scala 119:37] + node _T_1296 = eq(_T_1295, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_1297 = and(_T_1293, _T_1296) @[sequencer-master.scala 138:39] + node _T_1298 = eq(e[2].base.vs3.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1299 = eq(e[2].base.vs3.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1300 = and(_T_1298, _T_1299) @[types-vxu.scala 120:37] + node _T_1301 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1302 = eq(io.op.bits.base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1303 = and(_T_1301, _T_1302) @[types-vxu.scala 120:37] + node _T_1304 = and(_T_1300, _T_1303) @[sequencer-master.scala 139:39] + node _T_1305 = and(e[2].base.vs3.pred, io.op.bits.base.vd.pred) @[sequencer-master.scala 140:37] + node _T_1306 = or(_T_1304, _T_1305) @[sequencer-master.scala 139:75] + node _T_1307 = and(_T_1297, _T_1306) @[sequencer-master.scala 138:76] + node _T_1308 = eq(e[2].base.vs3.id, io.op.bits.base.vd.id) @[sequencer-master.scala 141:29] + node _T_1309 = and(_T_1307, _T_1308) @[sequencer-master.scala 140:72] + node _T_1310 = and(v[3], e[3].base.vs3.valid) @[sequencer-master.scala 136:44] + node _T_1311 = and(_T_1310, io.op.bits.base.vd.valid) @[sequencer-master.scala 137:32] + node _T_1312 = eq(e[3].base.vs3.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1313 = and(_T_1312, e[3].base.vs3.scalar) @[types-vxu.scala 119:37] + node _T_1314 = eq(_T_1313, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_1315 = and(_T_1311, _T_1314) @[sequencer-master.scala 137:62] + node _T_1316 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1317 = and(_T_1316, io.op.bits.base.vd.scalar) @[types-vxu.scala 119:37] + node _T_1318 = eq(_T_1317, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_1319 = and(_T_1315, _T_1318) @[sequencer-master.scala 138:39] + node _T_1320 = eq(e[3].base.vs3.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1321 = eq(e[3].base.vs3.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1322 = and(_T_1320, _T_1321) @[types-vxu.scala 120:37] + node _T_1323 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1324 = eq(io.op.bits.base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1325 = and(_T_1323, _T_1324) @[types-vxu.scala 120:37] + node _T_1326 = and(_T_1322, _T_1325) @[sequencer-master.scala 139:39] + node _T_1327 = and(e[3].base.vs3.pred, io.op.bits.base.vd.pred) @[sequencer-master.scala 140:37] + node _T_1328 = or(_T_1326, _T_1327) @[sequencer-master.scala 139:75] + node _T_1329 = and(_T_1319, _T_1328) @[sequencer-master.scala 138:76] + node _T_1330 = eq(e[3].base.vs3.id, io.op.bits.base.vd.id) @[sequencer-master.scala 141:29] + node _T_1331 = and(_T_1329, _T_1330) @[sequencer-master.scala 140:72] + node _T_1332 = and(v[4], e[4].base.vs3.valid) @[sequencer-master.scala 136:44] + node _T_1333 = and(_T_1332, io.op.bits.base.vd.valid) @[sequencer-master.scala 137:32] + node _T_1334 = eq(e[4].base.vs3.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1335 = and(_T_1334, e[4].base.vs3.scalar) @[types-vxu.scala 119:37] + node _T_1336 = eq(_T_1335, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_1337 = and(_T_1333, _T_1336) @[sequencer-master.scala 137:62] + node _T_1338 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1339 = and(_T_1338, io.op.bits.base.vd.scalar) @[types-vxu.scala 119:37] + node _T_1340 = eq(_T_1339, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_1341 = and(_T_1337, _T_1340) @[sequencer-master.scala 138:39] + node _T_1342 = eq(e[4].base.vs3.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1343 = eq(e[4].base.vs3.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1344 = and(_T_1342, _T_1343) @[types-vxu.scala 120:37] + node _T_1345 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1346 = eq(io.op.bits.base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1347 = and(_T_1345, _T_1346) @[types-vxu.scala 120:37] + node _T_1348 = and(_T_1344, _T_1347) @[sequencer-master.scala 139:39] + node _T_1349 = and(e[4].base.vs3.pred, io.op.bits.base.vd.pred) @[sequencer-master.scala 140:37] + node _T_1350 = or(_T_1348, _T_1349) @[sequencer-master.scala 139:75] + node _T_1351 = and(_T_1341, _T_1350) @[sequencer-master.scala 138:76] + node _T_1352 = eq(e[4].base.vs3.id, io.op.bits.base.vd.id) @[sequencer-master.scala 141:29] + node _T_1353 = and(_T_1351, _T_1352) @[sequencer-master.scala 140:72] + node _T_1354 = and(v[5], e[5].base.vs3.valid) @[sequencer-master.scala 136:44] + node _T_1355 = and(_T_1354, io.op.bits.base.vd.valid) @[sequencer-master.scala 137:32] + node _T_1356 = eq(e[5].base.vs3.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1357 = and(_T_1356, e[5].base.vs3.scalar) @[types-vxu.scala 119:37] + node _T_1358 = eq(_T_1357, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_1359 = and(_T_1355, _T_1358) @[sequencer-master.scala 137:62] + node _T_1360 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1361 = and(_T_1360, io.op.bits.base.vd.scalar) @[types-vxu.scala 119:37] + node _T_1362 = eq(_T_1361, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_1363 = and(_T_1359, _T_1362) @[sequencer-master.scala 138:39] + node _T_1364 = eq(e[5].base.vs3.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1365 = eq(e[5].base.vs3.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1366 = and(_T_1364, _T_1365) @[types-vxu.scala 120:37] + node _T_1367 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1368 = eq(io.op.bits.base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1369 = and(_T_1367, _T_1368) @[types-vxu.scala 120:37] + node _T_1370 = and(_T_1366, _T_1369) @[sequencer-master.scala 139:39] + node _T_1371 = and(e[5].base.vs3.pred, io.op.bits.base.vd.pred) @[sequencer-master.scala 140:37] + node _T_1372 = or(_T_1370, _T_1371) @[sequencer-master.scala 139:75] + node _T_1373 = and(_T_1363, _T_1372) @[sequencer-master.scala 138:76] + node _T_1374 = eq(e[5].base.vs3.id, io.op.bits.base.vd.id) @[sequencer-master.scala 141:29] + node _T_1375 = and(_T_1373, _T_1374) @[sequencer-master.scala 140:72] + node _T_1376 = and(v[6], e[6].base.vs3.valid) @[sequencer-master.scala 136:44] + node _T_1377 = and(_T_1376, io.op.bits.base.vd.valid) @[sequencer-master.scala 137:32] + node _T_1378 = eq(e[6].base.vs3.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1379 = and(_T_1378, e[6].base.vs3.scalar) @[types-vxu.scala 119:37] + node _T_1380 = eq(_T_1379, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_1381 = and(_T_1377, _T_1380) @[sequencer-master.scala 137:62] + node _T_1382 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1383 = and(_T_1382, io.op.bits.base.vd.scalar) @[types-vxu.scala 119:37] + node _T_1384 = eq(_T_1383, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_1385 = and(_T_1381, _T_1384) @[sequencer-master.scala 138:39] + node _T_1386 = eq(e[6].base.vs3.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1387 = eq(e[6].base.vs3.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1388 = and(_T_1386, _T_1387) @[types-vxu.scala 120:37] + node _T_1389 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1390 = eq(io.op.bits.base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1391 = and(_T_1389, _T_1390) @[types-vxu.scala 120:37] + node _T_1392 = and(_T_1388, _T_1391) @[sequencer-master.scala 139:39] + node _T_1393 = and(e[6].base.vs3.pred, io.op.bits.base.vd.pred) @[sequencer-master.scala 140:37] + node _T_1394 = or(_T_1392, _T_1393) @[sequencer-master.scala 139:75] + node _T_1395 = and(_T_1385, _T_1394) @[sequencer-master.scala 138:76] + node _T_1396 = eq(e[6].base.vs3.id, io.op.bits.base.vd.id) @[sequencer-master.scala 141:29] + node _T_1397 = and(_T_1395, _T_1396) @[sequencer-master.scala 140:72] + node _T_1398 = and(v[7], e[7].base.vs3.valid) @[sequencer-master.scala 136:44] + node _T_1399 = and(_T_1398, io.op.bits.base.vd.valid) @[sequencer-master.scala 137:32] + node _T_1400 = eq(e[7].base.vs3.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1401 = and(_T_1400, e[7].base.vs3.scalar) @[types-vxu.scala 119:37] + node _T_1402 = eq(_T_1401, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_1403 = and(_T_1399, _T_1402) @[sequencer-master.scala 137:62] + node _T_1404 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1405 = and(_T_1404, io.op.bits.base.vd.scalar) @[types-vxu.scala 119:37] + node _T_1406 = eq(_T_1405, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_1407 = and(_T_1403, _T_1406) @[sequencer-master.scala 138:39] + node _T_1408 = eq(e[7].base.vs3.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1409 = eq(e[7].base.vs3.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1410 = and(_T_1408, _T_1409) @[types-vxu.scala 120:37] + node _T_1411 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1412 = eq(io.op.bits.base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1413 = and(_T_1411, _T_1412) @[types-vxu.scala 120:37] + node _T_1414 = and(_T_1410, _T_1413) @[sequencer-master.scala 139:39] + node _T_1415 = and(e[7].base.vs3.pred, io.op.bits.base.vd.pred) @[sequencer-master.scala 140:37] + node _T_1416 = or(_T_1414, _T_1415) @[sequencer-master.scala 139:75] + node _T_1417 = and(_T_1407, _T_1416) @[sequencer-master.scala 138:76] + node _T_1418 = eq(e[7].base.vs3.id, io.op.bits.base.vd.id) @[sequencer-master.scala 141:29] + node _T_1419 = and(_T_1417, _T_1418) @[sequencer-master.scala 140:72] + wire _T_1420 : UInt<1>[8] @[sequencer-master.scala 136:12] + _T_1420 is invalid @[sequencer-master.scala 136:12] + _T_1420[0] <= _T_1265 @[sequencer-master.scala 136:12] + _T_1420[1] <= _T_1287 @[sequencer-master.scala 136:12] + _T_1420[2] <= _T_1309 @[sequencer-master.scala 136:12] + _T_1420[3] <= _T_1331 @[sequencer-master.scala 136:12] + _T_1420[4] <= _T_1353 @[sequencer-master.scala 136:12] + _T_1420[5] <= _T_1375 @[sequencer-master.scala 136:12] + _T_1420[6] <= _T_1397 @[sequencer-master.scala 136:12] + _T_1420[7] <= _T_1419 @[sequencer-master.scala 136:12] + node _T_1421 = and(v[0], e[0].base.vd.valid) @[sequencer-master.scala 136:44] + node _T_1422 = and(_T_1421, io.op.bits.base.vd.valid) @[sequencer-master.scala 137:32] + node _T_1423 = eq(e[0].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1424 = and(_T_1423, e[0].base.vd.scalar) @[types-vxu.scala 119:37] + node _T_1425 = eq(_T_1424, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_1426 = and(_T_1422, _T_1425) @[sequencer-master.scala 137:62] + node _T_1427 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1428 = and(_T_1427, io.op.bits.base.vd.scalar) @[types-vxu.scala 119:37] + node _T_1429 = eq(_T_1428, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_1430 = and(_T_1426, _T_1429) @[sequencer-master.scala 138:39] + node _T_1431 = eq(e[0].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1432 = eq(e[0].base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1433 = and(_T_1431, _T_1432) @[types-vxu.scala 120:37] + node _T_1434 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1435 = eq(io.op.bits.base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1436 = and(_T_1434, _T_1435) @[types-vxu.scala 120:37] + node _T_1437 = and(_T_1433, _T_1436) @[sequencer-master.scala 139:39] + node _T_1438 = and(e[0].base.vd.pred, io.op.bits.base.vd.pred) @[sequencer-master.scala 140:37] + node _T_1439 = or(_T_1437, _T_1438) @[sequencer-master.scala 139:75] + node _T_1440 = and(_T_1430, _T_1439) @[sequencer-master.scala 138:76] + node _T_1441 = eq(e[0].base.vd.id, io.op.bits.base.vd.id) @[sequencer-master.scala 141:29] + node _T_1442 = and(_T_1440, _T_1441) @[sequencer-master.scala 140:72] + node _T_1443 = and(v[1], e[1].base.vd.valid) @[sequencer-master.scala 136:44] + node _T_1444 = and(_T_1443, io.op.bits.base.vd.valid) @[sequencer-master.scala 137:32] + node _T_1445 = eq(e[1].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1446 = and(_T_1445, e[1].base.vd.scalar) @[types-vxu.scala 119:37] + node _T_1447 = eq(_T_1446, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_1448 = and(_T_1444, _T_1447) @[sequencer-master.scala 137:62] + node _T_1449 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1450 = and(_T_1449, io.op.bits.base.vd.scalar) @[types-vxu.scala 119:37] + node _T_1451 = eq(_T_1450, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_1452 = and(_T_1448, _T_1451) @[sequencer-master.scala 138:39] + node _T_1453 = eq(e[1].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1454 = eq(e[1].base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1455 = and(_T_1453, _T_1454) @[types-vxu.scala 120:37] + node _T_1456 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1457 = eq(io.op.bits.base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1458 = and(_T_1456, _T_1457) @[types-vxu.scala 120:37] + node _T_1459 = and(_T_1455, _T_1458) @[sequencer-master.scala 139:39] + node _T_1460 = and(e[1].base.vd.pred, io.op.bits.base.vd.pred) @[sequencer-master.scala 140:37] + node _T_1461 = or(_T_1459, _T_1460) @[sequencer-master.scala 139:75] + node _T_1462 = and(_T_1452, _T_1461) @[sequencer-master.scala 138:76] + node _T_1463 = eq(e[1].base.vd.id, io.op.bits.base.vd.id) @[sequencer-master.scala 141:29] + node _T_1464 = and(_T_1462, _T_1463) @[sequencer-master.scala 140:72] + node _T_1465 = and(v[2], e[2].base.vd.valid) @[sequencer-master.scala 136:44] + node _T_1466 = and(_T_1465, io.op.bits.base.vd.valid) @[sequencer-master.scala 137:32] + node _T_1467 = eq(e[2].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1468 = and(_T_1467, e[2].base.vd.scalar) @[types-vxu.scala 119:37] + node _T_1469 = eq(_T_1468, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_1470 = and(_T_1466, _T_1469) @[sequencer-master.scala 137:62] + node _T_1471 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1472 = and(_T_1471, io.op.bits.base.vd.scalar) @[types-vxu.scala 119:37] + node _T_1473 = eq(_T_1472, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_1474 = and(_T_1470, _T_1473) @[sequencer-master.scala 138:39] + node _T_1475 = eq(e[2].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1476 = eq(e[2].base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1477 = and(_T_1475, _T_1476) @[types-vxu.scala 120:37] + node _T_1478 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1479 = eq(io.op.bits.base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1480 = and(_T_1478, _T_1479) @[types-vxu.scala 120:37] + node _T_1481 = and(_T_1477, _T_1480) @[sequencer-master.scala 139:39] + node _T_1482 = and(e[2].base.vd.pred, io.op.bits.base.vd.pred) @[sequencer-master.scala 140:37] + node _T_1483 = or(_T_1481, _T_1482) @[sequencer-master.scala 139:75] + node _T_1484 = and(_T_1474, _T_1483) @[sequencer-master.scala 138:76] + node _T_1485 = eq(e[2].base.vd.id, io.op.bits.base.vd.id) @[sequencer-master.scala 141:29] + node _T_1486 = and(_T_1484, _T_1485) @[sequencer-master.scala 140:72] + node _T_1487 = and(v[3], e[3].base.vd.valid) @[sequencer-master.scala 136:44] + node _T_1488 = and(_T_1487, io.op.bits.base.vd.valid) @[sequencer-master.scala 137:32] + node _T_1489 = eq(e[3].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1490 = and(_T_1489, e[3].base.vd.scalar) @[types-vxu.scala 119:37] + node _T_1491 = eq(_T_1490, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_1492 = and(_T_1488, _T_1491) @[sequencer-master.scala 137:62] + node _T_1493 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1494 = and(_T_1493, io.op.bits.base.vd.scalar) @[types-vxu.scala 119:37] + node _T_1495 = eq(_T_1494, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_1496 = and(_T_1492, _T_1495) @[sequencer-master.scala 138:39] + node _T_1497 = eq(e[3].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1498 = eq(e[3].base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1499 = and(_T_1497, _T_1498) @[types-vxu.scala 120:37] + node _T_1500 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1501 = eq(io.op.bits.base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1502 = and(_T_1500, _T_1501) @[types-vxu.scala 120:37] + node _T_1503 = and(_T_1499, _T_1502) @[sequencer-master.scala 139:39] + node _T_1504 = and(e[3].base.vd.pred, io.op.bits.base.vd.pred) @[sequencer-master.scala 140:37] + node _T_1505 = or(_T_1503, _T_1504) @[sequencer-master.scala 139:75] + node _T_1506 = and(_T_1496, _T_1505) @[sequencer-master.scala 138:76] + node _T_1507 = eq(e[3].base.vd.id, io.op.bits.base.vd.id) @[sequencer-master.scala 141:29] + node _T_1508 = and(_T_1506, _T_1507) @[sequencer-master.scala 140:72] + node _T_1509 = and(v[4], e[4].base.vd.valid) @[sequencer-master.scala 136:44] + node _T_1510 = and(_T_1509, io.op.bits.base.vd.valid) @[sequencer-master.scala 137:32] + node _T_1511 = eq(e[4].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1512 = and(_T_1511, e[4].base.vd.scalar) @[types-vxu.scala 119:37] + node _T_1513 = eq(_T_1512, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_1514 = and(_T_1510, _T_1513) @[sequencer-master.scala 137:62] + node _T_1515 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1516 = and(_T_1515, io.op.bits.base.vd.scalar) @[types-vxu.scala 119:37] + node _T_1517 = eq(_T_1516, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_1518 = and(_T_1514, _T_1517) @[sequencer-master.scala 138:39] + node _T_1519 = eq(e[4].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1520 = eq(e[4].base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1521 = and(_T_1519, _T_1520) @[types-vxu.scala 120:37] + node _T_1522 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1523 = eq(io.op.bits.base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1524 = and(_T_1522, _T_1523) @[types-vxu.scala 120:37] + node _T_1525 = and(_T_1521, _T_1524) @[sequencer-master.scala 139:39] + node _T_1526 = and(e[4].base.vd.pred, io.op.bits.base.vd.pred) @[sequencer-master.scala 140:37] + node _T_1527 = or(_T_1525, _T_1526) @[sequencer-master.scala 139:75] + node _T_1528 = and(_T_1518, _T_1527) @[sequencer-master.scala 138:76] + node _T_1529 = eq(e[4].base.vd.id, io.op.bits.base.vd.id) @[sequencer-master.scala 141:29] + node _T_1530 = and(_T_1528, _T_1529) @[sequencer-master.scala 140:72] + node _T_1531 = and(v[5], e[5].base.vd.valid) @[sequencer-master.scala 136:44] + node _T_1532 = and(_T_1531, io.op.bits.base.vd.valid) @[sequencer-master.scala 137:32] + node _T_1533 = eq(e[5].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1534 = and(_T_1533, e[5].base.vd.scalar) @[types-vxu.scala 119:37] + node _T_1535 = eq(_T_1534, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_1536 = and(_T_1532, _T_1535) @[sequencer-master.scala 137:62] + node _T_1537 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1538 = and(_T_1537, io.op.bits.base.vd.scalar) @[types-vxu.scala 119:37] + node _T_1539 = eq(_T_1538, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_1540 = and(_T_1536, _T_1539) @[sequencer-master.scala 138:39] + node _T_1541 = eq(e[5].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1542 = eq(e[5].base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1543 = and(_T_1541, _T_1542) @[types-vxu.scala 120:37] + node _T_1544 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1545 = eq(io.op.bits.base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1546 = and(_T_1544, _T_1545) @[types-vxu.scala 120:37] + node _T_1547 = and(_T_1543, _T_1546) @[sequencer-master.scala 139:39] + node _T_1548 = and(e[5].base.vd.pred, io.op.bits.base.vd.pred) @[sequencer-master.scala 140:37] + node _T_1549 = or(_T_1547, _T_1548) @[sequencer-master.scala 139:75] + node _T_1550 = and(_T_1540, _T_1549) @[sequencer-master.scala 138:76] + node _T_1551 = eq(e[5].base.vd.id, io.op.bits.base.vd.id) @[sequencer-master.scala 141:29] + node _T_1552 = and(_T_1550, _T_1551) @[sequencer-master.scala 140:72] + node _T_1553 = and(v[6], e[6].base.vd.valid) @[sequencer-master.scala 136:44] + node _T_1554 = and(_T_1553, io.op.bits.base.vd.valid) @[sequencer-master.scala 137:32] + node _T_1555 = eq(e[6].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1556 = and(_T_1555, e[6].base.vd.scalar) @[types-vxu.scala 119:37] + node _T_1557 = eq(_T_1556, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_1558 = and(_T_1554, _T_1557) @[sequencer-master.scala 137:62] + node _T_1559 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1560 = and(_T_1559, io.op.bits.base.vd.scalar) @[types-vxu.scala 119:37] + node _T_1561 = eq(_T_1560, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_1562 = and(_T_1558, _T_1561) @[sequencer-master.scala 138:39] + node _T_1563 = eq(e[6].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1564 = eq(e[6].base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1565 = and(_T_1563, _T_1564) @[types-vxu.scala 120:37] + node _T_1566 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1567 = eq(io.op.bits.base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1568 = and(_T_1566, _T_1567) @[types-vxu.scala 120:37] + node _T_1569 = and(_T_1565, _T_1568) @[sequencer-master.scala 139:39] + node _T_1570 = and(e[6].base.vd.pred, io.op.bits.base.vd.pred) @[sequencer-master.scala 140:37] + node _T_1571 = or(_T_1569, _T_1570) @[sequencer-master.scala 139:75] + node _T_1572 = and(_T_1562, _T_1571) @[sequencer-master.scala 138:76] + node _T_1573 = eq(e[6].base.vd.id, io.op.bits.base.vd.id) @[sequencer-master.scala 141:29] + node _T_1574 = and(_T_1572, _T_1573) @[sequencer-master.scala 140:72] + node _T_1575 = and(v[7], e[7].base.vd.valid) @[sequencer-master.scala 136:44] + node _T_1576 = and(_T_1575, io.op.bits.base.vd.valid) @[sequencer-master.scala 137:32] + node _T_1577 = eq(e[7].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1578 = and(_T_1577, e[7].base.vd.scalar) @[types-vxu.scala 119:37] + node _T_1579 = eq(_T_1578, UInt<1>("h00")) @[sequencer-master.scala 138:11] + node _T_1580 = and(_T_1576, _T_1579) @[sequencer-master.scala 137:62] + node _T_1581 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1582 = and(_T_1581, io.op.bits.base.vd.scalar) @[types-vxu.scala 119:37] + node _T_1583 = eq(_T_1582, UInt<1>("h00")) @[sequencer-master.scala 138:42] + node _T_1584 = and(_T_1580, _T_1583) @[sequencer-master.scala 138:39] + node _T_1585 = eq(e[7].base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1586 = eq(e[7].base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1587 = and(_T_1585, _T_1586) @[types-vxu.scala 120:37] + node _T_1588 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1589 = eq(io.op.bits.base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1590 = and(_T_1588, _T_1589) @[types-vxu.scala 120:37] + node _T_1591 = and(_T_1587, _T_1590) @[sequencer-master.scala 139:39] + node _T_1592 = and(e[7].base.vd.pred, io.op.bits.base.vd.pred) @[sequencer-master.scala 140:37] + node _T_1593 = or(_T_1591, _T_1592) @[sequencer-master.scala 139:75] + node _T_1594 = and(_T_1584, _T_1593) @[sequencer-master.scala 138:76] + node _T_1595 = eq(e[7].base.vd.id, io.op.bits.base.vd.id) @[sequencer-master.scala 141:29] + node _T_1596 = and(_T_1594, _T_1595) @[sequencer-master.scala 140:72] + wire _T_1597 : UInt<1>[8] @[sequencer-master.scala 136:12] + _T_1597 is invalid @[sequencer-master.scala 136:12] + _T_1597[0] <= _T_1442 @[sequencer-master.scala 136:12] + _T_1597[1] <= _T_1464 @[sequencer-master.scala 136:12] + _T_1597[2] <= _T_1486 @[sequencer-master.scala 136:12] + _T_1597[3] <= _T_1508 @[sequencer-master.scala 136:12] + _T_1597[4] <= _T_1530 @[sequencer-master.scala 136:12] + _T_1597[5] <= _T_1552 @[sequencer-master.scala 136:12] + _T_1597[6] <= _T_1574 @[sequencer-master.scala 136:12] + _T_1597[7] <= _T_1596 @[sequencer-master.scala 136:12] + node _T_1598 = eq(io.op.bits.base.vs1.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1599 = eq(io.op.bits.base.vs1.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1600 = and(_T_1598, _T_1599) @[types-vxu.scala 120:37] + node _T_1601 = and(io.op.bits.base.vs1.valid, _T_1600) @[sequencer-master.scala 218:69] + node _T_1602 = eq(io.op.bits.base.vs2.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1603 = eq(io.op.bits.base.vs2.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1604 = and(_T_1602, _T_1603) @[types-vxu.scala 120:37] + node _T_1605 = and(io.op.bits.base.vs2.valid, _T_1604) @[sequencer-master.scala 218:69] + node _T_1606 = eq(io.op.bits.base.vs3.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1607 = eq(io.op.bits.base.vs3.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1608 = and(_T_1606, _T_1607) @[types-vxu.scala 120:37] + node _T_1609 = and(io.op.bits.base.vs3.valid, _T_1608) @[sequencer-master.scala 218:69] + node _T_1610 = add(_T_1605, _T_1609) @[Bitwise.scala 48:55] + node _T_1611 = add(_T_1601, _T_1610) @[Bitwise.scala 48:55] + node _T_1612 = eq(io.op.bits.active.vipred, UInt<1>("h00")) @[sequencer-master.scala 220:21] + node _T_1613 = mux(_T_1612, UInt<1>("h01"), UInt<1>("h00")) @[sequencer-master.scala 221:22] + node _T_1614 = gt(_T_1611, UInt<1>("h00")) @[sequencer-master.scala 222:17] + node _T_1615 = mux(_T_1614, _T_1611, _T_1613) @[sequencer-master.scala 222:12] + node _T_1616 = eq(io.op.bits.base.vs1.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1617 = eq(io.op.bits.base.vs1.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1618 = and(_T_1616, _T_1617) @[types-vxu.scala 120:37] + node _T_1619 = and(io.op.bits.base.vs1.valid, _T_1618) @[sequencer-master.scala 218:69] + node _T_1620 = eq(io.op.bits.active.vipred, UInt<1>("h00")) @[sequencer-master.scala 220:21] + node _T_1621 = mux(_T_1620, UInt<1>("h01"), UInt<1>("h00")) @[sequencer-master.scala 221:22] + node _T_1622 = gt(_T_1619, UInt<1>("h00")) @[sequencer-master.scala 222:17] + node _T_1623 = mux(_T_1622, _T_1619, _T_1621) @[sequencer-master.scala 222:12] + node _T_1624 = eq(io.op.bits.base.vs2.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1625 = eq(io.op.bits.base.vs2.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1626 = and(_T_1624, _T_1625) @[types-vxu.scala 120:37] + node _T_1627 = and(io.op.bits.base.vs2.valid, _T_1626) @[sequencer-master.scala 218:69] + node _T_1628 = eq(io.op.bits.active.vipred, UInt<1>("h00")) @[sequencer-master.scala 220:21] + node _T_1629 = mux(_T_1628, UInt<1>("h01"), UInt<1>("h00")) @[sequencer-master.scala 221:22] + node _T_1630 = gt(_T_1627, UInt<1>("h00")) @[sequencer-master.scala 222:17] + node _T_1631 = mux(_T_1630, _T_1627, _T_1629) @[sequencer-master.scala 222:12] + node _T_1632 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1633 = eq(io.op.bits.base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1634 = and(_T_1632, _T_1633) @[types-vxu.scala 120:37] + node _T_1635 = and(io.op.bits.base.vd.valid, _T_1634) @[sequencer-master.scala 218:69] + node _T_1636 = eq(io.op.bits.active.vipred, UInt<1>("h00")) @[sequencer-master.scala 220:21] + node _T_1637 = mux(_T_1636, UInt<1>("h01"), UInt<1>("h00")) @[sequencer-master.scala 221:22] + node _T_1638 = gt(_T_1635, UInt<1>("h00")) @[sequencer-master.scala 222:17] + node _T_1639 = mux(_T_1638, _T_1635, _T_1637) @[sequencer-master.scala 222:12] + wire _T_1640 : UInt<1> @[sequencer-master.scala 258:27] + _T_1640 is invalid @[sequencer-master.scala 258:27] + wire _T_1641 : UInt<1> @[sequencer-master.scala 259:27] + _T_1641 is invalid @[sequencer-master.scala 259:27] + wire _T_1642 : UInt<3> @[sequencer-master.scala 260:25] + _T_1642 is invalid @[sequencer-master.scala 260:25] + wire _T_1643 : UInt<3> @[sequencer-master.scala 261:25] + _T_1643 is invalid @[sequencer-master.scala 261:25] + node _T_1644 = add(tail, UInt<1>("h01")) @[util.scala 94:11] + node _T_1645 = tail(_T_1644, 1) @[util.scala 94:11] + node _T_1646 = add(tail, UInt<2>("h02")) @[util.scala 94:11] + node _T_1647 = tail(_T_1646, 1) @[util.scala 94:11] + node _T_1648 = add(tail, UInt<2>("h03")) @[util.scala 94:11] + node _T_1649 = tail(_T_1648, 1) @[util.scala 94:11] + node _T_1650 = add(tail, UInt<3>("h04")) @[util.scala 94:11] + node _T_1651 = tail(_T_1650, 1) @[util.scala 94:11] + node _T_1652 = eq(io.op.bits.base.vs1.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1653 = eq(io.op.bits.base.vs1.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1654 = and(_T_1652, _T_1653) @[types-vxu.scala 120:37] + node _T_1655 = and(io.op.bits.base.vs1.valid, _T_1654) @[sequencer-master.scala 498:33] + node _T_1656 = eq(_T_1655, UInt<1>("h00")) @[sequencer-master.scala 498:20] + node _T_1657 = eq(UInt<2>("h00"), io.op.bits.base.vs1.prec) @[sequencer-master.scala 499:57] + node _T_1658 = or(_T_1656, _T_1657) @[sequencer-master.scala 499:51] + node _T_1659 = eq(UInt<2>("h01"), io.op.bits.base.vs1.prec) @[sequencer-master.scala 499:57] + node _T_1660 = or(_T_1656, _T_1659) @[sequencer-master.scala 499:51] + node _T_1661 = eq(UInt<2>("h02"), io.op.bits.base.vs1.prec) @[sequencer-master.scala 499:57] + node _T_1662 = or(_T_1656, _T_1661) @[sequencer-master.scala 499:51] + node _T_1663 = eq(io.op.bits.base.vs2.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1664 = eq(io.op.bits.base.vs2.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1665 = and(_T_1663, _T_1664) @[types-vxu.scala 120:37] + node _T_1666 = and(io.op.bits.base.vs2.valid, _T_1665) @[sequencer-master.scala 498:33] + node _T_1667 = eq(_T_1666, UInt<1>("h00")) @[sequencer-master.scala 498:20] + node _T_1668 = eq(UInt<2>("h00"), io.op.bits.base.vs2.prec) @[sequencer-master.scala 499:57] + node _T_1669 = or(_T_1667, _T_1668) @[sequencer-master.scala 499:51] + node _T_1670 = eq(UInt<2>("h01"), io.op.bits.base.vs2.prec) @[sequencer-master.scala 499:57] + node _T_1671 = or(_T_1667, _T_1670) @[sequencer-master.scala 499:51] + node _T_1672 = eq(UInt<2>("h02"), io.op.bits.base.vs2.prec) @[sequencer-master.scala 499:57] + node _T_1673 = or(_T_1667, _T_1672) @[sequencer-master.scala 499:51] + node _T_1674 = eq(io.op.bits.base.vs3.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1675 = eq(io.op.bits.base.vs3.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1676 = and(_T_1674, _T_1675) @[types-vxu.scala 120:37] + node _T_1677 = and(io.op.bits.base.vs3.valid, _T_1676) @[sequencer-master.scala 498:33] + node _T_1678 = eq(_T_1677, UInt<1>("h00")) @[sequencer-master.scala 498:20] + node _T_1679 = eq(UInt<2>("h00"), io.op.bits.base.vs3.prec) @[sequencer-master.scala 499:57] + node _T_1680 = or(_T_1678, _T_1679) @[sequencer-master.scala 499:51] + node _T_1681 = eq(UInt<2>("h01"), io.op.bits.base.vs3.prec) @[sequencer-master.scala 499:57] + node _T_1682 = or(_T_1678, _T_1681) @[sequencer-master.scala 499:51] + node _T_1683 = eq(UInt<2>("h02"), io.op.bits.base.vs3.prec) @[sequencer-master.scala 499:57] + node _T_1684 = or(_T_1678, _T_1683) @[sequencer-master.scala 499:51] + node _T_1685 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1686 = eq(io.op.bits.base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1687 = and(_T_1685, _T_1686) @[types-vxu.scala 120:37] + node _T_1688 = and(io.op.bits.base.vd.valid, _T_1687) @[sequencer-master.scala 498:33] + node _T_1689 = eq(_T_1688, UInt<1>("h00")) @[sequencer-master.scala 498:20] + node _T_1690 = eq(UInt<2>("h00"), io.op.bits.base.vd.prec) @[sequencer-master.scala 499:57] + node _T_1691 = or(_T_1689, _T_1690) @[sequencer-master.scala 499:51] + node _T_1692 = eq(UInt<2>("h01"), io.op.bits.base.vd.prec) @[sequencer-master.scala 499:57] + node _T_1693 = or(_T_1689, _T_1692) @[sequencer-master.scala 499:51] + node _T_1694 = eq(UInt<2>("h02"), io.op.bits.base.vd.prec) @[sequencer-master.scala 499:57] + node _T_1695 = or(_T_1689, _T_1694) @[sequencer-master.scala 499:51] + _T_1640 <= UInt<1>("h00") @[sequencer-master.scala 404:19] + _T_1641 <= UInt<1>("h00") @[sequencer-master.scala 405:19] + _T_1642 <= head @[sequencer-master.scala 406:17] + _T_1643 <= tail @[sequencer-master.scala 407:17] + io.master.update.valid[0] <= UInt<1>("h00") @[sequencer-master.scala 410:35] + wire _T_1696 : {vp : {id : UInt<8>}, vs1 : {id : UInt<8>}, vs2 : {id : UInt<8>}, vs3 : {id : UInt<8>}, vd : {id : UInt<8>}} @[sequencer-master.scala 411:70] + _T_1696 is invalid @[sequencer-master.scala 411:70] + wire _T_1697 : UInt<40> + _T_1697 is invalid + _T_1697 <= UInt<1>("h00") + node _T_1698 = bits(_T_1697, 7, 0) @[sequencer-master.scala 411:70] + _T_1696.vd.id <= _T_1698 @[sequencer-master.scala 411:70] + node _T_1699 = bits(_T_1697, 15, 8) @[sequencer-master.scala 411:70] + _T_1696.vs3.id <= _T_1699 @[sequencer-master.scala 411:70] + node _T_1700 = bits(_T_1697, 23, 16) @[sequencer-master.scala 411:70] + _T_1696.vs2.id <= _T_1700 @[sequencer-master.scala 411:70] + node _T_1701 = bits(_T_1697, 31, 24) @[sequencer-master.scala 411:70] + _T_1696.vs1.id <= _T_1701 @[sequencer-master.scala 411:70] + node _T_1702 = bits(_T_1697, 39, 32) @[sequencer-master.scala 411:70] + _T_1696.vp.id <= _T_1702 @[sequencer-master.scala 411:70] + io.master.update.reg[0] <- _T_1696 @[sequencer-master.scala 411:33] + io.master.update.valid[1] <= UInt<1>("h00") @[sequencer-master.scala 410:35] + wire _T_1703 : {vp : {id : UInt<8>}, vs1 : {id : UInt<8>}, vs2 : {id : UInt<8>}, vs3 : {id : UInt<8>}, vd : {id : UInt<8>}} @[sequencer-master.scala 411:70] + _T_1703 is invalid @[sequencer-master.scala 411:70] + wire _T_1704 : UInt<40> + _T_1704 is invalid + _T_1704 <= UInt<1>("h00") + node _T_1705 = bits(_T_1704, 7, 0) @[sequencer-master.scala 411:70] + _T_1703.vd.id <= _T_1705 @[sequencer-master.scala 411:70] + node _T_1706 = bits(_T_1704, 15, 8) @[sequencer-master.scala 411:70] + _T_1703.vs3.id <= _T_1706 @[sequencer-master.scala 411:70] + node _T_1707 = bits(_T_1704, 23, 16) @[sequencer-master.scala 411:70] + _T_1703.vs2.id <= _T_1707 @[sequencer-master.scala 411:70] + node _T_1708 = bits(_T_1704, 31, 24) @[sequencer-master.scala 411:70] + _T_1703.vs1.id <= _T_1708 @[sequencer-master.scala 411:70] + node _T_1709 = bits(_T_1704, 39, 32) @[sequencer-master.scala 411:70] + _T_1703.vp.id <= _T_1709 @[sequencer-master.scala 411:70] + io.master.update.reg[1] <- _T_1703 @[sequencer-master.scala 411:33] + io.master.update.valid[2] <= UInt<1>("h00") @[sequencer-master.scala 410:35] + wire _T_1710 : {vp : {id : UInt<8>}, vs1 : {id : UInt<8>}, vs2 : {id : UInt<8>}, vs3 : {id : UInt<8>}, vd : {id : UInt<8>}} @[sequencer-master.scala 411:70] + _T_1710 is invalid @[sequencer-master.scala 411:70] + wire _T_1711 : UInt<40> + _T_1711 is invalid + _T_1711 <= UInt<1>("h00") + node _T_1712 = bits(_T_1711, 7, 0) @[sequencer-master.scala 411:70] + _T_1710.vd.id <= _T_1712 @[sequencer-master.scala 411:70] + node _T_1713 = bits(_T_1711, 15, 8) @[sequencer-master.scala 411:70] + _T_1710.vs3.id <= _T_1713 @[sequencer-master.scala 411:70] + node _T_1714 = bits(_T_1711, 23, 16) @[sequencer-master.scala 411:70] + _T_1710.vs2.id <= _T_1714 @[sequencer-master.scala 411:70] + node _T_1715 = bits(_T_1711, 31, 24) @[sequencer-master.scala 411:70] + _T_1710.vs1.id <= _T_1715 @[sequencer-master.scala 411:70] + node _T_1716 = bits(_T_1711, 39, 32) @[sequencer-master.scala 411:70] + _T_1710.vp.id <= _T_1716 @[sequencer-master.scala 411:70] + io.master.update.reg[2] <- _T_1710 @[sequencer-master.scala 411:33] + io.master.update.valid[3] <= UInt<1>("h00") @[sequencer-master.scala 410:35] + wire _T_1717 : {vp : {id : UInt<8>}, vs1 : {id : UInt<8>}, vs2 : {id : UInt<8>}, vs3 : {id : UInt<8>}, vd : {id : UInt<8>}} @[sequencer-master.scala 411:70] + _T_1717 is invalid @[sequencer-master.scala 411:70] + wire _T_1718 : UInt<40> + _T_1718 is invalid + _T_1718 <= UInt<1>("h00") + node _T_1719 = bits(_T_1718, 7, 0) @[sequencer-master.scala 411:70] + _T_1717.vd.id <= _T_1719 @[sequencer-master.scala 411:70] + node _T_1720 = bits(_T_1718, 15, 8) @[sequencer-master.scala 411:70] + _T_1717.vs3.id <= _T_1720 @[sequencer-master.scala 411:70] + node _T_1721 = bits(_T_1718, 23, 16) @[sequencer-master.scala 411:70] + _T_1717.vs2.id <= _T_1721 @[sequencer-master.scala 411:70] + node _T_1722 = bits(_T_1718, 31, 24) @[sequencer-master.scala 411:70] + _T_1717.vs1.id <= _T_1722 @[sequencer-master.scala 411:70] + node _T_1723 = bits(_T_1718, 39, 32) @[sequencer-master.scala 411:70] + _T_1717.vp.id <= _T_1723 @[sequencer-master.scala 411:70] + io.master.update.reg[3] <- _T_1717 @[sequencer-master.scala 411:33] + io.master.update.valid[4] <= UInt<1>("h00") @[sequencer-master.scala 410:35] + wire _T_1724 : {vp : {id : UInt<8>}, vs1 : {id : UInt<8>}, vs2 : {id : UInt<8>}, vs3 : {id : UInt<8>}, vd : {id : UInt<8>}} @[sequencer-master.scala 411:70] + _T_1724 is invalid @[sequencer-master.scala 411:70] + wire _T_1725 : UInt<40> + _T_1725 is invalid + _T_1725 <= UInt<1>("h00") + node _T_1726 = bits(_T_1725, 7, 0) @[sequencer-master.scala 411:70] + _T_1724.vd.id <= _T_1726 @[sequencer-master.scala 411:70] + node _T_1727 = bits(_T_1725, 15, 8) @[sequencer-master.scala 411:70] + _T_1724.vs3.id <= _T_1727 @[sequencer-master.scala 411:70] + node _T_1728 = bits(_T_1725, 23, 16) @[sequencer-master.scala 411:70] + _T_1724.vs2.id <= _T_1728 @[sequencer-master.scala 411:70] + node _T_1729 = bits(_T_1725, 31, 24) @[sequencer-master.scala 411:70] + _T_1724.vs1.id <= _T_1729 @[sequencer-master.scala 411:70] + node _T_1730 = bits(_T_1725, 39, 32) @[sequencer-master.scala 411:70] + _T_1724.vp.id <= _T_1730 @[sequencer-master.scala 411:70] + io.master.update.reg[4] <- _T_1724 @[sequencer-master.scala 411:33] + io.master.update.valid[5] <= UInt<1>("h00") @[sequencer-master.scala 410:35] + wire _T_1731 : {vp : {id : UInt<8>}, vs1 : {id : UInt<8>}, vs2 : {id : UInt<8>}, vs3 : {id : UInt<8>}, vd : {id : UInt<8>}} @[sequencer-master.scala 411:70] + _T_1731 is invalid @[sequencer-master.scala 411:70] + wire _T_1732 : UInt<40> + _T_1732 is invalid + _T_1732 <= UInt<1>("h00") + node _T_1733 = bits(_T_1732, 7, 0) @[sequencer-master.scala 411:70] + _T_1731.vd.id <= _T_1733 @[sequencer-master.scala 411:70] + node _T_1734 = bits(_T_1732, 15, 8) @[sequencer-master.scala 411:70] + _T_1731.vs3.id <= _T_1734 @[sequencer-master.scala 411:70] + node _T_1735 = bits(_T_1732, 23, 16) @[sequencer-master.scala 411:70] + _T_1731.vs2.id <= _T_1735 @[sequencer-master.scala 411:70] + node _T_1736 = bits(_T_1732, 31, 24) @[sequencer-master.scala 411:70] + _T_1731.vs1.id <= _T_1736 @[sequencer-master.scala 411:70] + node _T_1737 = bits(_T_1732, 39, 32) @[sequencer-master.scala 411:70] + _T_1731.vp.id <= _T_1737 @[sequencer-master.scala 411:70] + io.master.update.reg[5] <- _T_1731 @[sequencer-master.scala 411:33] + io.master.update.valid[6] <= UInt<1>("h00") @[sequencer-master.scala 410:35] + wire _T_1738 : {vp : {id : UInt<8>}, vs1 : {id : UInt<8>}, vs2 : {id : UInt<8>}, vs3 : {id : UInt<8>}, vd : {id : UInt<8>}} @[sequencer-master.scala 411:70] + _T_1738 is invalid @[sequencer-master.scala 411:70] + wire _T_1739 : UInt<40> + _T_1739 is invalid + _T_1739 <= UInt<1>("h00") + node _T_1740 = bits(_T_1739, 7, 0) @[sequencer-master.scala 411:70] + _T_1738.vd.id <= _T_1740 @[sequencer-master.scala 411:70] + node _T_1741 = bits(_T_1739, 15, 8) @[sequencer-master.scala 411:70] + _T_1738.vs3.id <= _T_1741 @[sequencer-master.scala 411:70] + node _T_1742 = bits(_T_1739, 23, 16) @[sequencer-master.scala 411:70] + _T_1738.vs2.id <= _T_1742 @[sequencer-master.scala 411:70] + node _T_1743 = bits(_T_1739, 31, 24) @[sequencer-master.scala 411:70] + _T_1738.vs1.id <= _T_1743 @[sequencer-master.scala 411:70] + node _T_1744 = bits(_T_1739, 39, 32) @[sequencer-master.scala 411:70] + _T_1738.vp.id <= _T_1744 @[sequencer-master.scala 411:70] + io.master.update.reg[6] <- _T_1738 @[sequencer-master.scala 411:33] + io.master.update.valid[7] <= UInt<1>("h00") @[sequencer-master.scala 410:35] + wire _T_1745 : {vp : {id : UInt<8>}, vs1 : {id : UInt<8>}, vs2 : {id : UInt<8>}, vs3 : {id : UInt<8>}, vd : {id : UInt<8>}} @[sequencer-master.scala 411:70] + _T_1745 is invalid @[sequencer-master.scala 411:70] + wire _T_1746 : UInt<40> + _T_1746 is invalid + _T_1746 <= UInt<1>("h00") + node _T_1747 = bits(_T_1746, 7, 0) @[sequencer-master.scala 411:70] + _T_1745.vd.id <= _T_1747 @[sequencer-master.scala 411:70] + node _T_1748 = bits(_T_1746, 15, 8) @[sequencer-master.scala 411:70] + _T_1745.vs3.id <= _T_1748 @[sequencer-master.scala 411:70] + node _T_1749 = bits(_T_1746, 23, 16) @[sequencer-master.scala 411:70] + _T_1745.vs2.id <= _T_1749 @[sequencer-master.scala 411:70] + node _T_1750 = bits(_T_1746, 31, 24) @[sequencer-master.scala 411:70] + _T_1745.vs1.id <= _T_1750 @[sequencer-master.scala 411:70] + node _T_1751 = bits(_T_1746, 39, 32) @[sequencer-master.scala 411:70] + _T_1745.vp.id <= _T_1751 @[sequencer-master.scala 411:70] + io.master.update.reg[7] <- _T_1745 @[sequencer-master.scala 411:33] + _T_1[0] <= UInt<1>("h00") @[sequencer-master.scala 192:24] + _T_2[0][0] <= e[0].raw[0] @[sequencer-master.scala 194:26] + _T_3[0][0] <= e[0].war[0] @[sequencer-master.scala 195:26] + _T_4[0][0] <= e[0].waw[0] @[sequencer-master.scala 196:26] + _T_2[0][1] <= e[0].raw[1] @[sequencer-master.scala 194:26] + _T_3[0][1] <= e[0].war[1] @[sequencer-master.scala 195:26] + _T_4[0][1] <= e[0].waw[1] @[sequencer-master.scala 196:26] + _T_2[0][2] <= e[0].raw[2] @[sequencer-master.scala 194:26] + _T_3[0][2] <= e[0].war[2] @[sequencer-master.scala 195:26] + _T_4[0][2] <= e[0].waw[2] @[sequencer-master.scala 196:26] + _T_2[0][3] <= e[0].raw[3] @[sequencer-master.scala 194:26] + _T_3[0][3] <= e[0].war[3] @[sequencer-master.scala 195:26] + _T_4[0][3] <= e[0].waw[3] @[sequencer-master.scala 196:26] + _T_2[0][4] <= e[0].raw[4] @[sequencer-master.scala 194:26] + _T_3[0][4] <= e[0].war[4] @[sequencer-master.scala 195:26] + _T_4[0][4] <= e[0].waw[4] @[sequencer-master.scala 196:26] + _T_2[0][5] <= e[0].raw[5] @[sequencer-master.scala 194:26] + _T_3[0][5] <= e[0].war[5] @[sequencer-master.scala 195:26] + _T_4[0][5] <= e[0].waw[5] @[sequencer-master.scala 196:26] + _T_2[0][6] <= e[0].raw[6] @[sequencer-master.scala 194:26] + _T_3[0][6] <= e[0].war[6] @[sequencer-master.scala 195:26] + _T_4[0][6] <= e[0].waw[6] @[sequencer-master.scala 196:26] + _T_2[0][7] <= e[0].raw[7] @[sequencer-master.scala 194:26] + _T_3[0][7] <= e[0].war[7] @[sequencer-master.scala 195:26] + _T_4[0][7] <= e[0].waw[7] @[sequencer-master.scala 196:26] + _T_1[1] <= UInt<1>("h00") @[sequencer-master.scala 192:24] + _T_2[1][0] <= e[1].raw[0] @[sequencer-master.scala 194:26] + _T_3[1][0] <= e[1].war[0] @[sequencer-master.scala 195:26] + _T_4[1][0] <= e[1].waw[0] @[sequencer-master.scala 196:26] + _T_2[1][1] <= e[1].raw[1] @[sequencer-master.scala 194:26] + _T_3[1][1] <= e[1].war[1] @[sequencer-master.scala 195:26] + _T_4[1][1] <= e[1].waw[1] @[sequencer-master.scala 196:26] + _T_2[1][2] <= e[1].raw[2] @[sequencer-master.scala 194:26] + _T_3[1][2] <= e[1].war[2] @[sequencer-master.scala 195:26] + _T_4[1][2] <= e[1].waw[2] @[sequencer-master.scala 196:26] + _T_2[1][3] <= e[1].raw[3] @[sequencer-master.scala 194:26] + _T_3[1][3] <= e[1].war[3] @[sequencer-master.scala 195:26] + _T_4[1][3] <= e[1].waw[3] @[sequencer-master.scala 196:26] + _T_2[1][4] <= e[1].raw[4] @[sequencer-master.scala 194:26] + _T_3[1][4] <= e[1].war[4] @[sequencer-master.scala 195:26] + _T_4[1][4] <= e[1].waw[4] @[sequencer-master.scala 196:26] + _T_2[1][5] <= e[1].raw[5] @[sequencer-master.scala 194:26] + _T_3[1][5] <= e[1].war[5] @[sequencer-master.scala 195:26] + _T_4[1][5] <= e[1].waw[5] @[sequencer-master.scala 196:26] + _T_2[1][6] <= e[1].raw[6] @[sequencer-master.scala 194:26] + _T_3[1][6] <= e[1].war[6] @[sequencer-master.scala 195:26] + _T_4[1][6] <= e[1].waw[6] @[sequencer-master.scala 196:26] + _T_2[1][7] <= e[1].raw[7] @[sequencer-master.scala 194:26] + _T_3[1][7] <= e[1].war[7] @[sequencer-master.scala 195:26] + _T_4[1][7] <= e[1].waw[7] @[sequencer-master.scala 196:26] + _T_1[2] <= UInt<1>("h00") @[sequencer-master.scala 192:24] + _T_2[2][0] <= e[2].raw[0] @[sequencer-master.scala 194:26] + _T_3[2][0] <= e[2].war[0] @[sequencer-master.scala 195:26] + _T_4[2][0] <= e[2].waw[0] @[sequencer-master.scala 196:26] + _T_2[2][1] <= e[2].raw[1] @[sequencer-master.scala 194:26] + _T_3[2][1] <= e[2].war[1] @[sequencer-master.scala 195:26] + _T_4[2][1] <= e[2].waw[1] @[sequencer-master.scala 196:26] + _T_2[2][2] <= e[2].raw[2] @[sequencer-master.scala 194:26] + _T_3[2][2] <= e[2].war[2] @[sequencer-master.scala 195:26] + _T_4[2][2] <= e[2].waw[2] @[sequencer-master.scala 196:26] + _T_2[2][3] <= e[2].raw[3] @[sequencer-master.scala 194:26] + _T_3[2][3] <= e[2].war[3] @[sequencer-master.scala 195:26] + _T_4[2][3] <= e[2].waw[3] @[sequencer-master.scala 196:26] + _T_2[2][4] <= e[2].raw[4] @[sequencer-master.scala 194:26] + _T_3[2][4] <= e[2].war[4] @[sequencer-master.scala 195:26] + _T_4[2][4] <= e[2].waw[4] @[sequencer-master.scala 196:26] + _T_2[2][5] <= e[2].raw[5] @[sequencer-master.scala 194:26] + _T_3[2][5] <= e[2].war[5] @[sequencer-master.scala 195:26] + _T_4[2][5] <= e[2].waw[5] @[sequencer-master.scala 196:26] + _T_2[2][6] <= e[2].raw[6] @[sequencer-master.scala 194:26] + _T_3[2][6] <= e[2].war[6] @[sequencer-master.scala 195:26] + _T_4[2][6] <= e[2].waw[6] @[sequencer-master.scala 196:26] + _T_2[2][7] <= e[2].raw[7] @[sequencer-master.scala 194:26] + _T_3[2][7] <= e[2].war[7] @[sequencer-master.scala 195:26] + _T_4[2][7] <= e[2].waw[7] @[sequencer-master.scala 196:26] + _T_1[3] <= UInt<1>("h00") @[sequencer-master.scala 192:24] + _T_2[3][0] <= e[3].raw[0] @[sequencer-master.scala 194:26] + _T_3[3][0] <= e[3].war[0] @[sequencer-master.scala 195:26] + _T_4[3][0] <= e[3].waw[0] @[sequencer-master.scala 196:26] + _T_2[3][1] <= e[3].raw[1] @[sequencer-master.scala 194:26] + _T_3[3][1] <= e[3].war[1] @[sequencer-master.scala 195:26] + _T_4[3][1] <= e[3].waw[1] @[sequencer-master.scala 196:26] + _T_2[3][2] <= e[3].raw[2] @[sequencer-master.scala 194:26] + _T_3[3][2] <= e[3].war[2] @[sequencer-master.scala 195:26] + _T_4[3][2] <= e[3].waw[2] @[sequencer-master.scala 196:26] + _T_2[3][3] <= e[3].raw[3] @[sequencer-master.scala 194:26] + _T_3[3][3] <= e[3].war[3] @[sequencer-master.scala 195:26] + _T_4[3][3] <= e[3].waw[3] @[sequencer-master.scala 196:26] + _T_2[3][4] <= e[3].raw[4] @[sequencer-master.scala 194:26] + _T_3[3][4] <= e[3].war[4] @[sequencer-master.scala 195:26] + _T_4[3][4] <= e[3].waw[4] @[sequencer-master.scala 196:26] + _T_2[3][5] <= e[3].raw[5] @[sequencer-master.scala 194:26] + _T_3[3][5] <= e[3].war[5] @[sequencer-master.scala 195:26] + _T_4[3][5] <= e[3].waw[5] @[sequencer-master.scala 196:26] + _T_2[3][6] <= e[3].raw[6] @[sequencer-master.scala 194:26] + _T_3[3][6] <= e[3].war[6] @[sequencer-master.scala 195:26] + _T_4[3][6] <= e[3].waw[6] @[sequencer-master.scala 196:26] + _T_2[3][7] <= e[3].raw[7] @[sequencer-master.scala 194:26] + _T_3[3][7] <= e[3].war[7] @[sequencer-master.scala 195:26] + _T_4[3][7] <= e[3].waw[7] @[sequencer-master.scala 196:26] + _T_1[4] <= UInt<1>("h00") @[sequencer-master.scala 192:24] + _T_2[4][0] <= e[4].raw[0] @[sequencer-master.scala 194:26] + _T_3[4][0] <= e[4].war[0] @[sequencer-master.scala 195:26] + _T_4[4][0] <= e[4].waw[0] @[sequencer-master.scala 196:26] + _T_2[4][1] <= e[4].raw[1] @[sequencer-master.scala 194:26] + _T_3[4][1] <= e[4].war[1] @[sequencer-master.scala 195:26] + _T_4[4][1] <= e[4].waw[1] @[sequencer-master.scala 196:26] + _T_2[4][2] <= e[4].raw[2] @[sequencer-master.scala 194:26] + _T_3[4][2] <= e[4].war[2] @[sequencer-master.scala 195:26] + _T_4[4][2] <= e[4].waw[2] @[sequencer-master.scala 196:26] + _T_2[4][3] <= e[4].raw[3] @[sequencer-master.scala 194:26] + _T_3[4][3] <= e[4].war[3] @[sequencer-master.scala 195:26] + _T_4[4][3] <= e[4].waw[3] @[sequencer-master.scala 196:26] + _T_2[4][4] <= e[4].raw[4] @[sequencer-master.scala 194:26] + _T_3[4][4] <= e[4].war[4] @[sequencer-master.scala 195:26] + _T_4[4][4] <= e[4].waw[4] @[sequencer-master.scala 196:26] + _T_2[4][5] <= e[4].raw[5] @[sequencer-master.scala 194:26] + _T_3[4][5] <= e[4].war[5] @[sequencer-master.scala 195:26] + _T_4[4][5] <= e[4].waw[5] @[sequencer-master.scala 196:26] + _T_2[4][6] <= e[4].raw[6] @[sequencer-master.scala 194:26] + _T_3[4][6] <= e[4].war[6] @[sequencer-master.scala 195:26] + _T_4[4][6] <= e[4].waw[6] @[sequencer-master.scala 196:26] + _T_2[4][7] <= e[4].raw[7] @[sequencer-master.scala 194:26] + _T_3[4][7] <= e[4].war[7] @[sequencer-master.scala 195:26] + _T_4[4][7] <= e[4].waw[7] @[sequencer-master.scala 196:26] + _T_1[5] <= UInt<1>("h00") @[sequencer-master.scala 192:24] + _T_2[5][0] <= e[5].raw[0] @[sequencer-master.scala 194:26] + _T_3[5][0] <= e[5].war[0] @[sequencer-master.scala 195:26] + _T_4[5][0] <= e[5].waw[0] @[sequencer-master.scala 196:26] + _T_2[5][1] <= e[5].raw[1] @[sequencer-master.scala 194:26] + _T_3[5][1] <= e[5].war[1] @[sequencer-master.scala 195:26] + _T_4[5][1] <= e[5].waw[1] @[sequencer-master.scala 196:26] + _T_2[5][2] <= e[5].raw[2] @[sequencer-master.scala 194:26] + _T_3[5][2] <= e[5].war[2] @[sequencer-master.scala 195:26] + _T_4[5][2] <= e[5].waw[2] @[sequencer-master.scala 196:26] + _T_2[5][3] <= e[5].raw[3] @[sequencer-master.scala 194:26] + _T_3[5][3] <= e[5].war[3] @[sequencer-master.scala 195:26] + _T_4[5][3] <= e[5].waw[3] @[sequencer-master.scala 196:26] + _T_2[5][4] <= e[5].raw[4] @[sequencer-master.scala 194:26] + _T_3[5][4] <= e[5].war[4] @[sequencer-master.scala 195:26] + _T_4[5][4] <= e[5].waw[4] @[sequencer-master.scala 196:26] + _T_2[5][5] <= e[5].raw[5] @[sequencer-master.scala 194:26] + _T_3[5][5] <= e[5].war[5] @[sequencer-master.scala 195:26] + _T_4[5][5] <= e[5].waw[5] @[sequencer-master.scala 196:26] + _T_2[5][6] <= e[5].raw[6] @[sequencer-master.scala 194:26] + _T_3[5][6] <= e[5].war[6] @[sequencer-master.scala 195:26] + _T_4[5][6] <= e[5].waw[6] @[sequencer-master.scala 196:26] + _T_2[5][7] <= e[5].raw[7] @[sequencer-master.scala 194:26] + _T_3[5][7] <= e[5].war[7] @[sequencer-master.scala 195:26] + _T_4[5][7] <= e[5].waw[7] @[sequencer-master.scala 196:26] + _T_1[6] <= UInt<1>("h00") @[sequencer-master.scala 192:24] + _T_2[6][0] <= e[6].raw[0] @[sequencer-master.scala 194:26] + _T_3[6][0] <= e[6].war[0] @[sequencer-master.scala 195:26] + _T_4[6][0] <= e[6].waw[0] @[sequencer-master.scala 196:26] + _T_2[6][1] <= e[6].raw[1] @[sequencer-master.scala 194:26] + _T_3[6][1] <= e[6].war[1] @[sequencer-master.scala 195:26] + _T_4[6][1] <= e[6].waw[1] @[sequencer-master.scala 196:26] + _T_2[6][2] <= e[6].raw[2] @[sequencer-master.scala 194:26] + _T_3[6][2] <= e[6].war[2] @[sequencer-master.scala 195:26] + _T_4[6][2] <= e[6].waw[2] @[sequencer-master.scala 196:26] + _T_2[6][3] <= e[6].raw[3] @[sequencer-master.scala 194:26] + _T_3[6][3] <= e[6].war[3] @[sequencer-master.scala 195:26] + _T_4[6][3] <= e[6].waw[3] @[sequencer-master.scala 196:26] + _T_2[6][4] <= e[6].raw[4] @[sequencer-master.scala 194:26] + _T_3[6][4] <= e[6].war[4] @[sequencer-master.scala 195:26] + _T_4[6][4] <= e[6].waw[4] @[sequencer-master.scala 196:26] + _T_2[6][5] <= e[6].raw[5] @[sequencer-master.scala 194:26] + _T_3[6][5] <= e[6].war[5] @[sequencer-master.scala 195:26] + _T_4[6][5] <= e[6].waw[5] @[sequencer-master.scala 196:26] + _T_2[6][6] <= e[6].raw[6] @[sequencer-master.scala 194:26] + _T_3[6][6] <= e[6].war[6] @[sequencer-master.scala 195:26] + _T_4[6][6] <= e[6].waw[6] @[sequencer-master.scala 196:26] + _T_2[6][7] <= e[6].raw[7] @[sequencer-master.scala 194:26] + _T_3[6][7] <= e[6].war[7] @[sequencer-master.scala 195:26] + _T_4[6][7] <= e[6].waw[7] @[sequencer-master.scala 196:26] + _T_1[7] <= UInt<1>("h00") @[sequencer-master.scala 192:24] + _T_2[7][0] <= e[7].raw[0] @[sequencer-master.scala 194:26] + _T_3[7][0] <= e[7].war[0] @[sequencer-master.scala 195:26] + _T_4[7][0] <= e[7].waw[0] @[sequencer-master.scala 196:26] + _T_2[7][1] <= e[7].raw[1] @[sequencer-master.scala 194:26] + _T_3[7][1] <= e[7].war[1] @[sequencer-master.scala 195:26] + _T_4[7][1] <= e[7].waw[1] @[sequencer-master.scala 196:26] + _T_2[7][2] <= e[7].raw[2] @[sequencer-master.scala 194:26] + _T_3[7][2] <= e[7].war[2] @[sequencer-master.scala 195:26] + _T_4[7][2] <= e[7].waw[2] @[sequencer-master.scala 196:26] + _T_2[7][3] <= e[7].raw[3] @[sequencer-master.scala 194:26] + _T_3[7][3] <= e[7].war[3] @[sequencer-master.scala 195:26] + _T_4[7][3] <= e[7].waw[3] @[sequencer-master.scala 196:26] + _T_2[7][4] <= e[7].raw[4] @[sequencer-master.scala 194:26] + _T_3[7][4] <= e[7].war[4] @[sequencer-master.scala 195:26] + _T_4[7][4] <= e[7].waw[4] @[sequencer-master.scala 196:26] + _T_2[7][5] <= e[7].raw[5] @[sequencer-master.scala 194:26] + _T_3[7][5] <= e[7].war[5] @[sequencer-master.scala 195:26] + _T_4[7][5] <= e[7].waw[5] @[sequencer-master.scala 196:26] + _T_2[7][6] <= e[7].raw[6] @[sequencer-master.scala 194:26] + _T_3[7][6] <= e[7].war[6] @[sequencer-master.scala 195:26] + _T_4[7][6] <= e[7].waw[6] @[sequencer-master.scala 196:26] + _T_2[7][7] <= e[7].raw[7] @[sequencer-master.scala 194:26] + _T_3[7][7] <= e[7].war[7] @[sequencer-master.scala 195:26] + _T_4[7][7] <= e[7].waw[7] @[sequencer-master.scala 196:26] + node _T_1752 = and(io.op.ready, io.op.valid) @[Decoupled.scala 37:37] + when _T_1752 : @[sequencer-master.scala 639:27] + when io.op.bits.active.vint : @[sequencer-master.scala 640:39] + v[tail] <= UInt<1>("h01") @[sequencer-master.scala 267:35] + e[tail].rate <= UInt<1>("h00") @[sequencer-master.scala 271:19] + e[tail].base.vp.valid <= UInt<1>("h00") @[sequencer-master.scala 272:28] + e[tail].base.vs1.valid <= UInt<1>("h00") @[sequencer-master.scala 273:29] + e[tail].base.vs2.valid <= UInt<1>("h00") @[sequencer-master.scala 274:29] + e[tail].base.vs3.valid <= UInt<1>("h00") @[sequencer-master.scala 275:29] + e[tail].base.vd.valid <= UInt<1>("h00") @[sequencer-master.scala 276:28] + _T_1[tail] <= UInt<1>("h01") @[sequencer-master.scala 188:42] + _T_2[tail][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + e[tail].last <= UInt<1>("h00") @[sequencer-master.scala 283:19] + io.master.update.valid[tail] <= UInt<1>("h01") @[sequencer-master.scala 284:35] + e[tail].active.viu <= UInt<1>("h01") @[sequencer-master.scala 288:26] + e[tail].fn.union <= io.op.bits.fn.union @[sequencer-master.scala 289:23] + when io.op.bits.base.vp.valid : @[sequencer-master.scala 320:41] + e[tail].base.vp <- io.op.bits.base.vp @[sequencer-master.scala 321:24] + io.master.update.reg[tail].vp.id <= io.op.bits.reg.vp.id @[sequencer-master.scala 322:41] + skip @[sequencer-master.scala 320:41] + when _T_181[0] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[1] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[2] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[3] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[4] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[5] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[6] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[7] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when io.op.bits.base.vs1.valid : @[sequencer-master.scala 328:47] + e[tail].base.vs1 <- io.op.bits.base.vs1 @[sequencer-master.scala 329:29] + io.master.update.reg[tail].vs1.id <= io.op.bits.reg.vs1.id @[sequencer-master.scala 330:47] + node _T_1753 = eq(io.op.bits.base.vs1.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1754 = and(_T_1753, io.op.bits.base.vs1.scalar) @[types-vxu.scala 119:37] + when _T_1754 : @[sequencer-master.scala 331:55] + e[tail].sreg.ss1 <= io.op.bits.sreg.ss1 @[sequencer-master.scala 332:31] + skip @[sequencer-master.scala 331:55] + skip @[sequencer-master.scala 328:47] + when _T_358[0] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[1] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[2] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[3] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[4] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[5] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[6] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[7] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when io.op.bits.base.vs2.valid : @[sequencer-master.scala 328:47] + e[tail].base.vs2 <- io.op.bits.base.vs2 @[sequencer-master.scala 329:29] + io.master.update.reg[tail].vs2.id <= io.op.bits.reg.vs2.id @[sequencer-master.scala 330:47] + node _T_1755 = eq(io.op.bits.base.vs2.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1756 = and(_T_1755, io.op.bits.base.vs2.scalar) @[types-vxu.scala 119:37] + when _T_1756 : @[sequencer-master.scala 331:55] + e[tail].sreg.ss2 <= io.op.bits.sreg.ss2 @[sequencer-master.scala 332:31] + skip @[sequencer-master.scala 331:55] + skip @[sequencer-master.scala 328:47] + when _T_535[0] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[1] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[2] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[3] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[4] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[5] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[6] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[7] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + node _T_1757 = eq(io.op.bits.base.vd.valid, UInt<1>("h00")) @[sequencer-master.scala 361:16] + node _T_1758 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1759 = and(_T_1758, io.op.bits.base.vd.scalar) @[types-vxu.scala 119:37] + node _T_1760 = eq(_T_1759, UInt<1>("h00")) @[sequencer-master.scala 361:45] + node _T_1761 = or(_T_1757, _T_1760) @[sequencer-master.scala 361:42] + node _T_1762 = bits(reset, 0, 0) @[sequencer-master.scala 361:15] + node _T_1763 = or(_T_1761, _T_1762) @[sequencer-master.scala 361:15] + node _T_1764 = eq(_T_1763, UInt<1>("h00")) @[sequencer-master.scala 361:15] + when _T_1764 : @[sequencer-master.scala 361:15] + printf(clock, UInt<1>(1), "Assertion failed: iwindow.set.vd: vd should always be vector\n at sequencer-master.scala:361 assert(!io.op.bits.base.vd.valid || !io.op.bits.base.vd.is_scalar(), \"iwindow.set.vd: vd should always be vector\")\n") @[sequencer-master.scala 361:15] + stop(clock, UInt<1>(1), 1) @[sequencer-master.scala 361:15] + skip @[sequencer-master.scala 361:15] + when io.op.bits.base.vd.valid : @[sequencer-master.scala 362:41] + e[tail].base.vd <- io.op.bits.base.vd @[sequencer-master.scala 363:24] + io.master.update.reg[tail].vd.id <= io.op.bits.reg.vd.id @[sequencer-master.scala 364:41] + skip @[sequencer-master.scala 362:41] + node _T_1765 = or(_T_889[0], _T_1066[0]) @[sequencer-master.scala 161:31] + node _T_1766 = or(_T_1765, _T_1243[0]) @[sequencer-master.scala 161:49] + node _T_1767 = or(_T_1766, _T_1420[0]) @[sequencer-master.scala 161:67] + when _T_1767 : @[sequencer-master.scala 161:86] + _T_3[tail][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_1768 = or(_T_889[1], _T_1066[1]) @[sequencer-master.scala 161:31] + node _T_1769 = or(_T_1768, _T_1243[1]) @[sequencer-master.scala 161:49] + node _T_1770 = or(_T_1769, _T_1420[1]) @[sequencer-master.scala 161:67] + when _T_1770 : @[sequencer-master.scala 161:86] + _T_3[tail][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_1771 = or(_T_889[2], _T_1066[2]) @[sequencer-master.scala 161:31] + node _T_1772 = or(_T_1771, _T_1243[2]) @[sequencer-master.scala 161:49] + node _T_1773 = or(_T_1772, _T_1420[2]) @[sequencer-master.scala 161:67] + when _T_1773 : @[sequencer-master.scala 161:86] + _T_3[tail][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_1774 = or(_T_889[3], _T_1066[3]) @[sequencer-master.scala 161:31] + node _T_1775 = or(_T_1774, _T_1243[3]) @[sequencer-master.scala 161:49] + node _T_1776 = or(_T_1775, _T_1420[3]) @[sequencer-master.scala 161:67] + when _T_1776 : @[sequencer-master.scala 161:86] + _T_3[tail][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_1777 = or(_T_889[4], _T_1066[4]) @[sequencer-master.scala 161:31] + node _T_1778 = or(_T_1777, _T_1243[4]) @[sequencer-master.scala 161:49] + node _T_1779 = or(_T_1778, _T_1420[4]) @[sequencer-master.scala 161:67] + when _T_1779 : @[sequencer-master.scala 161:86] + _T_3[tail][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_1780 = or(_T_889[5], _T_1066[5]) @[sequencer-master.scala 161:31] + node _T_1781 = or(_T_1780, _T_1243[5]) @[sequencer-master.scala 161:49] + node _T_1782 = or(_T_1781, _T_1420[5]) @[sequencer-master.scala 161:67] + when _T_1782 : @[sequencer-master.scala 161:86] + _T_3[tail][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_1783 = or(_T_889[6], _T_1066[6]) @[sequencer-master.scala 161:31] + node _T_1784 = or(_T_1783, _T_1243[6]) @[sequencer-master.scala 161:49] + node _T_1785 = or(_T_1784, _T_1420[6]) @[sequencer-master.scala 161:67] + when _T_1785 : @[sequencer-master.scala 161:86] + _T_3[tail][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_1786 = or(_T_889[7], _T_1066[7]) @[sequencer-master.scala 161:31] + node _T_1787 = or(_T_1786, _T_1243[7]) @[sequencer-master.scala 161:49] + node _T_1788 = or(_T_1787, _T_1420[7]) @[sequencer-master.scala 161:67] + when _T_1788 : @[sequencer-master.scala 161:86] + _T_3[tail][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + when _T_1597[0] : @[sequencer-master.scala 168:32] + _T_4[tail][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[1] : @[sequencer-master.scala 168:32] + _T_4[tail][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[2] : @[sequencer-master.scala 168:32] + _T_4[tail][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[3] : @[sequencer-master.scala 168:32] + _T_4[tail][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[4] : @[sequencer-master.scala 168:32] + _T_4[tail][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[5] : @[sequencer-master.scala 168:32] + _T_4[tail][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[6] : @[sequencer-master.scala 168:32] + _T_4[tail][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[7] : @[sequencer-master.scala 168:32] + _T_4[tail][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + e[tail].rports <= _T_1615 @[sequencer-master.scala 230:21] + e[tail].wport.sram <= UInt<1>("h00") @[sequencer-master.scala 231:25] + e[tail].wport.pred <= UInt<1>("h00") @[sequencer-master.scala 232:25] + node _T_1789 = add(UInt<4>("h00"), _T_1615) @[sequencer-master.scala 247:46] + node _T_1790 = tail(_T_1789, 1) @[sequencer-master.scala 247:46] + node _T_1791 = add(_T_1790, UInt<2>("h02")) @[sequencer-master.scala 247:56] + node _T_1792 = tail(_T_1791, 1) @[sequencer-master.scala 247:56] + node _T_1793 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1794 = eq(io.op.bits.base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1795 = and(_T_1793, _T_1794) @[types-vxu.scala 120:37] + when _T_1795 : @[sequencer-master.scala 235:47] + e[tail].wport.sram <= _T_1792 @[sequencer-master.scala 235:65] + skip @[sequencer-master.scala 235:47] + when io.op.bits.base.vd.pred : @[sequencer-master.scala 236:45] + e[tail].wport.pred <= _T_1792 @[sequencer-master.scala 236:63] + skip @[sequencer-master.scala 236:45] + _T_1641 <= UInt<1>("h01") @[sequencer-master.scala 265:41] + _T_1643 <= _T_1645 @[sequencer-master.scala 265:66] + skip @[sequencer-master.scala 640:39] + when io.op.bits.active.vipred : @[sequencer-master.scala 641:41] + v[tail] <= UInt<1>("h01") @[sequencer-master.scala 267:35] + e[tail].rate <= UInt<1>("h00") @[sequencer-master.scala 271:19] + e[tail].base.vp.valid <= UInt<1>("h00") @[sequencer-master.scala 272:28] + e[tail].base.vs1.valid <= UInt<1>("h00") @[sequencer-master.scala 273:29] + e[tail].base.vs2.valid <= UInt<1>("h00") @[sequencer-master.scala 274:29] + e[tail].base.vs3.valid <= UInt<1>("h00") @[sequencer-master.scala 275:29] + e[tail].base.vd.valid <= UInt<1>("h00") @[sequencer-master.scala 276:28] + _T_1[tail] <= UInt<1>("h01") @[sequencer-master.scala 188:42] + _T_2[tail][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + e[tail].last <= UInt<1>("h00") @[sequencer-master.scala 283:19] + io.master.update.valid[tail] <= UInt<1>("h01") @[sequencer-master.scala 284:35] + e[tail].active.vipu <= UInt<1>("h01") @[sequencer-master.scala 288:26] + e[tail].fn.union <= io.op.bits.fn.union @[sequencer-master.scala 289:23] + when io.op.bits.base.vs1.valid : @[sequencer-master.scala 328:47] + e[tail].base.vs1 <- io.op.bits.base.vs1 @[sequencer-master.scala 329:29] + io.master.update.reg[tail].vs1.id <= io.op.bits.reg.vs1.id @[sequencer-master.scala 330:47] + node _T_1796 = eq(io.op.bits.base.vs1.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1797 = and(_T_1796, io.op.bits.base.vs1.scalar) @[types-vxu.scala 119:37] + when _T_1797 : @[sequencer-master.scala 331:55] + e[tail].sreg.ss1 <= io.op.bits.sreg.ss1 @[sequencer-master.scala 332:31] + skip @[sequencer-master.scala 331:55] + skip @[sequencer-master.scala 328:47] + when _T_358[0] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[1] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[2] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[3] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[4] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[5] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[6] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[7] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when io.op.bits.base.vs2.valid : @[sequencer-master.scala 328:47] + e[tail].base.vs2 <- io.op.bits.base.vs2 @[sequencer-master.scala 329:29] + io.master.update.reg[tail].vs2.id <= io.op.bits.reg.vs2.id @[sequencer-master.scala 330:47] + node _T_1798 = eq(io.op.bits.base.vs2.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1799 = and(_T_1798, io.op.bits.base.vs2.scalar) @[types-vxu.scala 119:37] + when _T_1799 : @[sequencer-master.scala 331:55] + e[tail].sreg.ss2 <= io.op.bits.sreg.ss2 @[sequencer-master.scala 332:31] + skip @[sequencer-master.scala 331:55] + skip @[sequencer-master.scala 328:47] + when _T_535[0] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[1] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[2] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[3] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[4] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[5] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[6] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[7] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when io.op.bits.base.vs3.valid : @[sequencer-master.scala 328:47] + e[tail].base.vs3 <- io.op.bits.base.vs3 @[sequencer-master.scala 329:29] + io.master.update.reg[tail].vs3.id <= io.op.bits.reg.vs3.id @[sequencer-master.scala 330:47] + node _T_1800 = eq(io.op.bits.base.vs3.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1801 = and(_T_1800, io.op.bits.base.vs3.scalar) @[types-vxu.scala 119:37] + when _T_1801 : @[sequencer-master.scala 331:55] + e[tail].sreg.ss3 <= io.op.bits.sreg.ss3 @[sequencer-master.scala 332:31] + skip @[sequencer-master.scala 331:55] + skip @[sequencer-master.scala 328:47] + when _T_712[0] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_712[1] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_712[2] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_712[3] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_712[4] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_712[5] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_712[6] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_712[7] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + node _T_1802 = eq(io.op.bits.base.vd.valid, UInt<1>("h00")) @[sequencer-master.scala 361:16] + node _T_1803 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1804 = and(_T_1803, io.op.bits.base.vd.scalar) @[types-vxu.scala 119:37] + node _T_1805 = eq(_T_1804, UInt<1>("h00")) @[sequencer-master.scala 361:45] + node _T_1806 = or(_T_1802, _T_1805) @[sequencer-master.scala 361:42] + node _T_1807 = bits(reset, 0, 0) @[sequencer-master.scala 361:15] + node _T_1808 = or(_T_1806, _T_1807) @[sequencer-master.scala 361:15] + node _T_1809 = eq(_T_1808, UInt<1>("h00")) @[sequencer-master.scala 361:15] + when _T_1809 : @[sequencer-master.scala 361:15] + printf(clock, UInt<1>(1), "Assertion failed: iwindow.set.vd: vd should always be vector\n at sequencer-master.scala:361 assert(!io.op.bits.base.vd.valid || !io.op.bits.base.vd.is_scalar(), \"iwindow.set.vd: vd should always be vector\")\n") @[sequencer-master.scala 361:15] + stop(clock, UInt<1>(1), 1) @[sequencer-master.scala 361:15] + skip @[sequencer-master.scala 361:15] + when io.op.bits.base.vd.valid : @[sequencer-master.scala 362:41] + e[tail].base.vd <- io.op.bits.base.vd @[sequencer-master.scala 363:24] + io.master.update.reg[tail].vd.id <= io.op.bits.reg.vd.id @[sequencer-master.scala 364:41] + skip @[sequencer-master.scala 362:41] + node _T_1810 = or(_T_889[0], _T_1066[0]) @[sequencer-master.scala 161:31] + node _T_1811 = or(_T_1810, _T_1243[0]) @[sequencer-master.scala 161:49] + node _T_1812 = or(_T_1811, _T_1420[0]) @[sequencer-master.scala 161:67] + when _T_1812 : @[sequencer-master.scala 161:86] + _T_3[tail][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_1813 = or(_T_889[1], _T_1066[1]) @[sequencer-master.scala 161:31] + node _T_1814 = or(_T_1813, _T_1243[1]) @[sequencer-master.scala 161:49] + node _T_1815 = or(_T_1814, _T_1420[1]) @[sequencer-master.scala 161:67] + when _T_1815 : @[sequencer-master.scala 161:86] + _T_3[tail][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_1816 = or(_T_889[2], _T_1066[2]) @[sequencer-master.scala 161:31] + node _T_1817 = or(_T_1816, _T_1243[2]) @[sequencer-master.scala 161:49] + node _T_1818 = or(_T_1817, _T_1420[2]) @[sequencer-master.scala 161:67] + when _T_1818 : @[sequencer-master.scala 161:86] + _T_3[tail][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_1819 = or(_T_889[3], _T_1066[3]) @[sequencer-master.scala 161:31] + node _T_1820 = or(_T_1819, _T_1243[3]) @[sequencer-master.scala 161:49] + node _T_1821 = or(_T_1820, _T_1420[3]) @[sequencer-master.scala 161:67] + when _T_1821 : @[sequencer-master.scala 161:86] + _T_3[tail][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_1822 = or(_T_889[4], _T_1066[4]) @[sequencer-master.scala 161:31] + node _T_1823 = or(_T_1822, _T_1243[4]) @[sequencer-master.scala 161:49] + node _T_1824 = or(_T_1823, _T_1420[4]) @[sequencer-master.scala 161:67] + when _T_1824 : @[sequencer-master.scala 161:86] + _T_3[tail][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_1825 = or(_T_889[5], _T_1066[5]) @[sequencer-master.scala 161:31] + node _T_1826 = or(_T_1825, _T_1243[5]) @[sequencer-master.scala 161:49] + node _T_1827 = or(_T_1826, _T_1420[5]) @[sequencer-master.scala 161:67] + when _T_1827 : @[sequencer-master.scala 161:86] + _T_3[tail][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_1828 = or(_T_889[6], _T_1066[6]) @[sequencer-master.scala 161:31] + node _T_1829 = or(_T_1828, _T_1243[6]) @[sequencer-master.scala 161:49] + node _T_1830 = or(_T_1829, _T_1420[6]) @[sequencer-master.scala 161:67] + when _T_1830 : @[sequencer-master.scala 161:86] + _T_3[tail][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_1831 = or(_T_889[7], _T_1066[7]) @[sequencer-master.scala 161:31] + node _T_1832 = or(_T_1831, _T_1243[7]) @[sequencer-master.scala 161:49] + node _T_1833 = or(_T_1832, _T_1420[7]) @[sequencer-master.scala 161:67] + when _T_1833 : @[sequencer-master.scala 161:86] + _T_3[tail][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + when _T_1597[0] : @[sequencer-master.scala 168:32] + _T_4[tail][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[1] : @[sequencer-master.scala 168:32] + _T_4[tail][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[2] : @[sequencer-master.scala 168:32] + _T_4[tail][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[3] : @[sequencer-master.scala 168:32] + _T_4[tail][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[4] : @[sequencer-master.scala 168:32] + _T_4[tail][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[5] : @[sequencer-master.scala 168:32] + _T_4[tail][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[6] : @[sequencer-master.scala 168:32] + _T_4[tail][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[7] : @[sequencer-master.scala 168:32] + _T_4[tail][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + e[tail].rports <= _T_1615 @[sequencer-master.scala 230:21] + e[tail].wport.sram <= UInt<1>("h00") @[sequencer-master.scala 231:25] + e[tail].wport.pred <= UInt<1>("h00") @[sequencer-master.scala 232:25] + node _T_1834 = add(UInt<4>("h00"), _T_1615) @[sequencer-master.scala 247:46] + node _T_1835 = tail(_T_1834, 1) @[sequencer-master.scala 247:46] + node _T_1836 = add(_T_1835, UInt<1>("h01")) @[sequencer-master.scala 247:56] + node _T_1837 = tail(_T_1836, 1) @[sequencer-master.scala 247:56] + node _T_1838 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1839 = eq(io.op.bits.base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1840 = and(_T_1838, _T_1839) @[types-vxu.scala 120:37] + when _T_1840 : @[sequencer-master.scala 235:47] + e[tail].wport.sram <= _T_1837 @[sequencer-master.scala 235:65] + skip @[sequencer-master.scala 235:47] + when io.op.bits.base.vd.pred : @[sequencer-master.scala 236:45] + e[tail].wport.pred <= _T_1837 @[sequencer-master.scala 236:63] + skip @[sequencer-master.scala 236:45] + _T_1641 <= UInt<1>("h01") @[sequencer-master.scala 265:41] + _T_1643 <= _T_1645 @[sequencer-master.scala 265:66] + skip @[sequencer-master.scala 641:41] + when io.op.bits.active.vimul : @[sequencer-master.scala 642:40] + v[tail] <= UInt<1>("h01") @[sequencer-master.scala 267:35] + e[tail].rate <= UInt<1>("h00") @[sequencer-master.scala 271:19] + e[tail].base.vp.valid <= UInt<1>("h00") @[sequencer-master.scala 272:28] + e[tail].base.vs1.valid <= UInt<1>("h00") @[sequencer-master.scala 273:29] + e[tail].base.vs2.valid <= UInt<1>("h00") @[sequencer-master.scala 274:29] + e[tail].base.vs3.valid <= UInt<1>("h00") @[sequencer-master.scala 275:29] + e[tail].base.vd.valid <= UInt<1>("h00") @[sequencer-master.scala 276:28] + _T_1[tail] <= UInt<1>("h01") @[sequencer-master.scala 188:42] + _T_2[tail][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + e[tail].last <= UInt<1>("h00") @[sequencer-master.scala 283:19] + io.master.update.valid[tail] <= UInt<1>("h01") @[sequencer-master.scala 284:35] + e[tail].active.vimu <= UInt<1>("h01") @[sequencer-master.scala 288:26] + e[tail].fn.union <= io.op.bits.fn.union @[sequencer-master.scala 289:23] + when io.op.bits.base.vp.valid : @[sequencer-master.scala 320:41] + e[tail].base.vp <- io.op.bits.base.vp @[sequencer-master.scala 321:24] + io.master.update.reg[tail].vp.id <= io.op.bits.reg.vp.id @[sequencer-master.scala 322:41] + skip @[sequencer-master.scala 320:41] + when _T_181[0] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[1] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[2] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[3] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[4] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[5] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[6] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[7] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when io.op.bits.base.vs1.valid : @[sequencer-master.scala 328:47] + e[tail].base.vs1 <- io.op.bits.base.vs1 @[sequencer-master.scala 329:29] + io.master.update.reg[tail].vs1.id <= io.op.bits.reg.vs1.id @[sequencer-master.scala 330:47] + node _T_1841 = eq(io.op.bits.base.vs1.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1842 = and(_T_1841, io.op.bits.base.vs1.scalar) @[types-vxu.scala 119:37] + when _T_1842 : @[sequencer-master.scala 331:55] + e[tail].sreg.ss1 <= io.op.bits.sreg.ss1 @[sequencer-master.scala 332:31] + skip @[sequencer-master.scala 331:55] + skip @[sequencer-master.scala 328:47] + when _T_358[0] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[1] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[2] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[3] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[4] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[5] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[6] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[7] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when io.op.bits.base.vs2.valid : @[sequencer-master.scala 328:47] + e[tail].base.vs2 <- io.op.bits.base.vs2 @[sequencer-master.scala 329:29] + io.master.update.reg[tail].vs2.id <= io.op.bits.reg.vs2.id @[sequencer-master.scala 330:47] + node _T_1843 = eq(io.op.bits.base.vs2.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1844 = and(_T_1843, io.op.bits.base.vs2.scalar) @[types-vxu.scala 119:37] + when _T_1844 : @[sequencer-master.scala 331:55] + e[tail].sreg.ss2 <= io.op.bits.sreg.ss2 @[sequencer-master.scala 332:31] + skip @[sequencer-master.scala 331:55] + skip @[sequencer-master.scala 328:47] + when _T_535[0] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[1] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[2] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[3] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[4] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[5] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[6] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[7] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + node _T_1845 = eq(io.op.bits.base.vd.valid, UInt<1>("h00")) @[sequencer-master.scala 361:16] + node _T_1846 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1847 = and(_T_1846, io.op.bits.base.vd.scalar) @[types-vxu.scala 119:37] + node _T_1848 = eq(_T_1847, UInt<1>("h00")) @[sequencer-master.scala 361:45] + node _T_1849 = or(_T_1845, _T_1848) @[sequencer-master.scala 361:42] + node _T_1850 = bits(reset, 0, 0) @[sequencer-master.scala 361:15] + node _T_1851 = or(_T_1849, _T_1850) @[sequencer-master.scala 361:15] + node _T_1852 = eq(_T_1851, UInt<1>("h00")) @[sequencer-master.scala 361:15] + when _T_1852 : @[sequencer-master.scala 361:15] + printf(clock, UInt<1>(1), "Assertion failed: iwindow.set.vd: vd should always be vector\n at sequencer-master.scala:361 assert(!io.op.bits.base.vd.valid || !io.op.bits.base.vd.is_scalar(), \"iwindow.set.vd: vd should always be vector\")\n") @[sequencer-master.scala 361:15] + stop(clock, UInt<1>(1), 1) @[sequencer-master.scala 361:15] + skip @[sequencer-master.scala 361:15] + when io.op.bits.base.vd.valid : @[sequencer-master.scala 362:41] + e[tail].base.vd <- io.op.bits.base.vd @[sequencer-master.scala 363:24] + io.master.update.reg[tail].vd.id <= io.op.bits.reg.vd.id @[sequencer-master.scala 364:41] + skip @[sequencer-master.scala 362:41] + node _T_1853 = or(_T_889[0], _T_1066[0]) @[sequencer-master.scala 161:31] + node _T_1854 = or(_T_1853, _T_1243[0]) @[sequencer-master.scala 161:49] + node _T_1855 = or(_T_1854, _T_1420[0]) @[sequencer-master.scala 161:67] + when _T_1855 : @[sequencer-master.scala 161:86] + _T_3[tail][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_1856 = or(_T_889[1], _T_1066[1]) @[sequencer-master.scala 161:31] + node _T_1857 = or(_T_1856, _T_1243[1]) @[sequencer-master.scala 161:49] + node _T_1858 = or(_T_1857, _T_1420[1]) @[sequencer-master.scala 161:67] + when _T_1858 : @[sequencer-master.scala 161:86] + _T_3[tail][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_1859 = or(_T_889[2], _T_1066[2]) @[sequencer-master.scala 161:31] + node _T_1860 = or(_T_1859, _T_1243[2]) @[sequencer-master.scala 161:49] + node _T_1861 = or(_T_1860, _T_1420[2]) @[sequencer-master.scala 161:67] + when _T_1861 : @[sequencer-master.scala 161:86] + _T_3[tail][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_1862 = or(_T_889[3], _T_1066[3]) @[sequencer-master.scala 161:31] + node _T_1863 = or(_T_1862, _T_1243[3]) @[sequencer-master.scala 161:49] + node _T_1864 = or(_T_1863, _T_1420[3]) @[sequencer-master.scala 161:67] + when _T_1864 : @[sequencer-master.scala 161:86] + _T_3[tail][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_1865 = or(_T_889[4], _T_1066[4]) @[sequencer-master.scala 161:31] + node _T_1866 = or(_T_1865, _T_1243[4]) @[sequencer-master.scala 161:49] + node _T_1867 = or(_T_1866, _T_1420[4]) @[sequencer-master.scala 161:67] + when _T_1867 : @[sequencer-master.scala 161:86] + _T_3[tail][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_1868 = or(_T_889[5], _T_1066[5]) @[sequencer-master.scala 161:31] + node _T_1869 = or(_T_1868, _T_1243[5]) @[sequencer-master.scala 161:49] + node _T_1870 = or(_T_1869, _T_1420[5]) @[sequencer-master.scala 161:67] + when _T_1870 : @[sequencer-master.scala 161:86] + _T_3[tail][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_1871 = or(_T_889[6], _T_1066[6]) @[sequencer-master.scala 161:31] + node _T_1872 = or(_T_1871, _T_1243[6]) @[sequencer-master.scala 161:49] + node _T_1873 = or(_T_1872, _T_1420[6]) @[sequencer-master.scala 161:67] + when _T_1873 : @[sequencer-master.scala 161:86] + _T_3[tail][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_1874 = or(_T_889[7], _T_1066[7]) @[sequencer-master.scala 161:31] + node _T_1875 = or(_T_1874, _T_1243[7]) @[sequencer-master.scala 161:49] + node _T_1876 = or(_T_1875, _T_1420[7]) @[sequencer-master.scala 161:67] + when _T_1876 : @[sequencer-master.scala 161:86] + _T_3[tail][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + when _T_1597[0] : @[sequencer-master.scala 168:32] + _T_4[tail][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[1] : @[sequencer-master.scala 168:32] + _T_4[tail][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[2] : @[sequencer-master.scala 168:32] + _T_4[tail][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[3] : @[sequencer-master.scala 168:32] + _T_4[tail][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[4] : @[sequencer-master.scala 168:32] + _T_4[tail][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[5] : @[sequencer-master.scala 168:32] + _T_4[tail][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[6] : @[sequencer-master.scala 168:32] + _T_4[tail][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[7] : @[sequencer-master.scala 168:32] + _T_4[tail][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + e[tail].rports <= _T_1615 @[sequencer-master.scala 230:21] + e[tail].wport.sram <= UInt<1>("h00") @[sequencer-master.scala 231:25] + e[tail].wport.pred <= UInt<1>("h00") @[sequencer-master.scala 232:25] + node _T_1877 = add(UInt<4>("h00"), _T_1615) @[sequencer-master.scala 247:46] + node _T_1878 = tail(_T_1877, 1) @[sequencer-master.scala 247:46] + node _T_1879 = add(_T_1878, UInt<3>("h04")) @[sequencer-master.scala 247:56] + node _T_1880 = tail(_T_1879, 1) @[sequencer-master.scala 247:56] + node _T_1881 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_1882 = eq(io.op.bits.base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_1883 = and(_T_1881, _T_1882) @[types-vxu.scala 120:37] + when _T_1883 : @[sequencer-master.scala 235:47] + e[tail].wport.sram <= _T_1880 @[sequencer-master.scala 235:65] + skip @[sequencer-master.scala 235:47] + when io.op.bits.base.vd.pred : @[sequencer-master.scala 236:45] + e[tail].wport.pred <= _T_1880 @[sequencer-master.scala 236:63] + skip @[sequencer-master.scala 236:45] + _T_1641 <= UInt<1>("h01") @[sequencer-master.scala 265:41] + _T_1643 <= _T_1645 @[sequencer-master.scala 265:66] + skip @[sequencer-master.scala 642:40] + when io.op.bits.active.vidiv : @[sequencer-master.scala 643:40] + v[tail] <= UInt<1>("h01") @[sequencer-master.scala 267:35] + e[tail].rate <= UInt<1>("h00") @[sequencer-master.scala 271:19] + e[tail].base.vp.valid <= UInt<1>("h00") @[sequencer-master.scala 272:28] + e[tail].base.vs1.valid <= UInt<1>("h00") @[sequencer-master.scala 273:29] + e[tail].base.vs2.valid <= UInt<1>("h00") @[sequencer-master.scala 274:29] + e[tail].base.vs3.valid <= UInt<1>("h00") @[sequencer-master.scala 275:29] + e[tail].base.vd.valid <= UInt<1>("h00") @[sequencer-master.scala 276:28] + _T_1[tail] <= UInt<1>("h01") @[sequencer-master.scala 188:42] + _T_2[tail][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + e[tail].last <= UInt<1>("h00") @[sequencer-master.scala 283:19] + io.master.update.valid[tail] <= UInt<1>("h01") @[sequencer-master.scala 284:35] + e[tail].active.vqu <= UInt<1>("h01") @[sequencer-master.scala 288:26] + node _T_1884 = or(io.op.bits.active.vidiv, io.op.bits.active.vfdiv) @[sequencer-master.scala 298:31] + node _T_1885 = or(_T_1884, io.op.bits.active.vrpred) @[sequencer-master.scala 298:49] + node _T_1886 = or(_T_1885, io.op.bits.active.vrfirst) @[sequencer-master.scala 298:68] + node _T_1887 = bits(reset, 0, 0) @[sequencer-master.scala 298:15] + node _T_1888 = or(_T_1886, _T_1887) @[sequencer-master.scala 298:15] + node _T_1889 = eq(_T_1888, UInt<1>("h00")) @[sequencer-master.scala 298:15] + when _T_1889 : @[sequencer-master.scala 298:15] + printf(clock, UInt<1>(1), "Assertion failed: vqu should only be issued for idiv/fdiv/rpred/rfirst\n at sequencer-master.scala:298 assert(d.active.vidiv || d.active.vfdiv || d.active.vrpred || d.active.vrfirst,\n") @[sequencer-master.scala 298:15] + stop(clock, UInt<1>(1), 1) @[sequencer-master.scala 298:15] + skip @[sequencer-master.scala 298:15] + wire _T_1890 : {fp : UInt<2>, rm : UInt<3>, op : UInt<1>} @[types-vxu.scala 96:47] + _T_1890 is invalid @[types-vxu.scala 96:47] + wire _T_1891 : UInt<6> + _T_1891 is invalid + _T_1891 <= io.op.bits.fn.union + node _T_1892 = bits(_T_1891, 0, 0) @[types-vxu.scala 96:47] + _T_1890.op <= _T_1892 @[types-vxu.scala 96:47] + node _T_1893 = bits(_T_1891, 3, 1) @[types-vxu.scala 96:47] + _T_1890.rm <= _T_1893 @[types-vxu.scala 96:47] + node _T_1894 = bits(_T_1891, 5, 4) @[types-vxu.scala 96:47] + _T_1890.fp <= _T_1894 @[types-vxu.scala 96:47] + node _T_1895 = eq(_T_1890.op, UInt<1>("h00")) @[types-vxu.scala 54:51] + node _T_1896 = and(io.op.bits.active.vfdiv, _T_1895) @[sequencer-master.scala 300:46] + node _T_1897 = or(io.op.bits.active.vidiv, _T_1896) @[sequencer-master.scala 300:28] + node _T_1898 = or(io.op.bits.active.vidiv, io.op.bits.active.vfdiv) @[sequencer-master.scala 301:28] + node _T_1899 = or(_T_1898, io.op.bits.active.vrfirst) @[sequencer-master.scala 301:46] + node _T_1900 = cat(_T_1897, _T_1899) @[Cat.scala 30:58] + e[tail].fn.union <= _T_1900 @[sequencer-master.scala 289:23] + when io.op.bits.base.vp.valid : @[sequencer-master.scala 320:41] + e[tail].base.vp <- io.op.bits.base.vp @[sequencer-master.scala 321:24] + io.master.update.reg[tail].vp.id <= io.op.bits.reg.vp.id @[sequencer-master.scala 322:41] + skip @[sequencer-master.scala 320:41] + when _T_181[0] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[1] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[2] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[3] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[4] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[5] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[6] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[7] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when io.op.bits.base.vs1.valid : @[sequencer-master.scala 328:47] + e[tail].base.vs1 <- io.op.bits.base.vs1 @[sequencer-master.scala 329:29] + io.master.update.reg[tail].vs1.id <= io.op.bits.reg.vs1.id @[sequencer-master.scala 330:47] + node _T_1901 = eq(io.op.bits.base.vs1.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1902 = and(_T_1901, io.op.bits.base.vs1.scalar) @[types-vxu.scala 119:37] + when _T_1902 : @[sequencer-master.scala 331:55] + e[tail].sreg.ss1 <= io.op.bits.sreg.ss1 @[sequencer-master.scala 332:31] + skip @[sequencer-master.scala 331:55] + skip @[sequencer-master.scala 328:47] + when _T_358[0] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[1] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[2] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[3] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[4] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[5] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[6] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[7] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when io.op.bits.base.vs2.valid : @[sequencer-master.scala 328:47] + e[tail].base.vs2 <- io.op.bits.base.vs2 @[sequencer-master.scala 329:29] + io.master.update.reg[tail].vs2.id <= io.op.bits.reg.vs2.id @[sequencer-master.scala 330:47] + node _T_1903 = eq(io.op.bits.base.vs2.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1904 = and(_T_1903, io.op.bits.base.vs2.scalar) @[types-vxu.scala 119:37] + when _T_1904 : @[sequencer-master.scala 331:55] + e[tail].sreg.ss2 <= io.op.bits.sreg.ss2 @[sequencer-master.scala 332:31] + skip @[sequencer-master.scala 331:55] + skip @[sequencer-master.scala 328:47] + when _T_535[0] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[1] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[2] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[3] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[4] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[5] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[6] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[7] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + e[tail].rports <= _T_1615 @[sequencer-master.scala 230:21] + e[tail].wport.sram <= UInt<1>("h00") @[sequencer-master.scala 231:25] + e[tail].wport.pred <= UInt<1>("h00") @[sequencer-master.scala 232:25] + node _T_1905 = or(_T_889[0], _T_1066[0]) @[sequencer-master.scala 161:31] + node _T_1906 = or(_T_1905, _T_1243[0]) @[sequencer-master.scala 161:49] + node _T_1907 = or(_T_1906, _T_1420[0]) @[sequencer-master.scala 161:67] + when _T_1907 : @[sequencer-master.scala 161:86] + _T_3[tail][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_1908 = or(_T_889[1], _T_1066[1]) @[sequencer-master.scala 161:31] + node _T_1909 = or(_T_1908, _T_1243[1]) @[sequencer-master.scala 161:49] + node _T_1910 = or(_T_1909, _T_1420[1]) @[sequencer-master.scala 161:67] + when _T_1910 : @[sequencer-master.scala 161:86] + _T_3[tail][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_1911 = or(_T_889[2], _T_1066[2]) @[sequencer-master.scala 161:31] + node _T_1912 = or(_T_1911, _T_1243[2]) @[sequencer-master.scala 161:49] + node _T_1913 = or(_T_1912, _T_1420[2]) @[sequencer-master.scala 161:67] + when _T_1913 : @[sequencer-master.scala 161:86] + _T_3[tail][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_1914 = or(_T_889[3], _T_1066[3]) @[sequencer-master.scala 161:31] + node _T_1915 = or(_T_1914, _T_1243[3]) @[sequencer-master.scala 161:49] + node _T_1916 = or(_T_1915, _T_1420[3]) @[sequencer-master.scala 161:67] + when _T_1916 : @[sequencer-master.scala 161:86] + _T_3[tail][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_1917 = or(_T_889[4], _T_1066[4]) @[sequencer-master.scala 161:31] + node _T_1918 = or(_T_1917, _T_1243[4]) @[sequencer-master.scala 161:49] + node _T_1919 = or(_T_1918, _T_1420[4]) @[sequencer-master.scala 161:67] + when _T_1919 : @[sequencer-master.scala 161:86] + _T_3[tail][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_1920 = or(_T_889[5], _T_1066[5]) @[sequencer-master.scala 161:31] + node _T_1921 = or(_T_1920, _T_1243[5]) @[sequencer-master.scala 161:49] + node _T_1922 = or(_T_1921, _T_1420[5]) @[sequencer-master.scala 161:67] + when _T_1922 : @[sequencer-master.scala 161:86] + _T_3[tail][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_1923 = or(_T_889[6], _T_1066[6]) @[sequencer-master.scala 161:31] + node _T_1924 = or(_T_1923, _T_1243[6]) @[sequencer-master.scala 161:49] + node _T_1925 = or(_T_1924, _T_1420[6]) @[sequencer-master.scala 161:67] + when _T_1925 : @[sequencer-master.scala 161:86] + _T_3[tail][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_1926 = or(_T_889[7], _T_1066[7]) @[sequencer-master.scala 161:31] + node _T_1927 = or(_T_1926, _T_1243[7]) @[sequencer-master.scala 161:49] + node _T_1928 = or(_T_1927, _T_1420[7]) @[sequencer-master.scala 161:67] + when _T_1928 : @[sequencer-master.scala 161:86] + _T_3[tail][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + when _T_1597[0] : @[sequencer-master.scala 168:32] + _T_4[tail][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[1] : @[sequencer-master.scala 168:32] + _T_4[tail][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[2] : @[sequencer-master.scala 168:32] + _T_4[tail][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[3] : @[sequencer-master.scala 168:32] + _T_4[tail][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[4] : @[sequencer-master.scala 168:32] + _T_4[tail][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[5] : @[sequencer-master.scala 168:32] + _T_4[tail][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[6] : @[sequencer-master.scala 168:32] + _T_4[tail][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[7] : @[sequencer-master.scala 168:32] + _T_4[tail][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + v[_T_1645] <= UInt<1>("h01") @[sequencer-master.scala 267:35] + e[_T_1645].rate <= UInt<1>("h00") @[sequencer-master.scala 271:19] + e[_T_1645].base.vp.valid <= UInt<1>("h00") @[sequencer-master.scala 272:28] + e[_T_1645].base.vs1.valid <= UInt<1>("h00") @[sequencer-master.scala 273:29] + e[_T_1645].base.vs2.valid <= UInt<1>("h00") @[sequencer-master.scala 274:29] + e[_T_1645].base.vs3.valid <= UInt<1>("h00") @[sequencer-master.scala 275:29] + e[_T_1645].base.vd.valid <= UInt<1>("h00") @[sequencer-master.scala 276:28] + _T_1[_T_1645] <= UInt<1>("h01") @[sequencer-master.scala 188:42] + _T_2[_T_1645][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1645][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1645][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1645][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1645][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1645][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1645][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1645][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1645][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1645][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1645][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1645][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1645][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1645][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1645][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1645][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1645][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1645][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1645][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1645][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1645][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1645][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1645][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1645][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + e[_T_1645].last <= UInt<1>("h00") @[sequencer-master.scala 283:19] + io.master.update.valid[_T_1645] <= UInt<1>("h01") @[sequencer-master.scala 284:35] + e[_T_1645].active.vidu <= UInt<1>("h01") @[sequencer-master.scala 288:26] + e[_T_1645].fn.union <= io.op.bits.fn.union @[sequencer-master.scala 289:23] + node _T_1929 = eq(io.op.bits.base.vd.valid, UInt<1>("h00")) @[sequencer-master.scala 361:16] + node _T_1930 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1931 = and(_T_1930, io.op.bits.base.vd.scalar) @[types-vxu.scala 119:37] + node _T_1932 = eq(_T_1931, UInt<1>("h00")) @[sequencer-master.scala 361:45] + node _T_1933 = or(_T_1929, _T_1932) @[sequencer-master.scala 361:42] + node _T_1934 = bits(reset, 0, 0) @[sequencer-master.scala 361:15] + node _T_1935 = or(_T_1933, _T_1934) @[sequencer-master.scala 361:15] + node _T_1936 = eq(_T_1935, UInt<1>("h00")) @[sequencer-master.scala 361:15] + when _T_1936 : @[sequencer-master.scala 361:15] + printf(clock, UInt<1>(1), "Assertion failed: iwindow.set.vd: vd should always be vector\n at sequencer-master.scala:361 assert(!io.op.bits.base.vd.valid || !io.op.bits.base.vd.is_scalar(), \"iwindow.set.vd: vd should always be vector\")\n") @[sequencer-master.scala 361:15] + stop(clock, UInt<1>(1), 1) @[sequencer-master.scala 361:15] + skip @[sequencer-master.scala 361:15] + when io.op.bits.base.vd.valid : @[sequencer-master.scala 362:41] + e[_T_1645].base.vd <- io.op.bits.base.vd @[sequencer-master.scala 363:24] + io.master.update.reg[_T_1645].vd.id <= io.op.bits.reg.vd.id @[sequencer-master.scala 364:41] + skip @[sequencer-master.scala 362:41] + node _T_1937 = or(_T_889[0], _T_1066[0]) @[sequencer-master.scala 161:31] + node _T_1938 = or(_T_1937, _T_1243[0]) @[sequencer-master.scala 161:49] + node _T_1939 = or(_T_1938, _T_1420[0]) @[sequencer-master.scala 161:67] + when _T_1939 : @[sequencer-master.scala 161:86] + _T_3[_T_1645][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_1940 = or(_T_889[1], _T_1066[1]) @[sequencer-master.scala 161:31] + node _T_1941 = or(_T_1940, _T_1243[1]) @[sequencer-master.scala 161:49] + node _T_1942 = or(_T_1941, _T_1420[1]) @[sequencer-master.scala 161:67] + when _T_1942 : @[sequencer-master.scala 161:86] + _T_3[_T_1645][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_1943 = or(_T_889[2], _T_1066[2]) @[sequencer-master.scala 161:31] + node _T_1944 = or(_T_1943, _T_1243[2]) @[sequencer-master.scala 161:49] + node _T_1945 = or(_T_1944, _T_1420[2]) @[sequencer-master.scala 161:67] + when _T_1945 : @[sequencer-master.scala 161:86] + _T_3[_T_1645][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_1946 = or(_T_889[3], _T_1066[3]) @[sequencer-master.scala 161:31] + node _T_1947 = or(_T_1946, _T_1243[3]) @[sequencer-master.scala 161:49] + node _T_1948 = or(_T_1947, _T_1420[3]) @[sequencer-master.scala 161:67] + when _T_1948 : @[sequencer-master.scala 161:86] + _T_3[_T_1645][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_1949 = or(_T_889[4], _T_1066[4]) @[sequencer-master.scala 161:31] + node _T_1950 = or(_T_1949, _T_1243[4]) @[sequencer-master.scala 161:49] + node _T_1951 = or(_T_1950, _T_1420[4]) @[sequencer-master.scala 161:67] + when _T_1951 : @[sequencer-master.scala 161:86] + _T_3[_T_1645][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_1952 = or(_T_889[5], _T_1066[5]) @[sequencer-master.scala 161:31] + node _T_1953 = or(_T_1952, _T_1243[5]) @[sequencer-master.scala 161:49] + node _T_1954 = or(_T_1953, _T_1420[5]) @[sequencer-master.scala 161:67] + when _T_1954 : @[sequencer-master.scala 161:86] + _T_3[_T_1645][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_1955 = or(_T_889[6], _T_1066[6]) @[sequencer-master.scala 161:31] + node _T_1956 = or(_T_1955, _T_1243[6]) @[sequencer-master.scala 161:49] + node _T_1957 = or(_T_1956, _T_1420[6]) @[sequencer-master.scala 161:67] + when _T_1957 : @[sequencer-master.scala 161:86] + _T_3[_T_1645][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_1958 = or(_T_889[7], _T_1066[7]) @[sequencer-master.scala 161:31] + node _T_1959 = or(_T_1958, _T_1243[7]) @[sequencer-master.scala 161:49] + node _T_1960 = or(_T_1959, _T_1420[7]) @[sequencer-master.scala 161:67] + when _T_1960 : @[sequencer-master.scala 161:86] + _T_3[_T_1645][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + when _T_1597[0] : @[sequencer-master.scala 168:32] + _T_4[_T_1645][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[1] : @[sequencer-master.scala 168:32] + _T_4[_T_1645][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[2] : @[sequencer-master.scala 168:32] + _T_4[_T_1645][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[3] : @[sequencer-master.scala 168:32] + _T_4[_T_1645][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[4] : @[sequencer-master.scala 168:32] + _T_4[_T_1645][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[5] : @[sequencer-master.scala 168:32] + _T_4[_T_1645][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[6] : @[sequencer-master.scala 168:32] + _T_4[_T_1645][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[7] : @[sequencer-master.scala 168:32] + _T_4[_T_1645][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + e[_T_1645].rports <= UInt<1>("h00") @[sequencer-master.scala 230:21] + e[_T_1645].wport.sram <= UInt<1>("h00") @[sequencer-master.scala 231:25] + e[_T_1645].wport.pred <= UInt<1>("h00") @[sequencer-master.scala 232:25] + _T_1641 <= UInt<1>("h01") @[sequencer-master.scala 265:41] + _T_1643 <= _T_1647 @[sequencer-master.scala 265:66] + skip @[sequencer-master.scala 643:40] + when io.op.bits.active.vfma : @[sequencer-master.scala 644:39] + wire _T_1961 : {fp : UInt<2>, rm : UInt<3>, op : UInt<3>} @[types-vxu.scala 95:47] + _T_1961 is invalid @[types-vxu.scala 95:47] + wire _T_1962 : UInt<8> + _T_1962 is invalid + _T_1962 <= io.op.bits.fn.union + node _T_1963 = bits(_T_1962, 2, 0) @[types-vxu.scala 95:47] + _T_1961.op <= _T_1963 @[types-vxu.scala 95:47] + node _T_1964 = bits(_T_1962, 5, 3) @[types-vxu.scala 95:47] + _T_1961.rm <= _T_1964 @[types-vxu.scala 95:47] + node _T_1965 = bits(_T_1962, 7, 6) @[types-vxu.scala 95:47] + _T_1961.fp <= _T_1965 @[types-vxu.scala 95:47] + node _T_1966 = eq(_T_1961.fp, UInt<2>("h01")) @[types-vxu.scala 53:51] + node _T_1967 = eq(_T_1961.fp, UInt<2>("h00")) @[types-vxu.scala 53:51] + node _T_1968 = eq(_T_1961.fp, UInt<2>("h02")) @[types-vxu.scala 53:51] + v[tail] <= UInt<1>("h01") @[sequencer-master.scala 267:35] + e[tail].rate <= UInt<1>("h00") @[sequencer-master.scala 271:19] + e[tail].base.vp.valid <= UInt<1>("h00") @[sequencer-master.scala 272:28] + e[tail].base.vs1.valid <= UInt<1>("h00") @[sequencer-master.scala 273:29] + e[tail].base.vs2.valid <= UInt<1>("h00") @[sequencer-master.scala 274:29] + e[tail].base.vs3.valid <= UInt<1>("h00") @[sequencer-master.scala 275:29] + e[tail].base.vd.valid <= UInt<1>("h00") @[sequencer-master.scala 276:28] + _T_1[tail] <= UInt<1>("h01") @[sequencer-master.scala 188:42] + _T_2[tail][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + e[tail].last <= UInt<1>("h00") @[sequencer-master.scala 283:19] + io.master.update.valid[tail] <= UInt<1>("h01") @[sequencer-master.scala 284:35] + e[tail].active.vfmu <= UInt<1>("h01") @[sequencer-master.scala 288:26] + e[tail].fn.union <= io.op.bits.fn.union @[sequencer-master.scala 289:23] + when io.op.bits.base.vp.valid : @[sequencer-master.scala 320:41] + e[tail].base.vp <- io.op.bits.base.vp @[sequencer-master.scala 321:24] + io.master.update.reg[tail].vp.id <= io.op.bits.reg.vp.id @[sequencer-master.scala 322:41] + skip @[sequencer-master.scala 320:41] + when _T_181[0] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[1] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[2] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[3] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[4] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[5] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[6] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[7] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when io.op.bits.base.vs1.valid : @[sequencer-master.scala 328:47] + e[tail].base.vs1 <- io.op.bits.base.vs1 @[sequencer-master.scala 329:29] + io.master.update.reg[tail].vs1.id <= io.op.bits.reg.vs1.id @[sequencer-master.scala 330:47] + node _T_1969 = eq(io.op.bits.base.vs1.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1970 = and(_T_1969, io.op.bits.base.vs1.scalar) @[types-vxu.scala 119:37] + when _T_1970 : @[sequencer-master.scala 331:55] + e[tail].sreg.ss1 <= io.op.bits.sreg.ss1 @[sequencer-master.scala 332:31] + skip @[sequencer-master.scala 331:55] + skip @[sequencer-master.scala 328:47] + when _T_358[0] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[1] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[2] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[3] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[4] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[5] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[6] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[7] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when io.op.bits.base.vs2.valid : @[sequencer-master.scala 328:47] + e[tail].base.vs2 <- io.op.bits.base.vs2 @[sequencer-master.scala 329:29] + io.master.update.reg[tail].vs2.id <= io.op.bits.reg.vs2.id @[sequencer-master.scala 330:47] + node _T_1971 = eq(io.op.bits.base.vs2.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1972 = and(_T_1971, io.op.bits.base.vs2.scalar) @[types-vxu.scala 119:37] + when _T_1972 : @[sequencer-master.scala 331:55] + e[tail].sreg.ss2 <= io.op.bits.sreg.ss2 @[sequencer-master.scala 332:31] + skip @[sequencer-master.scala 331:55] + skip @[sequencer-master.scala 328:47] + when _T_535[0] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[1] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[2] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[3] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[4] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[5] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[6] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[7] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when io.op.bits.base.vs3.valid : @[sequencer-master.scala 328:47] + e[tail].base.vs3 <- io.op.bits.base.vs3 @[sequencer-master.scala 329:29] + io.master.update.reg[tail].vs3.id <= io.op.bits.reg.vs3.id @[sequencer-master.scala 330:47] + node _T_1973 = eq(io.op.bits.base.vs3.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1974 = and(_T_1973, io.op.bits.base.vs3.scalar) @[types-vxu.scala 119:37] + when _T_1974 : @[sequencer-master.scala 331:55] + e[tail].sreg.ss3 <= io.op.bits.sreg.ss3 @[sequencer-master.scala 332:31] + skip @[sequencer-master.scala 331:55] + skip @[sequencer-master.scala 328:47] + when _T_712[0] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_712[1] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_712[2] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_712[3] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_712[4] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_712[5] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_712[6] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_712[7] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + node _T_1975 = eq(io.op.bits.base.vd.valid, UInt<1>("h00")) @[sequencer-master.scala 361:16] + node _T_1976 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_1977 = and(_T_1976, io.op.bits.base.vd.scalar) @[types-vxu.scala 119:37] + node _T_1978 = eq(_T_1977, UInt<1>("h00")) @[sequencer-master.scala 361:45] + node _T_1979 = or(_T_1975, _T_1978) @[sequencer-master.scala 361:42] + node _T_1980 = bits(reset, 0, 0) @[sequencer-master.scala 361:15] + node _T_1981 = or(_T_1979, _T_1980) @[sequencer-master.scala 361:15] + node _T_1982 = eq(_T_1981, UInt<1>("h00")) @[sequencer-master.scala 361:15] + when _T_1982 : @[sequencer-master.scala 361:15] + printf(clock, UInt<1>(1), "Assertion failed: iwindow.set.vd: vd should always be vector\n at sequencer-master.scala:361 assert(!io.op.bits.base.vd.valid || !io.op.bits.base.vd.is_scalar(), \"iwindow.set.vd: vd should always be vector\")\n") @[sequencer-master.scala 361:15] + stop(clock, UInt<1>(1), 1) @[sequencer-master.scala 361:15] + skip @[sequencer-master.scala 361:15] + when io.op.bits.base.vd.valid : @[sequencer-master.scala 362:41] + e[tail].base.vd <- io.op.bits.base.vd @[sequencer-master.scala 363:24] + io.master.update.reg[tail].vd.id <= io.op.bits.reg.vd.id @[sequencer-master.scala 364:41] + skip @[sequencer-master.scala 362:41] + node _T_1983 = or(_T_889[0], _T_1066[0]) @[sequencer-master.scala 161:31] + node _T_1984 = or(_T_1983, _T_1243[0]) @[sequencer-master.scala 161:49] + node _T_1985 = or(_T_1984, _T_1420[0]) @[sequencer-master.scala 161:67] + when _T_1985 : @[sequencer-master.scala 161:86] + _T_3[tail][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_1986 = or(_T_889[1], _T_1066[1]) @[sequencer-master.scala 161:31] + node _T_1987 = or(_T_1986, _T_1243[1]) @[sequencer-master.scala 161:49] + node _T_1988 = or(_T_1987, _T_1420[1]) @[sequencer-master.scala 161:67] + when _T_1988 : @[sequencer-master.scala 161:86] + _T_3[tail][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_1989 = or(_T_889[2], _T_1066[2]) @[sequencer-master.scala 161:31] + node _T_1990 = or(_T_1989, _T_1243[2]) @[sequencer-master.scala 161:49] + node _T_1991 = or(_T_1990, _T_1420[2]) @[sequencer-master.scala 161:67] + when _T_1991 : @[sequencer-master.scala 161:86] + _T_3[tail][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_1992 = or(_T_889[3], _T_1066[3]) @[sequencer-master.scala 161:31] + node _T_1993 = or(_T_1992, _T_1243[3]) @[sequencer-master.scala 161:49] + node _T_1994 = or(_T_1993, _T_1420[3]) @[sequencer-master.scala 161:67] + when _T_1994 : @[sequencer-master.scala 161:86] + _T_3[tail][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_1995 = or(_T_889[4], _T_1066[4]) @[sequencer-master.scala 161:31] + node _T_1996 = or(_T_1995, _T_1243[4]) @[sequencer-master.scala 161:49] + node _T_1997 = or(_T_1996, _T_1420[4]) @[sequencer-master.scala 161:67] + when _T_1997 : @[sequencer-master.scala 161:86] + _T_3[tail][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_1998 = or(_T_889[5], _T_1066[5]) @[sequencer-master.scala 161:31] + node _T_1999 = or(_T_1998, _T_1243[5]) @[sequencer-master.scala 161:49] + node _T_2000 = or(_T_1999, _T_1420[5]) @[sequencer-master.scala 161:67] + when _T_2000 : @[sequencer-master.scala 161:86] + _T_3[tail][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2001 = or(_T_889[6], _T_1066[6]) @[sequencer-master.scala 161:31] + node _T_2002 = or(_T_2001, _T_1243[6]) @[sequencer-master.scala 161:49] + node _T_2003 = or(_T_2002, _T_1420[6]) @[sequencer-master.scala 161:67] + when _T_2003 : @[sequencer-master.scala 161:86] + _T_3[tail][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2004 = or(_T_889[7], _T_1066[7]) @[sequencer-master.scala 161:31] + node _T_2005 = or(_T_2004, _T_1243[7]) @[sequencer-master.scala 161:49] + node _T_2006 = or(_T_2005, _T_1420[7]) @[sequencer-master.scala 161:67] + when _T_2006 : @[sequencer-master.scala 161:86] + _T_3[tail][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + when _T_1597[0] : @[sequencer-master.scala 168:32] + _T_4[tail][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[1] : @[sequencer-master.scala 168:32] + _T_4[tail][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[2] : @[sequencer-master.scala 168:32] + _T_4[tail][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[3] : @[sequencer-master.scala 168:32] + _T_4[tail][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[4] : @[sequencer-master.scala 168:32] + _T_4[tail][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[5] : @[sequencer-master.scala 168:32] + _T_4[tail][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[6] : @[sequencer-master.scala 168:32] + _T_4[tail][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[7] : @[sequencer-master.scala 168:32] + _T_4[tail][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + node _T_2007 = mux(_T_1966, UInt<3>("h05"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2008 = mux(_T_1967, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2009 = mux(_T_1968, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2010 = or(_T_2007, _T_2008) @[Mux.scala 19:72] + node _T_2011 = or(_T_2010, _T_2009) @[Mux.scala 19:72] + wire _T_2012 : UInt<3> @[Mux.scala 19:72] + _T_2012 <= _T_2011 @[Mux.scala 19:72] + e[tail].rports <= _T_1615 @[sequencer-master.scala 230:21] + e[tail].wport.sram <= UInt<1>("h00") @[sequencer-master.scala 231:25] + e[tail].wport.pred <= UInt<1>("h00") @[sequencer-master.scala 232:25] + node _T_2013 = add(UInt<4>("h00"), _T_1615) @[sequencer-master.scala 247:46] + node _T_2014 = tail(_T_2013, 1) @[sequencer-master.scala 247:46] + node _T_2015 = add(_T_2014, _T_2012) @[sequencer-master.scala 247:56] + node _T_2016 = tail(_T_2015, 1) @[sequencer-master.scala 247:56] + node _T_2017 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_2018 = eq(io.op.bits.base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_2019 = and(_T_2017, _T_2018) @[types-vxu.scala 120:37] + when _T_2019 : @[sequencer-master.scala 235:47] + e[tail].wport.sram <= _T_2016 @[sequencer-master.scala 235:65] + skip @[sequencer-master.scala 235:47] + when io.op.bits.base.vd.pred : @[sequencer-master.scala 236:45] + e[tail].wport.pred <= _T_2016 @[sequencer-master.scala 236:63] + skip @[sequencer-master.scala 236:45] + _T_1641 <= UInt<1>("h01") @[sequencer-master.scala 265:41] + _T_1643 <= _T_1645 @[sequencer-master.scala 265:66] + skip @[sequencer-master.scala 644:39] + when io.op.bits.active.vfdiv : @[sequencer-master.scala 645:40] + v[tail] <= UInt<1>("h01") @[sequencer-master.scala 267:35] + e[tail].rate <= UInt<1>("h00") @[sequencer-master.scala 271:19] + e[tail].base.vp.valid <= UInt<1>("h00") @[sequencer-master.scala 272:28] + e[tail].base.vs1.valid <= UInt<1>("h00") @[sequencer-master.scala 273:29] + e[tail].base.vs2.valid <= UInt<1>("h00") @[sequencer-master.scala 274:29] + e[tail].base.vs3.valid <= UInt<1>("h00") @[sequencer-master.scala 275:29] + e[tail].base.vd.valid <= UInt<1>("h00") @[sequencer-master.scala 276:28] + _T_1[tail] <= UInt<1>("h01") @[sequencer-master.scala 188:42] + _T_2[tail][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + e[tail].last <= UInt<1>("h00") @[sequencer-master.scala 283:19] + io.master.update.valid[tail] <= UInt<1>("h01") @[sequencer-master.scala 284:35] + e[tail].active.vqu <= UInt<1>("h01") @[sequencer-master.scala 288:26] + node _T_2020 = or(io.op.bits.active.vidiv, io.op.bits.active.vfdiv) @[sequencer-master.scala 298:31] + node _T_2021 = or(_T_2020, io.op.bits.active.vrpred) @[sequencer-master.scala 298:49] + node _T_2022 = or(_T_2021, io.op.bits.active.vrfirst) @[sequencer-master.scala 298:68] + node _T_2023 = bits(reset, 0, 0) @[sequencer-master.scala 298:15] + node _T_2024 = or(_T_2022, _T_2023) @[sequencer-master.scala 298:15] + node _T_2025 = eq(_T_2024, UInt<1>("h00")) @[sequencer-master.scala 298:15] + when _T_2025 : @[sequencer-master.scala 298:15] + printf(clock, UInt<1>(1), "Assertion failed: vqu should only be issued for idiv/fdiv/rpred/rfirst\n at sequencer-master.scala:298 assert(d.active.vidiv || d.active.vfdiv || d.active.vrpred || d.active.vrfirst,\n") @[sequencer-master.scala 298:15] + stop(clock, UInt<1>(1), 1) @[sequencer-master.scala 298:15] + skip @[sequencer-master.scala 298:15] + wire _T_2026 : {fp : UInt<2>, rm : UInt<3>, op : UInt<1>} @[types-vxu.scala 96:47] + _T_2026 is invalid @[types-vxu.scala 96:47] + wire _T_2027 : UInt<6> + _T_2027 is invalid + _T_2027 <= io.op.bits.fn.union + node _T_2028 = bits(_T_2027, 0, 0) @[types-vxu.scala 96:47] + _T_2026.op <= _T_2028 @[types-vxu.scala 96:47] + node _T_2029 = bits(_T_2027, 3, 1) @[types-vxu.scala 96:47] + _T_2026.rm <= _T_2029 @[types-vxu.scala 96:47] + node _T_2030 = bits(_T_2027, 5, 4) @[types-vxu.scala 96:47] + _T_2026.fp <= _T_2030 @[types-vxu.scala 96:47] + node _T_2031 = eq(_T_2026.op, UInt<1>("h00")) @[types-vxu.scala 54:51] + node _T_2032 = and(io.op.bits.active.vfdiv, _T_2031) @[sequencer-master.scala 300:46] + node _T_2033 = or(io.op.bits.active.vidiv, _T_2032) @[sequencer-master.scala 300:28] + node _T_2034 = or(io.op.bits.active.vidiv, io.op.bits.active.vfdiv) @[sequencer-master.scala 301:28] + node _T_2035 = or(_T_2034, io.op.bits.active.vrfirst) @[sequencer-master.scala 301:46] + node _T_2036 = cat(_T_2033, _T_2035) @[Cat.scala 30:58] + e[tail].fn.union <= _T_2036 @[sequencer-master.scala 289:23] + when io.op.bits.base.vp.valid : @[sequencer-master.scala 320:41] + e[tail].base.vp <- io.op.bits.base.vp @[sequencer-master.scala 321:24] + io.master.update.reg[tail].vp.id <= io.op.bits.reg.vp.id @[sequencer-master.scala 322:41] + skip @[sequencer-master.scala 320:41] + when _T_181[0] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[1] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[2] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[3] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[4] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[5] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[6] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[7] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when io.op.bits.base.vs1.valid : @[sequencer-master.scala 328:47] + e[tail].base.vs1 <- io.op.bits.base.vs1 @[sequencer-master.scala 329:29] + io.master.update.reg[tail].vs1.id <= io.op.bits.reg.vs1.id @[sequencer-master.scala 330:47] + node _T_2037 = eq(io.op.bits.base.vs1.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_2038 = and(_T_2037, io.op.bits.base.vs1.scalar) @[types-vxu.scala 119:37] + when _T_2038 : @[sequencer-master.scala 331:55] + e[tail].sreg.ss1 <= io.op.bits.sreg.ss1 @[sequencer-master.scala 332:31] + skip @[sequencer-master.scala 331:55] + skip @[sequencer-master.scala 328:47] + when _T_358[0] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[1] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[2] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[3] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[4] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[5] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[6] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[7] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when io.op.bits.base.vs2.valid : @[sequencer-master.scala 328:47] + e[tail].base.vs2 <- io.op.bits.base.vs2 @[sequencer-master.scala 329:29] + io.master.update.reg[tail].vs2.id <= io.op.bits.reg.vs2.id @[sequencer-master.scala 330:47] + node _T_2039 = eq(io.op.bits.base.vs2.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_2040 = and(_T_2039, io.op.bits.base.vs2.scalar) @[types-vxu.scala 119:37] + when _T_2040 : @[sequencer-master.scala 331:55] + e[tail].sreg.ss2 <= io.op.bits.sreg.ss2 @[sequencer-master.scala 332:31] + skip @[sequencer-master.scala 331:55] + skip @[sequencer-master.scala 328:47] + when _T_535[0] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[1] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[2] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[3] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[4] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[5] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[6] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[7] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + e[tail].rports <= _T_1615 @[sequencer-master.scala 230:21] + e[tail].wport.sram <= UInt<1>("h00") @[sequencer-master.scala 231:25] + e[tail].wport.pred <= UInt<1>("h00") @[sequencer-master.scala 232:25] + node _T_2041 = or(_T_889[0], _T_1066[0]) @[sequencer-master.scala 161:31] + node _T_2042 = or(_T_2041, _T_1243[0]) @[sequencer-master.scala 161:49] + node _T_2043 = or(_T_2042, _T_1420[0]) @[sequencer-master.scala 161:67] + when _T_2043 : @[sequencer-master.scala 161:86] + _T_3[tail][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2044 = or(_T_889[1], _T_1066[1]) @[sequencer-master.scala 161:31] + node _T_2045 = or(_T_2044, _T_1243[1]) @[sequencer-master.scala 161:49] + node _T_2046 = or(_T_2045, _T_1420[1]) @[sequencer-master.scala 161:67] + when _T_2046 : @[sequencer-master.scala 161:86] + _T_3[tail][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2047 = or(_T_889[2], _T_1066[2]) @[sequencer-master.scala 161:31] + node _T_2048 = or(_T_2047, _T_1243[2]) @[sequencer-master.scala 161:49] + node _T_2049 = or(_T_2048, _T_1420[2]) @[sequencer-master.scala 161:67] + when _T_2049 : @[sequencer-master.scala 161:86] + _T_3[tail][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2050 = or(_T_889[3], _T_1066[3]) @[sequencer-master.scala 161:31] + node _T_2051 = or(_T_2050, _T_1243[3]) @[sequencer-master.scala 161:49] + node _T_2052 = or(_T_2051, _T_1420[3]) @[sequencer-master.scala 161:67] + when _T_2052 : @[sequencer-master.scala 161:86] + _T_3[tail][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2053 = or(_T_889[4], _T_1066[4]) @[sequencer-master.scala 161:31] + node _T_2054 = or(_T_2053, _T_1243[4]) @[sequencer-master.scala 161:49] + node _T_2055 = or(_T_2054, _T_1420[4]) @[sequencer-master.scala 161:67] + when _T_2055 : @[sequencer-master.scala 161:86] + _T_3[tail][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2056 = or(_T_889[5], _T_1066[5]) @[sequencer-master.scala 161:31] + node _T_2057 = or(_T_2056, _T_1243[5]) @[sequencer-master.scala 161:49] + node _T_2058 = or(_T_2057, _T_1420[5]) @[sequencer-master.scala 161:67] + when _T_2058 : @[sequencer-master.scala 161:86] + _T_3[tail][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2059 = or(_T_889[6], _T_1066[6]) @[sequencer-master.scala 161:31] + node _T_2060 = or(_T_2059, _T_1243[6]) @[sequencer-master.scala 161:49] + node _T_2061 = or(_T_2060, _T_1420[6]) @[sequencer-master.scala 161:67] + when _T_2061 : @[sequencer-master.scala 161:86] + _T_3[tail][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2062 = or(_T_889[7], _T_1066[7]) @[sequencer-master.scala 161:31] + node _T_2063 = or(_T_2062, _T_1243[7]) @[sequencer-master.scala 161:49] + node _T_2064 = or(_T_2063, _T_1420[7]) @[sequencer-master.scala 161:67] + when _T_2064 : @[sequencer-master.scala 161:86] + _T_3[tail][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + when _T_1597[0] : @[sequencer-master.scala 168:32] + _T_4[tail][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[1] : @[sequencer-master.scala 168:32] + _T_4[tail][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[2] : @[sequencer-master.scala 168:32] + _T_4[tail][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[3] : @[sequencer-master.scala 168:32] + _T_4[tail][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[4] : @[sequencer-master.scala 168:32] + _T_4[tail][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[5] : @[sequencer-master.scala 168:32] + _T_4[tail][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[6] : @[sequencer-master.scala 168:32] + _T_4[tail][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[7] : @[sequencer-master.scala 168:32] + _T_4[tail][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + v[_T_1645] <= UInt<1>("h01") @[sequencer-master.scala 267:35] + e[_T_1645].rate <= UInt<1>("h00") @[sequencer-master.scala 271:19] + e[_T_1645].base.vp.valid <= UInt<1>("h00") @[sequencer-master.scala 272:28] + e[_T_1645].base.vs1.valid <= UInt<1>("h00") @[sequencer-master.scala 273:29] + e[_T_1645].base.vs2.valid <= UInt<1>("h00") @[sequencer-master.scala 274:29] + e[_T_1645].base.vs3.valid <= UInt<1>("h00") @[sequencer-master.scala 275:29] + e[_T_1645].base.vd.valid <= UInt<1>("h00") @[sequencer-master.scala 276:28] + _T_1[_T_1645] <= UInt<1>("h01") @[sequencer-master.scala 188:42] + _T_2[_T_1645][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1645][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1645][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1645][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1645][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1645][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1645][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1645][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1645][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1645][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1645][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1645][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1645][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1645][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1645][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1645][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1645][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1645][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1645][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1645][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1645][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1645][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1645][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1645][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + e[_T_1645].last <= UInt<1>("h00") @[sequencer-master.scala 283:19] + io.master.update.valid[_T_1645] <= UInt<1>("h01") @[sequencer-master.scala 284:35] + e[_T_1645].active.vfdu <= UInt<1>("h01") @[sequencer-master.scala 288:26] + e[_T_1645].fn.union <= io.op.bits.fn.union @[sequencer-master.scala 289:23] + node _T_2065 = eq(io.op.bits.base.vd.valid, UInt<1>("h00")) @[sequencer-master.scala 361:16] + node _T_2066 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_2067 = and(_T_2066, io.op.bits.base.vd.scalar) @[types-vxu.scala 119:37] + node _T_2068 = eq(_T_2067, UInt<1>("h00")) @[sequencer-master.scala 361:45] + node _T_2069 = or(_T_2065, _T_2068) @[sequencer-master.scala 361:42] + node _T_2070 = bits(reset, 0, 0) @[sequencer-master.scala 361:15] + node _T_2071 = or(_T_2069, _T_2070) @[sequencer-master.scala 361:15] + node _T_2072 = eq(_T_2071, UInt<1>("h00")) @[sequencer-master.scala 361:15] + when _T_2072 : @[sequencer-master.scala 361:15] + printf(clock, UInt<1>(1), "Assertion failed: iwindow.set.vd: vd should always be vector\n at sequencer-master.scala:361 assert(!io.op.bits.base.vd.valid || !io.op.bits.base.vd.is_scalar(), \"iwindow.set.vd: vd should always be vector\")\n") @[sequencer-master.scala 361:15] + stop(clock, UInt<1>(1), 1) @[sequencer-master.scala 361:15] + skip @[sequencer-master.scala 361:15] + when io.op.bits.base.vd.valid : @[sequencer-master.scala 362:41] + e[_T_1645].base.vd <- io.op.bits.base.vd @[sequencer-master.scala 363:24] + io.master.update.reg[_T_1645].vd.id <= io.op.bits.reg.vd.id @[sequencer-master.scala 364:41] + skip @[sequencer-master.scala 362:41] + node _T_2073 = or(_T_889[0], _T_1066[0]) @[sequencer-master.scala 161:31] + node _T_2074 = or(_T_2073, _T_1243[0]) @[sequencer-master.scala 161:49] + node _T_2075 = or(_T_2074, _T_1420[0]) @[sequencer-master.scala 161:67] + when _T_2075 : @[sequencer-master.scala 161:86] + _T_3[_T_1645][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2076 = or(_T_889[1], _T_1066[1]) @[sequencer-master.scala 161:31] + node _T_2077 = or(_T_2076, _T_1243[1]) @[sequencer-master.scala 161:49] + node _T_2078 = or(_T_2077, _T_1420[1]) @[sequencer-master.scala 161:67] + when _T_2078 : @[sequencer-master.scala 161:86] + _T_3[_T_1645][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2079 = or(_T_889[2], _T_1066[2]) @[sequencer-master.scala 161:31] + node _T_2080 = or(_T_2079, _T_1243[2]) @[sequencer-master.scala 161:49] + node _T_2081 = or(_T_2080, _T_1420[2]) @[sequencer-master.scala 161:67] + when _T_2081 : @[sequencer-master.scala 161:86] + _T_3[_T_1645][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2082 = or(_T_889[3], _T_1066[3]) @[sequencer-master.scala 161:31] + node _T_2083 = or(_T_2082, _T_1243[3]) @[sequencer-master.scala 161:49] + node _T_2084 = or(_T_2083, _T_1420[3]) @[sequencer-master.scala 161:67] + when _T_2084 : @[sequencer-master.scala 161:86] + _T_3[_T_1645][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2085 = or(_T_889[4], _T_1066[4]) @[sequencer-master.scala 161:31] + node _T_2086 = or(_T_2085, _T_1243[4]) @[sequencer-master.scala 161:49] + node _T_2087 = or(_T_2086, _T_1420[4]) @[sequencer-master.scala 161:67] + when _T_2087 : @[sequencer-master.scala 161:86] + _T_3[_T_1645][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2088 = or(_T_889[5], _T_1066[5]) @[sequencer-master.scala 161:31] + node _T_2089 = or(_T_2088, _T_1243[5]) @[sequencer-master.scala 161:49] + node _T_2090 = or(_T_2089, _T_1420[5]) @[sequencer-master.scala 161:67] + when _T_2090 : @[sequencer-master.scala 161:86] + _T_3[_T_1645][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2091 = or(_T_889[6], _T_1066[6]) @[sequencer-master.scala 161:31] + node _T_2092 = or(_T_2091, _T_1243[6]) @[sequencer-master.scala 161:49] + node _T_2093 = or(_T_2092, _T_1420[6]) @[sequencer-master.scala 161:67] + when _T_2093 : @[sequencer-master.scala 161:86] + _T_3[_T_1645][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2094 = or(_T_889[7], _T_1066[7]) @[sequencer-master.scala 161:31] + node _T_2095 = or(_T_2094, _T_1243[7]) @[sequencer-master.scala 161:49] + node _T_2096 = or(_T_2095, _T_1420[7]) @[sequencer-master.scala 161:67] + when _T_2096 : @[sequencer-master.scala 161:86] + _T_3[_T_1645][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + when _T_1597[0] : @[sequencer-master.scala 168:32] + _T_4[_T_1645][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[1] : @[sequencer-master.scala 168:32] + _T_4[_T_1645][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[2] : @[sequencer-master.scala 168:32] + _T_4[_T_1645][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[3] : @[sequencer-master.scala 168:32] + _T_4[_T_1645][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[4] : @[sequencer-master.scala 168:32] + _T_4[_T_1645][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[5] : @[sequencer-master.scala 168:32] + _T_4[_T_1645][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[6] : @[sequencer-master.scala 168:32] + _T_4[_T_1645][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[7] : @[sequencer-master.scala 168:32] + _T_4[_T_1645][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + e[_T_1645].rports <= UInt<1>("h00") @[sequencer-master.scala 230:21] + e[_T_1645].wport.sram <= UInt<1>("h00") @[sequencer-master.scala 231:25] + e[_T_1645].wport.pred <= UInt<1>("h00") @[sequencer-master.scala 232:25] + _T_1641 <= UInt<1>("h01") @[sequencer-master.scala 265:41] + _T_1643 <= _T_1647 @[sequencer-master.scala 265:66] + skip @[sequencer-master.scala 645:40] + when io.op.bits.active.vfcmp : @[sequencer-master.scala 646:40] + v[tail] <= UInt<1>("h01") @[sequencer-master.scala 267:35] + e[tail].rate <= UInt<1>("h00") @[sequencer-master.scala 271:19] + e[tail].base.vp.valid <= UInt<1>("h00") @[sequencer-master.scala 272:28] + e[tail].base.vs1.valid <= UInt<1>("h00") @[sequencer-master.scala 273:29] + e[tail].base.vs2.valid <= UInt<1>("h00") @[sequencer-master.scala 274:29] + e[tail].base.vs3.valid <= UInt<1>("h00") @[sequencer-master.scala 275:29] + e[tail].base.vd.valid <= UInt<1>("h00") @[sequencer-master.scala 276:28] + _T_1[tail] <= UInt<1>("h01") @[sequencer-master.scala 188:42] + _T_2[tail][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + e[tail].last <= UInt<1>("h00") @[sequencer-master.scala 283:19] + io.master.update.valid[tail] <= UInt<1>("h01") @[sequencer-master.scala 284:35] + e[tail].active.vfcu <= UInt<1>("h01") @[sequencer-master.scala 288:26] + e[tail].fn.union <= io.op.bits.fn.union @[sequencer-master.scala 289:23] + when io.op.bits.base.vp.valid : @[sequencer-master.scala 320:41] + e[tail].base.vp <- io.op.bits.base.vp @[sequencer-master.scala 321:24] + io.master.update.reg[tail].vp.id <= io.op.bits.reg.vp.id @[sequencer-master.scala 322:41] + skip @[sequencer-master.scala 320:41] + when _T_181[0] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[1] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[2] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[3] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[4] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[5] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[6] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[7] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when io.op.bits.base.vs1.valid : @[sequencer-master.scala 328:47] + e[tail].base.vs1 <- io.op.bits.base.vs1 @[sequencer-master.scala 329:29] + io.master.update.reg[tail].vs1.id <= io.op.bits.reg.vs1.id @[sequencer-master.scala 330:47] + node _T_2097 = eq(io.op.bits.base.vs1.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_2098 = and(_T_2097, io.op.bits.base.vs1.scalar) @[types-vxu.scala 119:37] + when _T_2098 : @[sequencer-master.scala 331:55] + e[tail].sreg.ss1 <= io.op.bits.sreg.ss1 @[sequencer-master.scala 332:31] + skip @[sequencer-master.scala 331:55] + skip @[sequencer-master.scala 328:47] + when _T_358[0] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[1] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[2] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[3] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[4] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[5] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[6] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[7] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when io.op.bits.base.vs2.valid : @[sequencer-master.scala 328:47] + e[tail].base.vs2 <- io.op.bits.base.vs2 @[sequencer-master.scala 329:29] + io.master.update.reg[tail].vs2.id <= io.op.bits.reg.vs2.id @[sequencer-master.scala 330:47] + node _T_2099 = eq(io.op.bits.base.vs2.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_2100 = and(_T_2099, io.op.bits.base.vs2.scalar) @[types-vxu.scala 119:37] + when _T_2100 : @[sequencer-master.scala 331:55] + e[tail].sreg.ss2 <= io.op.bits.sreg.ss2 @[sequencer-master.scala 332:31] + skip @[sequencer-master.scala 331:55] + skip @[sequencer-master.scala 328:47] + when _T_535[0] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[1] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[2] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[3] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[4] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[5] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[6] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[7] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + node _T_2101 = eq(io.op.bits.base.vd.valid, UInt<1>("h00")) @[sequencer-master.scala 361:16] + node _T_2102 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_2103 = and(_T_2102, io.op.bits.base.vd.scalar) @[types-vxu.scala 119:37] + node _T_2104 = eq(_T_2103, UInt<1>("h00")) @[sequencer-master.scala 361:45] + node _T_2105 = or(_T_2101, _T_2104) @[sequencer-master.scala 361:42] + node _T_2106 = bits(reset, 0, 0) @[sequencer-master.scala 361:15] + node _T_2107 = or(_T_2105, _T_2106) @[sequencer-master.scala 361:15] + node _T_2108 = eq(_T_2107, UInt<1>("h00")) @[sequencer-master.scala 361:15] + when _T_2108 : @[sequencer-master.scala 361:15] + printf(clock, UInt<1>(1), "Assertion failed: iwindow.set.vd: vd should always be vector\n at sequencer-master.scala:361 assert(!io.op.bits.base.vd.valid || !io.op.bits.base.vd.is_scalar(), \"iwindow.set.vd: vd should always be vector\")\n") @[sequencer-master.scala 361:15] + stop(clock, UInt<1>(1), 1) @[sequencer-master.scala 361:15] + skip @[sequencer-master.scala 361:15] + when io.op.bits.base.vd.valid : @[sequencer-master.scala 362:41] + e[tail].base.vd <- io.op.bits.base.vd @[sequencer-master.scala 363:24] + io.master.update.reg[tail].vd.id <= io.op.bits.reg.vd.id @[sequencer-master.scala 364:41] + skip @[sequencer-master.scala 362:41] + node _T_2109 = or(_T_889[0], _T_1066[0]) @[sequencer-master.scala 161:31] + node _T_2110 = or(_T_2109, _T_1243[0]) @[sequencer-master.scala 161:49] + node _T_2111 = or(_T_2110, _T_1420[0]) @[sequencer-master.scala 161:67] + when _T_2111 : @[sequencer-master.scala 161:86] + _T_3[tail][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2112 = or(_T_889[1], _T_1066[1]) @[sequencer-master.scala 161:31] + node _T_2113 = or(_T_2112, _T_1243[1]) @[sequencer-master.scala 161:49] + node _T_2114 = or(_T_2113, _T_1420[1]) @[sequencer-master.scala 161:67] + when _T_2114 : @[sequencer-master.scala 161:86] + _T_3[tail][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2115 = or(_T_889[2], _T_1066[2]) @[sequencer-master.scala 161:31] + node _T_2116 = or(_T_2115, _T_1243[2]) @[sequencer-master.scala 161:49] + node _T_2117 = or(_T_2116, _T_1420[2]) @[sequencer-master.scala 161:67] + when _T_2117 : @[sequencer-master.scala 161:86] + _T_3[tail][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2118 = or(_T_889[3], _T_1066[3]) @[sequencer-master.scala 161:31] + node _T_2119 = or(_T_2118, _T_1243[3]) @[sequencer-master.scala 161:49] + node _T_2120 = or(_T_2119, _T_1420[3]) @[sequencer-master.scala 161:67] + when _T_2120 : @[sequencer-master.scala 161:86] + _T_3[tail][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2121 = or(_T_889[4], _T_1066[4]) @[sequencer-master.scala 161:31] + node _T_2122 = or(_T_2121, _T_1243[4]) @[sequencer-master.scala 161:49] + node _T_2123 = or(_T_2122, _T_1420[4]) @[sequencer-master.scala 161:67] + when _T_2123 : @[sequencer-master.scala 161:86] + _T_3[tail][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2124 = or(_T_889[5], _T_1066[5]) @[sequencer-master.scala 161:31] + node _T_2125 = or(_T_2124, _T_1243[5]) @[sequencer-master.scala 161:49] + node _T_2126 = or(_T_2125, _T_1420[5]) @[sequencer-master.scala 161:67] + when _T_2126 : @[sequencer-master.scala 161:86] + _T_3[tail][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2127 = or(_T_889[6], _T_1066[6]) @[sequencer-master.scala 161:31] + node _T_2128 = or(_T_2127, _T_1243[6]) @[sequencer-master.scala 161:49] + node _T_2129 = or(_T_2128, _T_1420[6]) @[sequencer-master.scala 161:67] + when _T_2129 : @[sequencer-master.scala 161:86] + _T_3[tail][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2130 = or(_T_889[7], _T_1066[7]) @[sequencer-master.scala 161:31] + node _T_2131 = or(_T_2130, _T_1243[7]) @[sequencer-master.scala 161:49] + node _T_2132 = or(_T_2131, _T_1420[7]) @[sequencer-master.scala 161:67] + when _T_2132 : @[sequencer-master.scala 161:86] + _T_3[tail][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + when _T_1597[0] : @[sequencer-master.scala 168:32] + _T_4[tail][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[1] : @[sequencer-master.scala 168:32] + _T_4[tail][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[2] : @[sequencer-master.scala 168:32] + _T_4[tail][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[3] : @[sequencer-master.scala 168:32] + _T_4[tail][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[4] : @[sequencer-master.scala 168:32] + _T_4[tail][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[5] : @[sequencer-master.scala 168:32] + _T_4[tail][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[6] : @[sequencer-master.scala 168:32] + _T_4[tail][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[7] : @[sequencer-master.scala 168:32] + _T_4[tail][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + e[tail].rports <= _T_1615 @[sequencer-master.scala 230:21] + e[tail].wport.sram <= UInt<1>("h00") @[sequencer-master.scala 231:25] + e[tail].wport.pred <= UInt<1>("h00") @[sequencer-master.scala 232:25] + node _T_2133 = add(UInt<4>("h00"), _T_1615) @[sequencer-master.scala 247:46] + node _T_2134 = tail(_T_2133, 1) @[sequencer-master.scala 247:46] + node _T_2135 = add(_T_2134, UInt<2>("h02")) @[sequencer-master.scala 247:56] + node _T_2136 = tail(_T_2135, 1) @[sequencer-master.scala 247:56] + node _T_2137 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_2138 = eq(io.op.bits.base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_2139 = and(_T_2137, _T_2138) @[types-vxu.scala 120:37] + when _T_2139 : @[sequencer-master.scala 235:47] + e[tail].wport.sram <= _T_2136 @[sequencer-master.scala 235:65] + skip @[sequencer-master.scala 235:47] + when io.op.bits.base.vd.pred : @[sequencer-master.scala 236:45] + e[tail].wport.pred <= _T_2136 @[sequencer-master.scala 236:63] + skip @[sequencer-master.scala 236:45] + _T_1641 <= UInt<1>("h01") @[sequencer-master.scala 265:41] + _T_1643 <= _T_1645 @[sequencer-master.scala 265:66] + skip @[sequencer-master.scala 646:40] + when io.op.bits.active.vfconv : @[sequencer-master.scala 647:41] + v[tail] <= UInt<1>("h01") @[sequencer-master.scala 267:35] + e[tail].rate <= UInt<1>("h00") @[sequencer-master.scala 271:19] + e[tail].base.vp.valid <= UInt<1>("h00") @[sequencer-master.scala 272:28] + e[tail].base.vs1.valid <= UInt<1>("h00") @[sequencer-master.scala 273:29] + e[tail].base.vs2.valid <= UInt<1>("h00") @[sequencer-master.scala 274:29] + e[tail].base.vs3.valid <= UInt<1>("h00") @[sequencer-master.scala 275:29] + e[tail].base.vd.valid <= UInt<1>("h00") @[sequencer-master.scala 276:28] + _T_1[tail] <= UInt<1>("h01") @[sequencer-master.scala 188:42] + _T_2[tail][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + e[tail].last <= UInt<1>("h00") @[sequencer-master.scala 283:19] + io.master.update.valid[tail] <= UInt<1>("h01") @[sequencer-master.scala 284:35] + e[tail].active.vfvu <= UInt<1>("h01") @[sequencer-master.scala 288:26] + e[tail].fn.union <= io.op.bits.fn.union @[sequencer-master.scala 289:23] + when io.op.bits.base.vp.valid : @[sequencer-master.scala 320:41] + e[tail].base.vp <- io.op.bits.base.vp @[sequencer-master.scala 321:24] + io.master.update.reg[tail].vp.id <= io.op.bits.reg.vp.id @[sequencer-master.scala 322:41] + skip @[sequencer-master.scala 320:41] + when _T_181[0] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[1] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[2] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[3] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[4] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[5] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[6] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[7] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when io.op.bits.base.vs1.valid : @[sequencer-master.scala 328:47] + e[tail].base.vs1 <- io.op.bits.base.vs1 @[sequencer-master.scala 329:29] + io.master.update.reg[tail].vs1.id <= io.op.bits.reg.vs1.id @[sequencer-master.scala 330:47] + node _T_2140 = eq(io.op.bits.base.vs1.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_2141 = and(_T_2140, io.op.bits.base.vs1.scalar) @[types-vxu.scala 119:37] + when _T_2141 : @[sequencer-master.scala 331:55] + e[tail].sreg.ss1 <= io.op.bits.sreg.ss1 @[sequencer-master.scala 332:31] + skip @[sequencer-master.scala 331:55] + skip @[sequencer-master.scala 328:47] + when _T_358[0] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[1] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[2] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[3] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[4] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[5] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[6] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[7] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + node _T_2142 = eq(io.op.bits.base.vd.valid, UInt<1>("h00")) @[sequencer-master.scala 361:16] + node _T_2143 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_2144 = and(_T_2143, io.op.bits.base.vd.scalar) @[types-vxu.scala 119:37] + node _T_2145 = eq(_T_2144, UInt<1>("h00")) @[sequencer-master.scala 361:45] + node _T_2146 = or(_T_2142, _T_2145) @[sequencer-master.scala 361:42] + node _T_2147 = bits(reset, 0, 0) @[sequencer-master.scala 361:15] + node _T_2148 = or(_T_2146, _T_2147) @[sequencer-master.scala 361:15] + node _T_2149 = eq(_T_2148, UInt<1>("h00")) @[sequencer-master.scala 361:15] + when _T_2149 : @[sequencer-master.scala 361:15] + printf(clock, UInt<1>(1), "Assertion failed: iwindow.set.vd: vd should always be vector\n at sequencer-master.scala:361 assert(!io.op.bits.base.vd.valid || !io.op.bits.base.vd.is_scalar(), \"iwindow.set.vd: vd should always be vector\")\n") @[sequencer-master.scala 361:15] + stop(clock, UInt<1>(1), 1) @[sequencer-master.scala 361:15] + skip @[sequencer-master.scala 361:15] + when io.op.bits.base.vd.valid : @[sequencer-master.scala 362:41] + e[tail].base.vd <- io.op.bits.base.vd @[sequencer-master.scala 363:24] + io.master.update.reg[tail].vd.id <= io.op.bits.reg.vd.id @[sequencer-master.scala 364:41] + skip @[sequencer-master.scala 362:41] + node _T_2150 = or(_T_889[0], _T_1066[0]) @[sequencer-master.scala 161:31] + node _T_2151 = or(_T_2150, _T_1243[0]) @[sequencer-master.scala 161:49] + node _T_2152 = or(_T_2151, _T_1420[0]) @[sequencer-master.scala 161:67] + when _T_2152 : @[sequencer-master.scala 161:86] + _T_3[tail][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2153 = or(_T_889[1], _T_1066[1]) @[sequencer-master.scala 161:31] + node _T_2154 = or(_T_2153, _T_1243[1]) @[sequencer-master.scala 161:49] + node _T_2155 = or(_T_2154, _T_1420[1]) @[sequencer-master.scala 161:67] + when _T_2155 : @[sequencer-master.scala 161:86] + _T_3[tail][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2156 = or(_T_889[2], _T_1066[2]) @[sequencer-master.scala 161:31] + node _T_2157 = or(_T_2156, _T_1243[2]) @[sequencer-master.scala 161:49] + node _T_2158 = or(_T_2157, _T_1420[2]) @[sequencer-master.scala 161:67] + when _T_2158 : @[sequencer-master.scala 161:86] + _T_3[tail][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2159 = or(_T_889[3], _T_1066[3]) @[sequencer-master.scala 161:31] + node _T_2160 = or(_T_2159, _T_1243[3]) @[sequencer-master.scala 161:49] + node _T_2161 = or(_T_2160, _T_1420[3]) @[sequencer-master.scala 161:67] + when _T_2161 : @[sequencer-master.scala 161:86] + _T_3[tail][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2162 = or(_T_889[4], _T_1066[4]) @[sequencer-master.scala 161:31] + node _T_2163 = or(_T_2162, _T_1243[4]) @[sequencer-master.scala 161:49] + node _T_2164 = or(_T_2163, _T_1420[4]) @[sequencer-master.scala 161:67] + when _T_2164 : @[sequencer-master.scala 161:86] + _T_3[tail][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2165 = or(_T_889[5], _T_1066[5]) @[sequencer-master.scala 161:31] + node _T_2166 = or(_T_2165, _T_1243[5]) @[sequencer-master.scala 161:49] + node _T_2167 = or(_T_2166, _T_1420[5]) @[sequencer-master.scala 161:67] + when _T_2167 : @[sequencer-master.scala 161:86] + _T_3[tail][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2168 = or(_T_889[6], _T_1066[6]) @[sequencer-master.scala 161:31] + node _T_2169 = or(_T_2168, _T_1243[6]) @[sequencer-master.scala 161:49] + node _T_2170 = or(_T_2169, _T_1420[6]) @[sequencer-master.scala 161:67] + when _T_2170 : @[sequencer-master.scala 161:86] + _T_3[tail][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2171 = or(_T_889[7], _T_1066[7]) @[sequencer-master.scala 161:31] + node _T_2172 = or(_T_2171, _T_1243[7]) @[sequencer-master.scala 161:49] + node _T_2173 = or(_T_2172, _T_1420[7]) @[sequencer-master.scala 161:67] + when _T_2173 : @[sequencer-master.scala 161:86] + _T_3[tail][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + when _T_1597[0] : @[sequencer-master.scala 168:32] + _T_4[tail][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[1] : @[sequencer-master.scala 168:32] + _T_4[tail][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[2] : @[sequencer-master.scala 168:32] + _T_4[tail][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[3] : @[sequencer-master.scala 168:32] + _T_4[tail][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[4] : @[sequencer-master.scala 168:32] + _T_4[tail][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[5] : @[sequencer-master.scala 168:32] + _T_4[tail][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[6] : @[sequencer-master.scala 168:32] + _T_4[tail][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[7] : @[sequencer-master.scala 168:32] + _T_4[tail][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + e[tail].rports <= _T_1615 @[sequencer-master.scala 230:21] + e[tail].wport.sram <= UInt<1>("h00") @[sequencer-master.scala 231:25] + e[tail].wport.pred <= UInt<1>("h00") @[sequencer-master.scala 232:25] + node _T_2174 = add(UInt<4>("h00"), _T_1615) @[sequencer-master.scala 247:46] + node _T_2175 = tail(_T_2174, 1) @[sequencer-master.scala 247:46] + node _T_2176 = add(_T_2175, UInt<2>("h03")) @[sequencer-master.scala 247:56] + node _T_2177 = tail(_T_2176, 1) @[sequencer-master.scala 247:56] + node _T_2178 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 120:31] + node _T_2179 = eq(io.op.bits.base.vd.scalar, UInt<1>("h00")) @[types-vxu.scala 120:40] + node _T_2180 = and(_T_2178, _T_2179) @[types-vxu.scala 120:37] + when _T_2180 : @[sequencer-master.scala 235:47] + e[tail].wport.sram <= _T_2177 @[sequencer-master.scala 235:65] + skip @[sequencer-master.scala 235:47] + when io.op.bits.base.vd.pred : @[sequencer-master.scala 236:45] + e[tail].wport.pred <= _T_2177 @[sequencer-master.scala 236:63] + skip @[sequencer-master.scala 236:45] + _T_1641 <= UInt<1>("h01") @[sequencer-master.scala 265:41] + _T_1643 <= _T_1645 @[sequencer-master.scala 265:66] + skip @[sequencer-master.scala 647:41] + when io.op.bits.active.vrpred : @[sequencer-master.scala 648:41] + v[tail] <= UInt<1>("h01") @[sequencer-master.scala 267:35] + e[tail].rate <= UInt<1>("h00") @[sequencer-master.scala 271:19] + e[tail].base.vp.valid <= UInt<1>("h00") @[sequencer-master.scala 272:28] + e[tail].base.vs1.valid <= UInt<1>("h00") @[sequencer-master.scala 273:29] + e[tail].base.vs2.valid <= UInt<1>("h00") @[sequencer-master.scala 274:29] + e[tail].base.vs3.valid <= UInt<1>("h00") @[sequencer-master.scala 275:29] + e[tail].base.vd.valid <= UInt<1>("h00") @[sequencer-master.scala 276:28] + _T_1[tail] <= UInt<1>("h01") @[sequencer-master.scala 188:42] + _T_2[tail][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + e[tail].last <= UInt<1>("h00") @[sequencer-master.scala 283:19] + io.master.update.valid[tail] <= UInt<1>("h01") @[sequencer-master.scala 284:35] + e[tail].active.vqu <= UInt<1>("h01") @[sequencer-master.scala 288:26] + node _T_2181 = or(io.op.bits.active.vidiv, io.op.bits.active.vfdiv) @[sequencer-master.scala 298:31] + node _T_2182 = or(_T_2181, io.op.bits.active.vrpred) @[sequencer-master.scala 298:49] + node _T_2183 = or(_T_2182, io.op.bits.active.vrfirst) @[sequencer-master.scala 298:68] + node _T_2184 = bits(reset, 0, 0) @[sequencer-master.scala 298:15] + node _T_2185 = or(_T_2183, _T_2184) @[sequencer-master.scala 298:15] + node _T_2186 = eq(_T_2185, UInt<1>("h00")) @[sequencer-master.scala 298:15] + when _T_2186 : @[sequencer-master.scala 298:15] + printf(clock, UInt<1>(1), "Assertion failed: vqu should only be issued for idiv/fdiv/rpred/rfirst\n at sequencer-master.scala:298 assert(d.active.vidiv || d.active.vfdiv || d.active.vrpred || d.active.vrfirst,\n") @[sequencer-master.scala 298:15] + stop(clock, UInt<1>(1), 1) @[sequencer-master.scala 298:15] + skip @[sequencer-master.scala 298:15] + wire _T_2187 : {fp : UInt<2>, rm : UInt<3>, op : UInt<1>} @[types-vxu.scala 96:47] + _T_2187 is invalid @[types-vxu.scala 96:47] + wire _T_2188 : UInt<6> + _T_2188 is invalid + _T_2188 <= io.op.bits.fn.union + node _T_2189 = bits(_T_2188, 0, 0) @[types-vxu.scala 96:47] + _T_2187.op <= _T_2189 @[types-vxu.scala 96:47] + node _T_2190 = bits(_T_2188, 3, 1) @[types-vxu.scala 96:47] + _T_2187.rm <= _T_2190 @[types-vxu.scala 96:47] + node _T_2191 = bits(_T_2188, 5, 4) @[types-vxu.scala 96:47] + _T_2187.fp <= _T_2191 @[types-vxu.scala 96:47] + node _T_2192 = eq(_T_2187.op, UInt<1>("h00")) @[types-vxu.scala 54:51] + node _T_2193 = and(io.op.bits.active.vfdiv, _T_2192) @[sequencer-master.scala 300:46] + node _T_2194 = or(io.op.bits.active.vidiv, _T_2193) @[sequencer-master.scala 300:28] + node _T_2195 = or(io.op.bits.active.vidiv, io.op.bits.active.vfdiv) @[sequencer-master.scala 301:28] + node _T_2196 = or(_T_2195, io.op.bits.active.vrfirst) @[sequencer-master.scala 301:46] + node _T_2197 = cat(_T_2194, _T_2196) @[Cat.scala 30:58] + e[tail].fn.union <= _T_2197 @[sequencer-master.scala 289:23] + when io.op.bits.base.vp.valid : @[sequencer-master.scala 320:41] + e[tail].base.vp <- io.op.bits.base.vp @[sequencer-master.scala 321:24] + io.master.update.reg[tail].vp.id <= io.op.bits.reg.vp.id @[sequencer-master.scala 322:41] + skip @[sequencer-master.scala 320:41] + when _T_181[0] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[1] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[2] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[3] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[4] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[5] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[6] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[7] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + e[tail].rports <= _T_1615 @[sequencer-master.scala 230:21] + e[tail].wport.sram <= UInt<1>("h00") @[sequencer-master.scala 231:25] + e[tail].wport.pred <= UInt<1>("h00") @[sequencer-master.scala 232:25] + _T_1641 <= UInt<1>("h01") @[sequencer-master.scala 265:41] + _T_1643 <= _T_1645 @[sequencer-master.scala 265:66] + skip @[sequencer-master.scala 648:41] + when io.op.bits.active.vrfirst : @[sequencer-master.scala 649:42] + v[tail] <= UInt<1>("h01") @[sequencer-master.scala 267:35] + e[tail].rate <= UInt<1>("h00") @[sequencer-master.scala 271:19] + e[tail].base.vp.valid <= UInt<1>("h00") @[sequencer-master.scala 272:28] + e[tail].base.vs1.valid <= UInt<1>("h00") @[sequencer-master.scala 273:29] + e[tail].base.vs2.valid <= UInt<1>("h00") @[sequencer-master.scala 274:29] + e[tail].base.vs3.valid <= UInt<1>("h00") @[sequencer-master.scala 275:29] + e[tail].base.vd.valid <= UInt<1>("h00") @[sequencer-master.scala 276:28] + _T_1[tail] <= UInt<1>("h01") @[sequencer-master.scala 188:42] + _T_2[tail][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + e[tail].last <= UInt<1>("h00") @[sequencer-master.scala 283:19] + io.master.update.valid[tail] <= UInt<1>("h01") @[sequencer-master.scala 284:35] + e[tail].active.vqu <= UInt<1>("h01") @[sequencer-master.scala 288:26] + node _T_2198 = or(io.op.bits.active.vidiv, io.op.bits.active.vfdiv) @[sequencer-master.scala 298:31] + node _T_2199 = or(_T_2198, io.op.bits.active.vrpred) @[sequencer-master.scala 298:49] + node _T_2200 = or(_T_2199, io.op.bits.active.vrfirst) @[sequencer-master.scala 298:68] + node _T_2201 = bits(reset, 0, 0) @[sequencer-master.scala 298:15] + node _T_2202 = or(_T_2200, _T_2201) @[sequencer-master.scala 298:15] + node _T_2203 = eq(_T_2202, UInt<1>("h00")) @[sequencer-master.scala 298:15] + when _T_2203 : @[sequencer-master.scala 298:15] + printf(clock, UInt<1>(1), "Assertion failed: vqu should only be issued for idiv/fdiv/rpred/rfirst\n at sequencer-master.scala:298 assert(d.active.vidiv || d.active.vfdiv || d.active.vrpred || d.active.vrfirst,\n") @[sequencer-master.scala 298:15] + stop(clock, UInt<1>(1), 1) @[sequencer-master.scala 298:15] + skip @[sequencer-master.scala 298:15] + wire _T_2204 : {fp : UInt<2>, rm : UInt<3>, op : UInt<1>} @[types-vxu.scala 96:47] + _T_2204 is invalid @[types-vxu.scala 96:47] + wire _T_2205 : UInt<6> + _T_2205 is invalid + _T_2205 <= io.op.bits.fn.union + node _T_2206 = bits(_T_2205, 0, 0) @[types-vxu.scala 96:47] + _T_2204.op <= _T_2206 @[types-vxu.scala 96:47] + node _T_2207 = bits(_T_2205, 3, 1) @[types-vxu.scala 96:47] + _T_2204.rm <= _T_2207 @[types-vxu.scala 96:47] + node _T_2208 = bits(_T_2205, 5, 4) @[types-vxu.scala 96:47] + _T_2204.fp <= _T_2208 @[types-vxu.scala 96:47] + node _T_2209 = eq(_T_2204.op, UInt<1>("h00")) @[types-vxu.scala 54:51] + node _T_2210 = and(io.op.bits.active.vfdiv, _T_2209) @[sequencer-master.scala 300:46] + node _T_2211 = or(io.op.bits.active.vidiv, _T_2210) @[sequencer-master.scala 300:28] + node _T_2212 = or(io.op.bits.active.vidiv, io.op.bits.active.vfdiv) @[sequencer-master.scala 301:28] + node _T_2213 = or(_T_2212, io.op.bits.active.vrfirst) @[sequencer-master.scala 301:46] + node _T_2214 = cat(_T_2211, _T_2213) @[Cat.scala 30:58] + e[tail].fn.union <= _T_2214 @[sequencer-master.scala 289:23] + when io.op.bits.base.vp.valid : @[sequencer-master.scala 320:41] + e[tail].base.vp <- io.op.bits.base.vp @[sequencer-master.scala 321:24] + io.master.update.reg[tail].vp.id <= io.op.bits.reg.vp.id @[sequencer-master.scala 322:41] + skip @[sequencer-master.scala 320:41] + when _T_181[0] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[1] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[2] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[3] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[4] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[5] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[6] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[7] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when io.op.bits.base.vs1.valid : @[sequencer-master.scala 328:47] + e[tail].base.vs1 <- io.op.bits.base.vs1 @[sequencer-master.scala 329:29] + io.master.update.reg[tail].vs1.id <= io.op.bits.reg.vs1.id @[sequencer-master.scala 330:47] + node _T_2215 = eq(io.op.bits.base.vs1.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_2216 = and(_T_2215, io.op.bits.base.vs1.scalar) @[types-vxu.scala 119:37] + when _T_2216 : @[sequencer-master.scala 331:55] + e[tail].sreg.ss1 <= io.op.bits.sreg.ss1 @[sequencer-master.scala 332:31] + skip @[sequencer-master.scala 331:55] + skip @[sequencer-master.scala 328:47] + when _T_358[0] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[1] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[2] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[3] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[4] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[5] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[6] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[7] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + e[tail].rports <= _T_1615 @[sequencer-master.scala 230:21] + e[tail].wport.sram <= UInt<1>("h00") @[sequencer-master.scala 231:25] + e[tail].wport.pred <= UInt<1>("h00") @[sequencer-master.scala 232:25] + _T_1641 <= UInt<1>("h01") @[sequencer-master.scala 265:41] + _T_1643 <= _T_1645 @[sequencer-master.scala 265:66] + skip @[sequencer-master.scala 649:42] + when io.op.bits.active.vamo : @[sequencer-master.scala 650:39] + v[tail] <= UInt<1>("h01") @[sequencer-master.scala 267:35] + e[tail].rate <= UInt<1>("h00") @[sequencer-master.scala 271:19] + e[tail].base.vp.valid <= UInt<1>("h00") @[sequencer-master.scala 272:28] + e[tail].base.vs1.valid <= UInt<1>("h00") @[sequencer-master.scala 273:29] + e[tail].base.vs2.valid <= UInt<1>("h00") @[sequencer-master.scala 274:29] + e[tail].base.vs3.valid <= UInt<1>("h00") @[sequencer-master.scala 275:29] + e[tail].base.vd.valid <= UInt<1>("h00") @[sequencer-master.scala 276:28] + _T_1[tail] <= UInt<1>("h01") @[sequencer-master.scala 188:42] + _T_2[tail][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + e[tail].last <= UInt<1>("h00") @[sequencer-master.scala 283:19] + io.master.update.valid[tail] <= UInt<1>("h01") @[sequencer-master.scala 284:35] + e[tail].active.vgu <= UInt<1>("h01") @[sequencer-master.scala 288:26] + e[tail].fn.union <= io.op.bits.fn.union @[sequencer-master.scala 289:23] + when io.op.bits.base.vp.valid : @[sequencer-master.scala 320:41] + e[tail].base.vp <- io.op.bits.base.vp @[sequencer-master.scala 321:24] + io.master.update.reg[tail].vp.id <= io.op.bits.reg.vp.id @[sequencer-master.scala 322:41] + skip @[sequencer-master.scala 320:41] + when _T_181[0] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[1] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[2] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[3] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[4] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[5] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[6] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[7] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when io.op.bits.base.vs1.valid : @[sequencer-master.scala 328:47] + e[tail].base.vs1 <- io.op.bits.base.vs1 @[sequencer-master.scala 329:29] + io.master.update.reg[tail].vs1.id <= io.op.bits.reg.vs1.id @[sequencer-master.scala 330:47] + node _T_2217 = eq(io.op.bits.base.vs1.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_2218 = and(_T_2217, io.op.bits.base.vs1.scalar) @[types-vxu.scala 119:37] + when _T_2218 : @[sequencer-master.scala 331:55] + e[tail].sreg.ss1 <= io.op.bits.sreg.ss1 @[sequencer-master.scala 332:31] + skip @[sequencer-master.scala 331:55] + skip @[sequencer-master.scala 328:47] + when _T_358[0] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[1] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[2] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[3] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[4] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[5] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[6] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_358[7] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + e[tail].rports <= _T_1623 @[sequencer-master.scala 230:21] + e[tail].wport.sram <= UInt<1>("h00") @[sequencer-master.scala 231:25] + e[tail].wport.pred <= UInt<1>("h00") @[sequencer-master.scala 232:25] + v[_T_1645] <= UInt<1>("h01") @[sequencer-master.scala 267:35] + e[_T_1645].rate <= UInt<1>("h00") @[sequencer-master.scala 271:19] + e[_T_1645].base.vp.valid <= UInt<1>("h00") @[sequencer-master.scala 272:28] + e[_T_1645].base.vs1.valid <= UInt<1>("h00") @[sequencer-master.scala 273:29] + e[_T_1645].base.vs2.valid <= UInt<1>("h00") @[sequencer-master.scala 274:29] + e[_T_1645].base.vs3.valid <= UInt<1>("h00") @[sequencer-master.scala 275:29] + e[_T_1645].base.vd.valid <= UInt<1>("h00") @[sequencer-master.scala 276:28] + _T_1[_T_1645] <= UInt<1>("h01") @[sequencer-master.scala 188:42] + _T_2[_T_1645][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1645][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1645][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1645][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1645][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1645][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1645][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1645][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1645][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1645][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1645][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1645][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1645][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1645][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1645][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1645][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1645][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1645][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1645][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1645][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1645][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1645][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1645][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1645][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + e[_T_1645].last <= UInt<1>("h00") @[sequencer-master.scala 283:19] + io.master.update.valid[_T_1645] <= UInt<1>("h01") @[sequencer-master.scala 284:35] + e[_T_1645].active.vcu <= UInt<1>("h01") @[sequencer-master.scala 288:26] + e[_T_1645].fn.union <= io.op.bits.fn.union @[sequencer-master.scala 289:23] + e[_T_1645].rports <= UInt<1>("h00") @[sequencer-master.scala 230:21] + e[_T_1645].wport.sram <= UInt<1>("h00") @[sequencer-master.scala 231:25] + e[_T_1645].wport.pred <= UInt<1>("h00") @[sequencer-master.scala 232:25] + node _T_2219 = or(_T_889[0], _T_1066[0]) @[sequencer-master.scala 161:31] + node _T_2220 = or(_T_2219, _T_1243[0]) @[sequencer-master.scala 161:49] + node _T_2221 = or(_T_2220, _T_1420[0]) @[sequencer-master.scala 161:67] + when _T_2221 : @[sequencer-master.scala 161:86] + _T_3[_T_1645][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2222 = or(_T_889[1], _T_1066[1]) @[sequencer-master.scala 161:31] + node _T_2223 = or(_T_2222, _T_1243[1]) @[sequencer-master.scala 161:49] + node _T_2224 = or(_T_2223, _T_1420[1]) @[sequencer-master.scala 161:67] + when _T_2224 : @[sequencer-master.scala 161:86] + _T_3[_T_1645][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2225 = or(_T_889[2], _T_1066[2]) @[sequencer-master.scala 161:31] + node _T_2226 = or(_T_2225, _T_1243[2]) @[sequencer-master.scala 161:49] + node _T_2227 = or(_T_2226, _T_1420[2]) @[sequencer-master.scala 161:67] + when _T_2227 : @[sequencer-master.scala 161:86] + _T_3[_T_1645][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2228 = or(_T_889[3], _T_1066[3]) @[sequencer-master.scala 161:31] + node _T_2229 = or(_T_2228, _T_1243[3]) @[sequencer-master.scala 161:49] + node _T_2230 = or(_T_2229, _T_1420[3]) @[sequencer-master.scala 161:67] + when _T_2230 : @[sequencer-master.scala 161:86] + _T_3[_T_1645][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2231 = or(_T_889[4], _T_1066[4]) @[sequencer-master.scala 161:31] + node _T_2232 = or(_T_2231, _T_1243[4]) @[sequencer-master.scala 161:49] + node _T_2233 = or(_T_2232, _T_1420[4]) @[sequencer-master.scala 161:67] + when _T_2233 : @[sequencer-master.scala 161:86] + _T_3[_T_1645][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2234 = or(_T_889[5], _T_1066[5]) @[sequencer-master.scala 161:31] + node _T_2235 = or(_T_2234, _T_1243[5]) @[sequencer-master.scala 161:49] + node _T_2236 = or(_T_2235, _T_1420[5]) @[sequencer-master.scala 161:67] + when _T_2236 : @[sequencer-master.scala 161:86] + _T_3[_T_1645][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2237 = or(_T_889[6], _T_1066[6]) @[sequencer-master.scala 161:31] + node _T_2238 = or(_T_2237, _T_1243[6]) @[sequencer-master.scala 161:49] + node _T_2239 = or(_T_2238, _T_1420[6]) @[sequencer-master.scala 161:67] + when _T_2239 : @[sequencer-master.scala 161:86] + _T_3[_T_1645][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2240 = or(_T_889[7], _T_1066[7]) @[sequencer-master.scala 161:31] + node _T_2241 = or(_T_2240, _T_1243[7]) @[sequencer-master.scala 161:49] + node _T_2242 = or(_T_2241, _T_1420[7]) @[sequencer-master.scala 161:67] + when _T_2242 : @[sequencer-master.scala 161:86] + _T_3[_T_1645][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + when _T_1597[0] : @[sequencer-master.scala 168:32] + _T_4[_T_1645][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[1] : @[sequencer-master.scala 168:32] + _T_4[_T_1645][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[2] : @[sequencer-master.scala 168:32] + _T_4[_T_1645][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[3] : @[sequencer-master.scala 168:32] + _T_4[_T_1645][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[4] : @[sequencer-master.scala 168:32] + _T_4[_T_1645][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[5] : @[sequencer-master.scala 168:32] + _T_4[_T_1645][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[6] : @[sequencer-master.scala 168:32] + _T_4[_T_1645][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[7] : @[sequencer-master.scala 168:32] + _T_4[_T_1645][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + v[_T_1647] <= UInt<1>("h01") @[sequencer-master.scala 267:35] + e[_T_1647].rate <= UInt<1>("h00") @[sequencer-master.scala 271:19] + e[_T_1647].base.vp.valid <= UInt<1>("h00") @[sequencer-master.scala 272:28] + e[_T_1647].base.vs1.valid <= UInt<1>("h00") @[sequencer-master.scala 273:29] + e[_T_1647].base.vs2.valid <= UInt<1>("h00") @[sequencer-master.scala 274:29] + e[_T_1647].base.vs3.valid <= UInt<1>("h00") @[sequencer-master.scala 275:29] + e[_T_1647].base.vd.valid <= UInt<1>("h00") @[sequencer-master.scala 276:28] + _T_1[_T_1647] <= UInt<1>("h01") @[sequencer-master.scala 188:42] + _T_2[_T_1647][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1647][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1647][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1647][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1647][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1647][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1647][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1647][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1647][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1647][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1647][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1647][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1647][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1647][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1647][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1647][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1647][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1647][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1647][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1647][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1647][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1647][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1647][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1647][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + e[_T_1647].last <= UInt<1>("h00") @[sequencer-master.scala 283:19] + io.master.update.valid[_T_1647] <= UInt<1>("h01") @[sequencer-master.scala 284:35] + e[_T_1647].active.vsu <= UInt<1>("h01") @[sequencer-master.scala 288:26] + e[_T_1647].fn.union <= io.op.bits.fn.union @[sequencer-master.scala 289:23] + when io.op.bits.base.vp.valid : @[sequencer-master.scala 320:41] + e[_T_1647].base.vp <- io.op.bits.base.vp @[sequencer-master.scala 321:24] + io.master.update.reg[_T_1647].vp.id <= io.op.bits.reg.vp.id @[sequencer-master.scala 322:41] + skip @[sequencer-master.scala 320:41] + when _T_181[0] : @[sequencer-master.scala 154:24] + _T_2[_T_1647][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[1] : @[sequencer-master.scala 154:24] + _T_2[_T_1647][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[2] : @[sequencer-master.scala 154:24] + _T_2[_T_1647][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[3] : @[sequencer-master.scala 154:24] + _T_2[_T_1647][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[4] : @[sequencer-master.scala 154:24] + _T_2[_T_1647][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[5] : @[sequencer-master.scala 154:24] + _T_2[_T_1647][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[6] : @[sequencer-master.scala 154:24] + _T_2[_T_1647][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[7] : @[sequencer-master.scala 154:24] + _T_2[_T_1647][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when io.op.bits.base.vs2.valid : @[sequencer-master.scala 328:47] + e[_T_1647].base.vs1 <- io.op.bits.base.vs2 @[sequencer-master.scala 329:29] + io.master.update.reg[_T_1647].vs1.id <= io.op.bits.reg.vs2.id @[sequencer-master.scala 330:47] + node _T_2243 = eq(io.op.bits.base.vs2.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_2244 = and(_T_2243, io.op.bits.base.vs2.scalar) @[types-vxu.scala 119:37] + when _T_2244 : @[sequencer-master.scala 331:55] + e[_T_1647].sreg.ss1 <= io.op.bits.sreg.ss2 @[sequencer-master.scala 332:31] + skip @[sequencer-master.scala 331:55] + skip @[sequencer-master.scala 328:47] + when _T_535[0] : @[sequencer-master.scala 154:24] + _T_2[_T_1647][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[1] : @[sequencer-master.scala 154:24] + _T_2[_T_1647][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[2] : @[sequencer-master.scala 154:24] + _T_2[_T_1647][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[3] : @[sequencer-master.scala 154:24] + _T_2[_T_1647][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[4] : @[sequencer-master.scala 154:24] + _T_2[_T_1647][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[5] : @[sequencer-master.scala 154:24] + _T_2[_T_1647][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[6] : @[sequencer-master.scala 154:24] + _T_2[_T_1647][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[7] : @[sequencer-master.scala 154:24] + _T_2[_T_1647][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + e[_T_1647].rports <= _T_1631 @[sequencer-master.scala 230:21] + e[_T_1647].wport.sram <= UInt<1>("h00") @[sequencer-master.scala 231:25] + e[_T_1647].wport.pred <= UInt<1>("h00") @[sequencer-master.scala 232:25] + _T_2[_T_1647][_T_1645] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + v[_T_1649] <= UInt<1>("h01") @[sequencer-master.scala 267:35] + e[_T_1649].rate <= UInt<1>("h00") @[sequencer-master.scala 271:19] + e[_T_1649].base.vp.valid <= UInt<1>("h00") @[sequencer-master.scala 272:28] + e[_T_1649].base.vs1.valid <= UInt<1>("h00") @[sequencer-master.scala 273:29] + e[_T_1649].base.vs2.valid <= UInt<1>("h00") @[sequencer-master.scala 274:29] + e[_T_1649].base.vs3.valid <= UInt<1>("h00") @[sequencer-master.scala 275:29] + e[_T_1649].base.vd.valid <= UInt<1>("h00") @[sequencer-master.scala 276:28] + _T_1[_T_1649] <= UInt<1>("h01") @[sequencer-master.scala 188:42] + _T_2[_T_1649][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1649][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1649][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1649][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1649][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1649][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1649][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1649][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1649][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1649][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1649][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1649][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1649][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1649][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1649][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1649][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1649][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1649][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1649][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1649][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1649][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1649][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1649][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1649][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + e[_T_1649].last <= UInt<1>("h00") @[sequencer-master.scala 283:19] + io.master.update.valid[_T_1649] <= UInt<1>("h01") @[sequencer-master.scala 284:35] + e[_T_1649].active.vlu <= UInt<1>("h01") @[sequencer-master.scala 288:26] + e[_T_1649].fn.union <= io.op.bits.fn.union @[sequencer-master.scala 289:23] + node _T_2245 = eq(io.op.bits.base.vd.valid, UInt<1>("h00")) @[sequencer-master.scala 361:16] + node _T_2246 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_2247 = and(_T_2246, io.op.bits.base.vd.scalar) @[types-vxu.scala 119:37] + node _T_2248 = eq(_T_2247, UInt<1>("h00")) @[sequencer-master.scala 361:45] + node _T_2249 = or(_T_2245, _T_2248) @[sequencer-master.scala 361:42] + node _T_2250 = bits(reset, 0, 0) @[sequencer-master.scala 361:15] + node _T_2251 = or(_T_2249, _T_2250) @[sequencer-master.scala 361:15] + node _T_2252 = eq(_T_2251, UInt<1>("h00")) @[sequencer-master.scala 361:15] + when _T_2252 : @[sequencer-master.scala 361:15] + printf(clock, UInt<1>(1), "Assertion failed: iwindow.set.vd: vd should always be vector\n at sequencer-master.scala:361 assert(!io.op.bits.base.vd.valid || !io.op.bits.base.vd.is_scalar(), \"iwindow.set.vd: vd should always be vector\")\n") @[sequencer-master.scala 361:15] + stop(clock, UInt<1>(1), 1) @[sequencer-master.scala 361:15] + skip @[sequencer-master.scala 361:15] + when io.op.bits.base.vd.valid : @[sequencer-master.scala 362:41] + e[_T_1649].base.vd <- io.op.bits.base.vd @[sequencer-master.scala 363:24] + io.master.update.reg[_T_1649].vd.id <= io.op.bits.reg.vd.id @[sequencer-master.scala 364:41] + skip @[sequencer-master.scala 362:41] + node _T_2253 = or(_T_889[0], _T_1066[0]) @[sequencer-master.scala 161:31] + node _T_2254 = or(_T_2253, _T_1243[0]) @[sequencer-master.scala 161:49] + node _T_2255 = or(_T_2254, _T_1420[0]) @[sequencer-master.scala 161:67] + when _T_2255 : @[sequencer-master.scala 161:86] + _T_3[_T_1649][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2256 = or(_T_889[1], _T_1066[1]) @[sequencer-master.scala 161:31] + node _T_2257 = or(_T_2256, _T_1243[1]) @[sequencer-master.scala 161:49] + node _T_2258 = or(_T_2257, _T_1420[1]) @[sequencer-master.scala 161:67] + when _T_2258 : @[sequencer-master.scala 161:86] + _T_3[_T_1649][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2259 = or(_T_889[2], _T_1066[2]) @[sequencer-master.scala 161:31] + node _T_2260 = or(_T_2259, _T_1243[2]) @[sequencer-master.scala 161:49] + node _T_2261 = or(_T_2260, _T_1420[2]) @[sequencer-master.scala 161:67] + when _T_2261 : @[sequencer-master.scala 161:86] + _T_3[_T_1649][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2262 = or(_T_889[3], _T_1066[3]) @[sequencer-master.scala 161:31] + node _T_2263 = or(_T_2262, _T_1243[3]) @[sequencer-master.scala 161:49] + node _T_2264 = or(_T_2263, _T_1420[3]) @[sequencer-master.scala 161:67] + when _T_2264 : @[sequencer-master.scala 161:86] + _T_3[_T_1649][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2265 = or(_T_889[4], _T_1066[4]) @[sequencer-master.scala 161:31] + node _T_2266 = or(_T_2265, _T_1243[4]) @[sequencer-master.scala 161:49] + node _T_2267 = or(_T_2266, _T_1420[4]) @[sequencer-master.scala 161:67] + when _T_2267 : @[sequencer-master.scala 161:86] + _T_3[_T_1649][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2268 = or(_T_889[5], _T_1066[5]) @[sequencer-master.scala 161:31] + node _T_2269 = or(_T_2268, _T_1243[5]) @[sequencer-master.scala 161:49] + node _T_2270 = or(_T_2269, _T_1420[5]) @[sequencer-master.scala 161:67] + when _T_2270 : @[sequencer-master.scala 161:86] + _T_3[_T_1649][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2271 = or(_T_889[6], _T_1066[6]) @[sequencer-master.scala 161:31] + node _T_2272 = or(_T_2271, _T_1243[6]) @[sequencer-master.scala 161:49] + node _T_2273 = or(_T_2272, _T_1420[6]) @[sequencer-master.scala 161:67] + when _T_2273 : @[sequencer-master.scala 161:86] + _T_3[_T_1649][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2274 = or(_T_889[7], _T_1066[7]) @[sequencer-master.scala 161:31] + node _T_2275 = or(_T_2274, _T_1243[7]) @[sequencer-master.scala 161:49] + node _T_2276 = or(_T_2275, _T_1420[7]) @[sequencer-master.scala 161:67] + when _T_2276 : @[sequencer-master.scala 161:86] + _T_3[_T_1649][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + when _T_1597[0] : @[sequencer-master.scala 168:32] + _T_4[_T_1649][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[1] : @[sequencer-master.scala 168:32] + _T_4[_T_1649][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[2] : @[sequencer-master.scala 168:32] + _T_4[_T_1649][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[3] : @[sequencer-master.scala 168:32] + _T_4[_T_1649][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[4] : @[sequencer-master.scala 168:32] + _T_4[_T_1649][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[5] : @[sequencer-master.scala 168:32] + _T_4[_T_1649][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[6] : @[sequencer-master.scala 168:32] + _T_4[_T_1649][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[7] : @[sequencer-master.scala 168:32] + _T_4[_T_1649][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + e[_T_1649].rports <= UInt<1>("h00") @[sequencer-master.scala 230:21] + e[_T_1649].wport.sram <= UInt<1>("h00") @[sequencer-master.scala 231:25] + e[_T_1649].wport.pred <= UInt<1>("h00") @[sequencer-master.scala 232:25] + _T_1641 <= UInt<1>("h01") @[sequencer-master.scala 265:41] + _T_1643 <= _T_1651 @[sequencer-master.scala 265:66] + skip @[sequencer-master.scala 650:39] + when io.op.bits.active.vldx : @[sequencer-master.scala 651:39] + v[tail] <= UInt<1>("h01") @[sequencer-master.scala 267:35] + e[tail].rate <= UInt<1>("h00") @[sequencer-master.scala 271:19] + e[tail].base.vp.valid <= UInt<1>("h00") @[sequencer-master.scala 272:28] + e[tail].base.vs1.valid <= UInt<1>("h00") @[sequencer-master.scala 273:29] + e[tail].base.vs2.valid <= UInt<1>("h00") @[sequencer-master.scala 274:29] + e[tail].base.vs3.valid <= UInt<1>("h00") @[sequencer-master.scala 275:29] + e[tail].base.vd.valid <= UInt<1>("h00") @[sequencer-master.scala 276:28] + _T_1[tail] <= UInt<1>("h01") @[sequencer-master.scala 188:42] + _T_2[tail][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + e[tail].last <= UInt<1>("h00") @[sequencer-master.scala 283:19] + io.master.update.valid[tail] <= UInt<1>("h01") @[sequencer-master.scala 284:35] + e[tail].active.vgu <= UInt<1>("h01") @[sequencer-master.scala 288:26] + e[tail].fn.union <= io.op.bits.fn.union @[sequencer-master.scala 289:23] + when io.op.bits.base.vp.valid : @[sequencer-master.scala 320:41] + e[tail].base.vp <- io.op.bits.base.vp @[sequencer-master.scala 321:24] + io.master.update.reg[tail].vp.id <= io.op.bits.reg.vp.id @[sequencer-master.scala 322:41] + skip @[sequencer-master.scala 320:41] + when _T_181[0] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[1] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[2] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[3] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[4] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[5] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[6] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[7] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when io.op.bits.base.vs2.valid : @[sequencer-master.scala 328:47] + e[tail].base.vs1 <- io.op.bits.base.vs2 @[sequencer-master.scala 329:29] + io.master.update.reg[tail].vs1.id <= io.op.bits.reg.vs2.id @[sequencer-master.scala 330:47] + node _T_2277 = eq(io.op.bits.base.vs2.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_2278 = and(_T_2277, io.op.bits.base.vs2.scalar) @[types-vxu.scala 119:37] + when _T_2278 : @[sequencer-master.scala 331:55] + e[tail].sreg.ss1 <= io.op.bits.sreg.ss2 @[sequencer-master.scala 332:31] + skip @[sequencer-master.scala 331:55] + skip @[sequencer-master.scala 328:47] + when _T_535[0] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[1] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[2] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[3] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[4] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[5] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[6] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[7] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + e[tail].rports <= _T_1631 @[sequencer-master.scala 230:21] + e[tail].wport.sram <= UInt<1>("h00") @[sequencer-master.scala 231:25] + e[tail].wport.pred <= UInt<1>("h00") @[sequencer-master.scala 232:25] + v[_T_1645] <= UInt<1>("h01") @[sequencer-master.scala 267:35] + e[_T_1645].rate <= UInt<1>("h00") @[sequencer-master.scala 271:19] + e[_T_1645].base.vp.valid <= UInt<1>("h00") @[sequencer-master.scala 272:28] + e[_T_1645].base.vs1.valid <= UInt<1>("h00") @[sequencer-master.scala 273:29] + e[_T_1645].base.vs2.valid <= UInt<1>("h00") @[sequencer-master.scala 274:29] + e[_T_1645].base.vs3.valid <= UInt<1>("h00") @[sequencer-master.scala 275:29] + e[_T_1645].base.vd.valid <= UInt<1>("h00") @[sequencer-master.scala 276:28] + _T_1[_T_1645] <= UInt<1>("h01") @[sequencer-master.scala 188:42] + _T_2[_T_1645][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1645][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1645][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1645][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1645][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1645][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1645][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1645][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1645][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1645][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1645][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1645][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1645][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1645][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1645][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1645][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1645][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1645][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1645][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1645][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1645][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1645][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1645][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1645][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + e[_T_1645].last <= UInt<1>("h00") @[sequencer-master.scala 283:19] + io.master.update.valid[_T_1645] <= UInt<1>("h01") @[sequencer-master.scala 284:35] + e[_T_1645].active.vcu <= UInt<1>("h01") @[sequencer-master.scala 288:26] + e[_T_1645].fn.union <= io.op.bits.fn.union @[sequencer-master.scala 289:23] + e[_T_1645].rports <= UInt<1>("h00") @[sequencer-master.scala 230:21] + e[_T_1645].wport.sram <= UInt<1>("h00") @[sequencer-master.scala 231:25] + e[_T_1645].wport.pred <= UInt<1>("h00") @[sequencer-master.scala 232:25] + node _T_2279 = or(_T_889[0], _T_1066[0]) @[sequencer-master.scala 161:31] + node _T_2280 = or(_T_2279, _T_1243[0]) @[sequencer-master.scala 161:49] + node _T_2281 = or(_T_2280, _T_1420[0]) @[sequencer-master.scala 161:67] + when _T_2281 : @[sequencer-master.scala 161:86] + _T_3[_T_1645][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2282 = or(_T_889[1], _T_1066[1]) @[sequencer-master.scala 161:31] + node _T_2283 = or(_T_2282, _T_1243[1]) @[sequencer-master.scala 161:49] + node _T_2284 = or(_T_2283, _T_1420[1]) @[sequencer-master.scala 161:67] + when _T_2284 : @[sequencer-master.scala 161:86] + _T_3[_T_1645][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2285 = or(_T_889[2], _T_1066[2]) @[sequencer-master.scala 161:31] + node _T_2286 = or(_T_2285, _T_1243[2]) @[sequencer-master.scala 161:49] + node _T_2287 = or(_T_2286, _T_1420[2]) @[sequencer-master.scala 161:67] + when _T_2287 : @[sequencer-master.scala 161:86] + _T_3[_T_1645][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2288 = or(_T_889[3], _T_1066[3]) @[sequencer-master.scala 161:31] + node _T_2289 = or(_T_2288, _T_1243[3]) @[sequencer-master.scala 161:49] + node _T_2290 = or(_T_2289, _T_1420[3]) @[sequencer-master.scala 161:67] + when _T_2290 : @[sequencer-master.scala 161:86] + _T_3[_T_1645][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2291 = or(_T_889[4], _T_1066[4]) @[sequencer-master.scala 161:31] + node _T_2292 = or(_T_2291, _T_1243[4]) @[sequencer-master.scala 161:49] + node _T_2293 = or(_T_2292, _T_1420[4]) @[sequencer-master.scala 161:67] + when _T_2293 : @[sequencer-master.scala 161:86] + _T_3[_T_1645][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2294 = or(_T_889[5], _T_1066[5]) @[sequencer-master.scala 161:31] + node _T_2295 = or(_T_2294, _T_1243[5]) @[sequencer-master.scala 161:49] + node _T_2296 = or(_T_2295, _T_1420[5]) @[sequencer-master.scala 161:67] + when _T_2296 : @[sequencer-master.scala 161:86] + _T_3[_T_1645][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2297 = or(_T_889[6], _T_1066[6]) @[sequencer-master.scala 161:31] + node _T_2298 = or(_T_2297, _T_1243[6]) @[sequencer-master.scala 161:49] + node _T_2299 = or(_T_2298, _T_1420[6]) @[sequencer-master.scala 161:67] + when _T_2299 : @[sequencer-master.scala 161:86] + _T_3[_T_1645][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2300 = or(_T_889[7], _T_1066[7]) @[sequencer-master.scala 161:31] + node _T_2301 = or(_T_2300, _T_1243[7]) @[sequencer-master.scala 161:49] + node _T_2302 = or(_T_2301, _T_1420[7]) @[sequencer-master.scala 161:67] + when _T_2302 : @[sequencer-master.scala 161:86] + _T_3[_T_1645][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + when _T_1597[0] : @[sequencer-master.scala 168:32] + _T_4[_T_1645][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[1] : @[sequencer-master.scala 168:32] + _T_4[_T_1645][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[2] : @[sequencer-master.scala 168:32] + _T_4[_T_1645][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[3] : @[sequencer-master.scala 168:32] + _T_4[_T_1645][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[4] : @[sequencer-master.scala 168:32] + _T_4[_T_1645][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[5] : @[sequencer-master.scala 168:32] + _T_4[_T_1645][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[6] : @[sequencer-master.scala 168:32] + _T_4[_T_1645][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[7] : @[sequencer-master.scala 168:32] + _T_4[_T_1645][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + v[_T_1647] <= UInt<1>("h01") @[sequencer-master.scala 267:35] + e[_T_1647].rate <= UInt<1>("h00") @[sequencer-master.scala 271:19] + e[_T_1647].base.vp.valid <= UInt<1>("h00") @[sequencer-master.scala 272:28] + e[_T_1647].base.vs1.valid <= UInt<1>("h00") @[sequencer-master.scala 273:29] + e[_T_1647].base.vs2.valid <= UInt<1>("h00") @[sequencer-master.scala 274:29] + e[_T_1647].base.vs3.valid <= UInt<1>("h00") @[sequencer-master.scala 275:29] + e[_T_1647].base.vd.valid <= UInt<1>("h00") @[sequencer-master.scala 276:28] + _T_1[_T_1647] <= UInt<1>("h01") @[sequencer-master.scala 188:42] + _T_2[_T_1647][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1647][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1647][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1647][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1647][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1647][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1647][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1647][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1647][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1647][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1647][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1647][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1647][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1647][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1647][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1647][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1647][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1647][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1647][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1647][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1647][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1647][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1647][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1647][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + e[_T_1647].last <= UInt<1>("h00") @[sequencer-master.scala 283:19] + io.master.update.valid[_T_1647] <= UInt<1>("h01") @[sequencer-master.scala 284:35] + e[_T_1647].active.vlu <= UInt<1>("h01") @[sequencer-master.scala 288:26] + e[_T_1647].fn.union <= io.op.bits.fn.union @[sequencer-master.scala 289:23] + node _T_2303 = eq(io.op.bits.base.vd.valid, UInt<1>("h00")) @[sequencer-master.scala 361:16] + node _T_2304 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_2305 = and(_T_2304, io.op.bits.base.vd.scalar) @[types-vxu.scala 119:37] + node _T_2306 = eq(_T_2305, UInt<1>("h00")) @[sequencer-master.scala 361:45] + node _T_2307 = or(_T_2303, _T_2306) @[sequencer-master.scala 361:42] + node _T_2308 = bits(reset, 0, 0) @[sequencer-master.scala 361:15] + node _T_2309 = or(_T_2307, _T_2308) @[sequencer-master.scala 361:15] + node _T_2310 = eq(_T_2309, UInt<1>("h00")) @[sequencer-master.scala 361:15] + when _T_2310 : @[sequencer-master.scala 361:15] + printf(clock, UInt<1>(1), "Assertion failed: iwindow.set.vd: vd should always be vector\n at sequencer-master.scala:361 assert(!io.op.bits.base.vd.valid || !io.op.bits.base.vd.is_scalar(), \"iwindow.set.vd: vd should always be vector\")\n") @[sequencer-master.scala 361:15] + stop(clock, UInt<1>(1), 1) @[sequencer-master.scala 361:15] + skip @[sequencer-master.scala 361:15] + when io.op.bits.base.vd.valid : @[sequencer-master.scala 362:41] + e[_T_1647].base.vd <- io.op.bits.base.vd @[sequencer-master.scala 363:24] + io.master.update.reg[_T_1647].vd.id <= io.op.bits.reg.vd.id @[sequencer-master.scala 364:41] + skip @[sequencer-master.scala 362:41] + node _T_2311 = or(_T_889[0], _T_1066[0]) @[sequencer-master.scala 161:31] + node _T_2312 = or(_T_2311, _T_1243[0]) @[sequencer-master.scala 161:49] + node _T_2313 = or(_T_2312, _T_1420[0]) @[sequencer-master.scala 161:67] + when _T_2313 : @[sequencer-master.scala 161:86] + _T_3[_T_1647][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2314 = or(_T_889[1], _T_1066[1]) @[sequencer-master.scala 161:31] + node _T_2315 = or(_T_2314, _T_1243[1]) @[sequencer-master.scala 161:49] + node _T_2316 = or(_T_2315, _T_1420[1]) @[sequencer-master.scala 161:67] + when _T_2316 : @[sequencer-master.scala 161:86] + _T_3[_T_1647][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2317 = or(_T_889[2], _T_1066[2]) @[sequencer-master.scala 161:31] + node _T_2318 = or(_T_2317, _T_1243[2]) @[sequencer-master.scala 161:49] + node _T_2319 = or(_T_2318, _T_1420[2]) @[sequencer-master.scala 161:67] + when _T_2319 : @[sequencer-master.scala 161:86] + _T_3[_T_1647][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2320 = or(_T_889[3], _T_1066[3]) @[sequencer-master.scala 161:31] + node _T_2321 = or(_T_2320, _T_1243[3]) @[sequencer-master.scala 161:49] + node _T_2322 = or(_T_2321, _T_1420[3]) @[sequencer-master.scala 161:67] + when _T_2322 : @[sequencer-master.scala 161:86] + _T_3[_T_1647][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2323 = or(_T_889[4], _T_1066[4]) @[sequencer-master.scala 161:31] + node _T_2324 = or(_T_2323, _T_1243[4]) @[sequencer-master.scala 161:49] + node _T_2325 = or(_T_2324, _T_1420[4]) @[sequencer-master.scala 161:67] + when _T_2325 : @[sequencer-master.scala 161:86] + _T_3[_T_1647][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2326 = or(_T_889[5], _T_1066[5]) @[sequencer-master.scala 161:31] + node _T_2327 = or(_T_2326, _T_1243[5]) @[sequencer-master.scala 161:49] + node _T_2328 = or(_T_2327, _T_1420[5]) @[sequencer-master.scala 161:67] + when _T_2328 : @[sequencer-master.scala 161:86] + _T_3[_T_1647][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2329 = or(_T_889[6], _T_1066[6]) @[sequencer-master.scala 161:31] + node _T_2330 = or(_T_2329, _T_1243[6]) @[sequencer-master.scala 161:49] + node _T_2331 = or(_T_2330, _T_1420[6]) @[sequencer-master.scala 161:67] + when _T_2331 : @[sequencer-master.scala 161:86] + _T_3[_T_1647][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2332 = or(_T_889[7], _T_1066[7]) @[sequencer-master.scala 161:31] + node _T_2333 = or(_T_2332, _T_1243[7]) @[sequencer-master.scala 161:49] + node _T_2334 = or(_T_2333, _T_1420[7]) @[sequencer-master.scala 161:67] + when _T_2334 : @[sequencer-master.scala 161:86] + _T_3[_T_1647][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + when _T_1597[0] : @[sequencer-master.scala 168:32] + _T_4[_T_1647][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[1] : @[sequencer-master.scala 168:32] + _T_4[_T_1647][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[2] : @[sequencer-master.scala 168:32] + _T_4[_T_1647][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[3] : @[sequencer-master.scala 168:32] + _T_4[_T_1647][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[4] : @[sequencer-master.scala 168:32] + _T_4[_T_1647][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[5] : @[sequencer-master.scala 168:32] + _T_4[_T_1647][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[6] : @[sequencer-master.scala 168:32] + _T_4[_T_1647][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[7] : @[sequencer-master.scala 168:32] + _T_4[_T_1647][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + e[_T_1647].rports <= UInt<1>("h00") @[sequencer-master.scala 230:21] + e[_T_1647].wport.sram <= UInt<1>("h00") @[sequencer-master.scala 231:25] + e[_T_1647].wport.pred <= UInt<1>("h00") @[sequencer-master.scala 232:25] + _T_1641 <= UInt<1>("h01") @[sequencer-master.scala 265:41] + _T_1643 <= _T_1649 @[sequencer-master.scala 265:66] + skip @[sequencer-master.scala 651:39] + when io.op.bits.active.vstx : @[sequencer-master.scala 652:39] + v[tail] <= UInt<1>("h01") @[sequencer-master.scala 267:35] + e[tail].rate <= UInt<1>("h00") @[sequencer-master.scala 271:19] + e[tail].base.vp.valid <= UInt<1>("h00") @[sequencer-master.scala 272:28] + e[tail].base.vs1.valid <= UInt<1>("h00") @[sequencer-master.scala 273:29] + e[tail].base.vs2.valid <= UInt<1>("h00") @[sequencer-master.scala 274:29] + e[tail].base.vs3.valid <= UInt<1>("h00") @[sequencer-master.scala 275:29] + e[tail].base.vd.valid <= UInt<1>("h00") @[sequencer-master.scala 276:28] + _T_1[tail] <= UInt<1>("h01") @[sequencer-master.scala 188:42] + _T_2[tail][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + e[tail].last <= UInt<1>("h00") @[sequencer-master.scala 283:19] + io.master.update.valid[tail] <= UInt<1>("h01") @[sequencer-master.scala 284:35] + e[tail].active.vgu <= UInt<1>("h01") @[sequencer-master.scala 288:26] + e[tail].fn.union <= io.op.bits.fn.union @[sequencer-master.scala 289:23] + when io.op.bits.base.vp.valid : @[sequencer-master.scala 320:41] + e[tail].base.vp <- io.op.bits.base.vp @[sequencer-master.scala 321:24] + io.master.update.reg[tail].vp.id <= io.op.bits.reg.vp.id @[sequencer-master.scala 322:41] + skip @[sequencer-master.scala 320:41] + when _T_181[0] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[1] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[2] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[3] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[4] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[5] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[6] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[7] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when io.op.bits.base.vs2.valid : @[sequencer-master.scala 328:47] + e[tail].base.vs1 <- io.op.bits.base.vs2 @[sequencer-master.scala 329:29] + io.master.update.reg[tail].vs1.id <= io.op.bits.reg.vs2.id @[sequencer-master.scala 330:47] + node _T_2335 = eq(io.op.bits.base.vs2.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_2336 = and(_T_2335, io.op.bits.base.vs2.scalar) @[types-vxu.scala 119:37] + when _T_2336 : @[sequencer-master.scala 331:55] + e[tail].sreg.ss1 <= io.op.bits.sreg.ss2 @[sequencer-master.scala 332:31] + skip @[sequencer-master.scala 331:55] + skip @[sequencer-master.scala 328:47] + when _T_535[0] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[1] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[2] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[3] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[4] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[5] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[6] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_535[7] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + e[tail].rports <= _T_1631 @[sequencer-master.scala 230:21] + e[tail].wport.sram <= UInt<1>("h00") @[sequencer-master.scala 231:25] + e[tail].wport.pred <= UInt<1>("h00") @[sequencer-master.scala 232:25] + v[_T_1645] <= UInt<1>("h01") @[sequencer-master.scala 267:35] + e[_T_1645].rate <= UInt<1>("h00") @[sequencer-master.scala 271:19] + e[_T_1645].base.vp.valid <= UInt<1>("h00") @[sequencer-master.scala 272:28] + e[_T_1645].base.vs1.valid <= UInt<1>("h00") @[sequencer-master.scala 273:29] + e[_T_1645].base.vs2.valid <= UInt<1>("h00") @[sequencer-master.scala 274:29] + e[_T_1645].base.vs3.valid <= UInt<1>("h00") @[sequencer-master.scala 275:29] + e[_T_1645].base.vd.valid <= UInt<1>("h00") @[sequencer-master.scala 276:28] + _T_1[_T_1645] <= UInt<1>("h01") @[sequencer-master.scala 188:42] + _T_2[_T_1645][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1645][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1645][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1645][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1645][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1645][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1645][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1645][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1645][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1645][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1645][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1645][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1645][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1645][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1645][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1645][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1645][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1645][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1645][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1645][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1645][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1645][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1645][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1645][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + e[_T_1645].last <= UInt<1>("h00") @[sequencer-master.scala 283:19] + io.master.update.valid[_T_1645] <= UInt<1>("h01") @[sequencer-master.scala 284:35] + e[_T_1645].active.vcu <= UInt<1>("h01") @[sequencer-master.scala 288:26] + e[_T_1645].fn.union <= io.op.bits.fn.union @[sequencer-master.scala 289:23] + e[_T_1645].rports <= UInt<1>("h00") @[sequencer-master.scala 230:21] + e[_T_1645].wport.sram <= UInt<1>("h00") @[sequencer-master.scala 231:25] + e[_T_1645].wport.pred <= UInt<1>("h00") @[sequencer-master.scala 232:25] + v[_T_1647] <= UInt<1>("h01") @[sequencer-master.scala 267:35] + e[_T_1647].rate <= UInt<1>("h00") @[sequencer-master.scala 271:19] + e[_T_1647].base.vp.valid <= UInt<1>("h00") @[sequencer-master.scala 272:28] + e[_T_1647].base.vs1.valid <= UInt<1>("h00") @[sequencer-master.scala 273:29] + e[_T_1647].base.vs2.valid <= UInt<1>("h00") @[sequencer-master.scala 274:29] + e[_T_1647].base.vs3.valid <= UInt<1>("h00") @[sequencer-master.scala 275:29] + e[_T_1647].base.vd.valid <= UInt<1>("h00") @[sequencer-master.scala 276:28] + _T_1[_T_1647] <= UInt<1>("h01") @[sequencer-master.scala 188:42] + _T_2[_T_1647][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1647][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1647][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1647][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1647][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1647][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1647][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1647][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1647][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1647][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1647][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1647][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1647][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1647][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1647][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1647][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1647][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1647][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1647][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1647][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1647][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1647][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1647][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1647][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + e[_T_1647].last <= UInt<1>("h00") @[sequencer-master.scala 283:19] + io.master.update.valid[_T_1647] <= UInt<1>("h01") @[sequencer-master.scala 284:35] + e[_T_1647].active.vsu <= UInt<1>("h01") @[sequencer-master.scala 288:26] + e[_T_1647].fn.union <= io.op.bits.fn.union @[sequencer-master.scala 289:23] + when io.op.bits.base.vp.valid : @[sequencer-master.scala 320:41] + e[_T_1647].base.vp <- io.op.bits.base.vp @[sequencer-master.scala 321:24] + io.master.update.reg[_T_1647].vp.id <= io.op.bits.reg.vp.id @[sequencer-master.scala 322:41] + skip @[sequencer-master.scala 320:41] + when _T_181[0] : @[sequencer-master.scala 154:24] + _T_2[_T_1647][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[1] : @[sequencer-master.scala 154:24] + _T_2[_T_1647][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[2] : @[sequencer-master.scala 154:24] + _T_2[_T_1647][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[3] : @[sequencer-master.scala 154:24] + _T_2[_T_1647][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[4] : @[sequencer-master.scala 154:24] + _T_2[_T_1647][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[5] : @[sequencer-master.scala 154:24] + _T_2[_T_1647][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[6] : @[sequencer-master.scala 154:24] + _T_2[_T_1647][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[7] : @[sequencer-master.scala 154:24] + _T_2[_T_1647][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + node _T_2337 = eq(io.op.bits.base.vd.valid, UInt<1>("h00")) @[sequencer-master.scala 353:16] + node _T_2338 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_2339 = and(_T_2338, io.op.bits.base.vd.scalar) @[types-vxu.scala 119:37] + node _T_2340 = eq(_T_2339, UInt<1>("h00")) @[sequencer-master.scala 353:45] + node _T_2341 = or(_T_2337, _T_2340) @[sequencer-master.scala 353:42] + node _T_2342 = bits(reset, 0, 0) @[sequencer-master.scala 353:15] + node _T_2343 = or(_T_2341, _T_2342) @[sequencer-master.scala 353:15] + node _T_2344 = eq(_T_2343, UInt<1>("h00")) @[sequencer-master.scala 353:15] + when _T_2344 : @[sequencer-master.scala 353:15] + printf(clock, UInt<1>(1), "Assertion failed: iwindow.set.vd_as_vs1: vd should always be vector\n at sequencer-master.scala:353 assert(!io.op.bits.base.vd.valid || !io.op.bits.base.vd.is_scalar(), \"iwindow.set.vd_as_vs1: vd should always be vector\")\n") @[sequencer-master.scala 353:15] + stop(clock, UInt<1>(1), 1) @[sequencer-master.scala 353:15] + skip @[sequencer-master.scala 353:15] + when io.op.bits.base.vd.valid : @[sequencer-master.scala 354:41] + e[_T_1647].base.vs1 <- io.op.bits.base.vd @[sequencer-master.scala 355:25] + io.master.update.reg[_T_1647].vs1.id <= io.op.bits.reg.vd.id @[sequencer-master.scala 356:42] + skip @[sequencer-master.scala 354:41] + when _T_1597[0] : @[sequencer-master.scala 154:24] + _T_2[_T_1647][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_1597[1] : @[sequencer-master.scala 154:24] + _T_2[_T_1647][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_1597[2] : @[sequencer-master.scala 154:24] + _T_2[_T_1647][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_1597[3] : @[sequencer-master.scala 154:24] + _T_2[_T_1647][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_1597[4] : @[sequencer-master.scala 154:24] + _T_2[_T_1647][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_1597[5] : @[sequencer-master.scala 154:24] + _T_2[_T_1647][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_1597[6] : @[sequencer-master.scala 154:24] + _T_2[_T_1647][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_1597[7] : @[sequencer-master.scala 154:24] + _T_2[_T_1647][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + e[_T_1647].rports <= _T_1639 @[sequencer-master.scala 230:21] + e[_T_1647].wport.sram <= UInt<1>("h00") @[sequencer-master.scala 231:25] + e[_T_1647].wport.pred <= UInt<1>("h00") @[sequencer-master.scala 232:25] + _T_2[_T_1647][_T_1645] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + _T_1641 <= UInt<1>("h01") @[sequencer-master.scala 265:41] + _T_1643 <= _T_1649 @[sequencer-master.scala 265:66] + skip @[sequencer-master.scala 652:39] + when io.op.bits.active.vld : @[sequencer-master.scala 653:38] + v[tail] <= UInt<1>("h01") @[sequencer-master.scala 267:35] + e[tail].rate <= UInt<1>("h00") @[sequencer-master.scala 271:19] + e[tail].base.vp.valid <= UInt<1>("h00") @[sequencer-master.scala 272:28] + e[tail].base.vs1.valid <= UInt<1>("h00") @[sequencer-master.scala 273:29] + e[tail].base.vs2.valid <= UInt<1>("h00") @[sequencer-master.scala 274:29] + e[tail].base.vs3.valid <= UInt<1>("h00") @[sequencer-master.scala 275:29] + e[tail].base.vd.valid <= UInt<1>("h00") @[sequencer-master.scala 276:28] + _T_1[tail] <= UInt<1>("h01") @[sequencer-master.scala 188:42] + _T_2[tail][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + e[tail].last <= UInt<1>("h00") @[sequencer-master.scala 283:19] + io.master.update.valid[tail] <= UInt<1>("h01") @[sequencer-master.scala 284:35] + e[tail].active.vpu <= UInt<1>("h01") @[sequencer-master.scala 288:26] + e[tail].fn.union <= io.op.bits.fn.union @[sequencer-master.scala 289:23] + when io.op.bits.base.vp.valid : @[sequencer-master.scala 320:41] + e[tail].base.vp <- io.op.bits.base.vp @[sequencer-master.scala 321:24] + io.master.update.reg[tail].vp.id <= io.op.bits.reg.vp.id @[sequencer-master.scala 322:41] + skip @[sequencer-master.scala 320:41] + when _T_181[0] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[1] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[2] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[3] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[4] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[5] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[6] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[7] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + e[tail].rports <= UInt<1>("h00") @[sequencer-master.scala 230:21] + e[tail].wport.sram <= UInt<1>("h00") @[sequencer-master.scala 231:25] + e[tail].wport.pred <= UInt<1>("h00") @[sequencer-master.scala 232:25] + v[_T_1645] <= UInt<1>("h01") @[sequencer-master.scala 267:35] + e[_T_1645].rate <= UInt<1>("h00") @[sequencer-master.scala 271:19] + e[_T_1645].base.vp.valid <= UInt<1>("h00") @[sequencer-master.scala 272:28] + e[_T_1645].base.vs1.valid <= UInt<1>("h00") @[sequencer-master.scala 273:29] + e[_T_1645].base.vs2.valid <= UInt<1>("h00") @[sequencer-master.scala 274:29] + e[_T_1645].base.vs3.valid <= UInt<1>("h00") @[sequencer-master.scala 275:29] + e[_T_1645].base.vd.valid <= UInt<1>("h00") @[sequencer-master.scala 276:28] + _T_1[_T_1645] <= UInt<1>("h01") @[sequencer-master.scala 188:42] + _T_2[_T_1645][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1645][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1645][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1645][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1645][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1645][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1645][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1645][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1645][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1645][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1645][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1645][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1645][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1645][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1645][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1645][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1645][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1645][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1645][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1645][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1645][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1645][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1645][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1645][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + e[_T_1645].last <= UInt<1>("h00") @[sequencer-master.scala 283:19] + io.master.update.valid[_T_1645] <= UInt<1>("h01") @[sequencer-master.scala 284:35] + e[_T_1645].active.vcu <= UInt<1>("h01") @[sequencer-master.scala 288:26] + e[_T_1645].fn.union <= io.op.bits.fn.union @[sequencer-master.scala 289:23] + e[_T_1645].rports <= UInt<1>("h00") @[sequencer-master.scala 230:21] + e[_T_1645].wport.sram <= UInt<1>("h00") @[sequencer-master.scala 231:25] + e[_T_1645].wport.pred <= UInt<1>("h00") @[sequencer-master.scala 232:25] + node _T_2345 = or(_T_889[0], _T_1066[0]) @[sequencer-master.scala 161:31] + node _T_2346 = or(_T_2345, _T_1243[0]) @[sequencer-master.scala 161:49] + node _T_2347 = or(_T_2346, _T_1420[0]) @[sequencer-master.scala 161:67] + when _T_2347 : @[sequencer-master.scala 161:86] + _T_3[_T_1645][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2348 = or(_T_889[1], _T_1066[1]) @[sequencer-master.scala 161:31] + node _T_2349 = or(_T_2348, _T_1243[1]) @[sequencer-master.scala 161:49] + node _T_2350 = or(_T_2349, _T_1420[1]) @[sequencer-master.scala 161:67] + when _T_2350 : @[sequencer-master.scala 161:86] + _T_3[_T_1645][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2351 = or(_T_889[2], _T_1066[2]) @[sequencer-master.scala 161:31] + node _T_2352 = or(_T_2351, _T_1243[2]) @[sequencer-master.scala 161:49] + node _T_2353 = or(_T_2352, _T_1420[2]) @[sequencer-master.scala 161:67] + when _T_2353 : @[sequencer-master.scala 161:86] + _T_3[_T_1645][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2354 = or(_T_889[3], _T_1066[3]) @[sequencer-master.scala 161:31] + node _T_2355 = or(_T_2354, _T_1243[3]) @[sequencer-master.scala 161:49] + node _T_2356 = or(_T_2355, _T_1420[3]) @[sequencer-master.scala 161:67] + when _T_2356 : @[sequencer-master.scala 161:86] + _T_3[_T_1645][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2357 = or(_T_889[4], _T_1066[4]) @[sequencer-master.scala 161:31] + node _T_2358 = or(_T_2357, _T_1243[4]) @[sequencer-master.scala 161:49] + node _T_2359 = or(_T_2358, _T_1420[4]) @[sequencer-master.scala 161:67] + when _T_2359 : @[sequencer-master.scala 161:86] + _T_3[_T_1645][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2360 = or(_T_889[5], _T_1066[5]) @[sequencer-master.scala 161:31] + node _T_2361 = or(_T_2360, _T_1243[5]) @[sequencer-master.scala 161:49] + node _T_2362 = or(_T_2361, _T_1420[5]) @[sequencer-master.scala 161:67] + when _T_2362 : @[sequencer-master.scala 161:86] + _T_3[_T_1645][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2363 = or(_T_889[6], _T_1066[6]) @[sequencer-master.scala 161:31] + node _T_2364 = or(_T_2363, _T_1243[6]) @[sequencer-master.scala 161:49] + node _T_2365 = or(_T_2364, _T_1420[6]) @[sequencer-master.scala 161:67] + when _T_2365 : @[sequencer-master.scala 161:86] + _T_3[_T_1645][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2366 = or(_T_889[7], _T_1066[7]) @[sequencer-master.scala 161:31] + node _T_2367 = or(_T_2366, _T_1243[7]) @[sequencer-master.scala 161:49] + node _T_2368 = or(_T_2367, _T_1420[7]) @[sequencer-master.scala 161:67] + when _T_2368 : @[sequencer-master.scala 161:86] + _T_3[_T_1645][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + when _T_1597[0] : @[sequencer-master.scala 168:32] + _T_4[_T_1645][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[1] : @[sequencer-master.scala 168:32] + _T_4[_T_1645][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[2] : @[sequencer-master.scala 168:32] + _T_4[_T_1645][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[3] : @[sequencer-master.scala 168:32] + _T_4[_T_1645][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[4] : @[sequencer-master.scala 168:32] + _T_4[_T_1645][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[5] : @[sequencer-master.scala 168:32] + _T_4[_T_1645][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[6] : @[sequencer-master.scala 168:32] + _T_4[_T_1645][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[7] : @[sequencer-master.scala 168:32] + _T_4[_T_1645][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + v[_T_1647] <= UInt<1>("h01") @[sequencer-master.scala 267:35] + e[_T_1647].rate <= UInt<1>("h00") @[sequencer-master.scala 271:19] + e[_T_1647].base.vp.valid <= UInt<1>("h00") @[sequencer-master.scala 272:28] + e[_T_1647].base.vs1.valid <= UInt<1>("h00") @[sequencer-master.scala 273:29] + e[_T_1647].base.vs2.valid <= UInt<1>("h00") @[sequencer-master.scala 274:29] + e[_T_1647].base.vs3.valid <= UInt<1>("h00") @[sequencer-master.scala 275:29] + e[_T_1647].base.vd.valid <= UInt<1>("h00") @[sequencer-master.scala 276:28] + _T_1[_T_1647] <= UInt<1>("h01") @[sequencer-master.scala 188:42] + _T_2[_T_1647][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1647][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1647][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1647][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1647][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1647][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1647][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1647][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1647][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1647][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1647][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1647][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1647][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1647][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1647][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1647][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1647][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1647][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1647][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1647][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1647][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1647][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1647][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1647][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + e[_T_1647].last <= UInt<1>("h00") @[sequencer-master.scala 283:19] + io.master.update.valid[_T_1647] <= UInt<1>("h01") @[sequencer-master.scala 284:35] + e[_T_1647].active.vlu <= UInt<1>("h01") @[sequencer-master.scala 288:26] + e[_T_1647].fn.union <= io.op.bits.fn.union @[sequencer-master.scala 289:23] + node _T_2369 = eq(io.op.bits.base.vd.valid, UInt<1>("h00")) @[sequencer-master.scala 361:16] + node _T_2370 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_2371 = and(_T_2370, io.op.bits.base.vd.scalar) @[types-vxu.scala 119:37] + node _T_2372 = eq(_T_2371, UInt<1>("h00")) @[sequencer-master.scala 361:45] + node _T_2373 = or(_T_2369, _T_2372) @[sequencer-master.scala 361:42] + node _T_2374 = bits(reset, 0, 0) @[sequencer-master.scala 361:15] + node _T_2375 = or(_T_2373, _T_2374) @[sequencer-master.scala 361:15] + node _T_2376 = eq(_T_2375, UInt<1>("h00")) @[sequencer-master.scala 361:15] + when _T_2376 : @[sequencer-master.scala 361:15] + printf(clock, UInt<1>(1), "Assertion failed: iwindow.set.vd: vd should always be vector\n at sequencer-master.scala:361 assert(!io.op.bits.base.vd.valid || !io.op.bits.base.vd.is_scalar(), \"iwindow.set.vd: vd should always be vector\")\n") @[sequencer-master.scala 361:15] + stop(clock, UInt<1>(1), 1) @[sequencer-master.scala 361:15] + skip @[sequencer-master.scala 361:15] + when io.op.bits.base.vd.valid : @[sequencer-master.scala 362:41] + e[_T_1647].base.vd <- io.op.bits.base.vd @[sequencer-master.scala 363:24] + io.master.update.reg[_T_1647].vd.id <= io.op.bits.reg.vd.id @[sequencer-master.scala 364:41] + skip @[sequencer-master.scala 362:41] + node _T_2377 = or(_T_889[0], _T_1066[0]) @[sequencer-master.scala 161:31] + node _T_2378 = or(_T_2377, _T_1243[0]) @[sequencer-master.scala 161:49] + node _T_2379 = or(_T_2378, _T_1420[0]) @[sequencer-master.scala 161:67] + when _T_2379 : @[sequencer-master.scala 161:86] + _T_3[_T_1647][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2380 = or(_T_889[1], _T_1066[1]) @[sequencer-master.scala 161:31] + node _T_2381 = or(_T_2380, _T_1243[1]) @[sequencer-master.scala 161:49] + node _T_2382 = or(_T_2381, _T_1420[1]) @[sequencer-master.scala 161:67] + when _T_2382 : @[sequencer-master.scala 161:86] + _T_3[_T_1647][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2383 = or(_T_889[2], _T_1066[2]) @[sequencer-master.scala 161:31] + node _T_2384 = or(_T_2383, _T_1243[2]) @[sequencer-master.scala 161:49] + node _T_2385 = or(_T_2384, _T_1420[2]) @[sequencer-master.scala 161:67] + when _T_2385 : @[sequencer-master.scala 161:86] + _T_3[_T_1647][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2386 = or(_T_889[3], _T_1066[3]) @[sequencer-master.scala 161:31] + node _T_2387 = or(_T_2386, _T_1243[3]) @[sequencer-master.scala 161:49] + node _T_2388 = or(_T_2387, _T_1420[3]) @[sequencer-master.scala 161:67] + when _T_2388 : @[sequencer-master.scala 161:86] + _T_3[_T_1647][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2389 = or(_T_889[4], _T_1066[4]) @[sequencer-master.scala 161:31] + node _T_2390 = or(_T_2389, _T_1243[4]) @[sequencer-master.scala 161:49] + node _T_2391 = or(_T_2390, _T_1420[4]) @[sequencer-master.scala 161:67] + when _T_2391 : @[sequencer-master.scala 161:86] + _T_3[_T_1647][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2392 = or(_T_889[5], _T_1066[5]) @[sequencer-master.scala 161:31] + node _T_2393 = or(_T_2392, _T_1243[5]) @[sequencer-master.scala 161:49] + node _T_2394 = or(_T_2393, _T_1420[5]) @[sequencer-master.scala 161:67] + when _T_2394 : @[sequencer-master.scala 161:86] + _T_3[_T_1647][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2395 = or(_T_889[6], _T_1066[6]) @[sequencer-master.scala 161:31] + node _T_2396 = or(_T_2395, _T_1243[6]) @[sequencer-master.scala 161:49] + node _T_2397 = or(_T_2396, _T_1420[6]) @[sequencer-master.scala 161:67] + when _T_2397 : @[sequencer-master.scala 161:86] + _T_3[_T_1647][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + node _T_2398 = or(_T_889[7], _T_1066[7]) @[sequencer-master.scala 161:31] + node _T_2399 = or(_T_2398, _T_1243[7]) @[sequencer-master.scala 161:49] + node _T_2400 = or(_T_2399, _T_1420[7]) @[sequencer-master.scala 161:67] + when _T_2400 : @[sequencer-master.scala 161:86] + _T_3[_T_1647][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 132:52] + skip @[sequencer-master.scala 161:86] + when _T_1597[0] : @[sequencer-master.scala 168:32] + _T_4[_T_1647][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[1] : @[sequencer-master.scala 168:32] + _T_4[_T_1647][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[2] : @[sequencer-master.scala 168:32] + _T_4[_T_1647][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[3] : @[sequencer-master.scala 168:32] + _T_4[_T_1647][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[4] : @[sequencer-master.scala 168:32] + _T_4[_T_1647][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[5] : @[sequencer-master.scala 168:32] + _T_4[_T_1647][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[6] : @[sequencer-master.scala 168:32] + _T_4[_T_1647][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + when _T_1597[7] : @[sequencer-master.scala 168:32] + _T_4[_T_1647][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 133:52] + skip @[sequencer-master.scala 168:32] + e[_T_1647].rports <= UInt<1>("h00") @[sequencer-master.scala 230:21] + e[_T_1647].wport.sram <= UInt<1>("h00") @[sequencer-master.scala 231:25] + e[_T_1647].wport.pred <= UInt<1>("h00") @[sequencer-master.scala 232:25] + _T_1641 <= UInt<1>("h01") @[sequencer-master.scala 265:41] + _T_1643 <= _T_1649 @[sequencer-master.scala 265:66] + skip @[sequencer-master.scala 653:38] + when io.op.bits.active.vst : @[sequencer-master.scala 654:38] + v[tail] <= UInt<1>("h01") @[sequencer-master.scala 267:35] + e[tail].rate <= UInt<1>("h00") @[sequencer-master.scala 271:19] + e[tail].base.vp.valid <= UInt<1>("h00") @[sequencer-master.scala 272:28] + e[tail].base.vs1.valid <= UInt<1>("h00") @[sequencer-master.scala 273:29] + e[tail].base.vs2.valid <= UInt<1>("h00") @[sequencer-master.scala 274:29] + e[tail].base.vs3.valid <= UInt<1>("h00") @[sequencer-master.scala 275:29] + e[tail].base.vd.valid <= UInt<1>("h00") @[sequencer-master.scala 276:28] + _T_1[tail] <= UInt<1>("h01") @[sequencer-master.scala 188:42] + _T_2[tail][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[tail][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[tail][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[tail][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + e[tail].last <= UInt<1>("h00") @[sequencer-master.scala 283:19] + io.master.update.valid[tail] <= UInt<1>("h01") @[sequencer-master.scala 284:35] + e[tail].active.vpu <= UInt<1>("h01") @[sequencer-master.scala 288:26] + e[tail].fn.union <= io.op.bits.fn.union @[sequencer-master.scala 289:23] + when io.op.bits.base.vp.valid : @[sequencer-master.scala 320:41] + e[tail].base.vp <- io.op.bits.base.vp @[sequencer-master.scala 321:24] + io.master.update.reg[tail].vp.id <= io.op.bits.reg.vp.id @[sequencer-master.scala 322:41] + skip @[sequencer-master.scala 320:41] + when _T_181[0] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[1] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[2] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[3] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[4] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[5] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[6] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[7] : @[sequencer-master.scala 154:24] + _T_2[tail][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + e[tail].rports <= UInt<1>("h00") @[sequencer-master.scala 230:21] + e[tail].wport.sram <= UInt<1>("h00") @[sequencer-master.scala 231:25] + e[tail].wport.pred <= UInt<1>("h00") @[sequencer-master.scala 232:25] + v[_T_1645] <= UInt<1>("h01") @[sequencer-master.scala 267:35] + e[_T_1645].rate <= UInt<1>("h00") @[sequencer-master.scala 271:19] + e[_T_1645].base.vp.valid <= UInt<1>("h00") @[sequencer-master.scala 272:28] + e[_T_1645].base.vs1.valid <= UInt<1>("h00") @[sequencer-master.scala 273:29] + e[_T_1645].base.vs2.valid <= UInt<1>("h00") @[sequencer-master.scala 274:29] + e[_T_1645].base.vs3.valid <= UInt<1>("h00") @[sequencer-master.scala 275:29] + e[_T_1645].base.vd.valid <= UInt<1>("h00") @[sequencer-master.scala 276:28] + _T_1[_T_1645] <= UInt<1>("h01") @[sequencer-master.scala 188:42] + _T_2[_T_1645][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1645][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1645][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1645][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1645][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1645][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1645][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1645][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1645][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1645][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1645][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1645][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1645][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1645][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1645][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1645][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1645][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1645][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1645][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1645][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1645][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1645][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1645][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1645][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + e[_T_1645].last <= UInt<1>("h00") @[sequencer-master.scala 283:19] + io.master.update.valid[_T_1645] <= UInt<1>("h01") @[sequencer-master.scala 284:35] + e[_T_1645].active.vcu <= UInt<1>("h01") @[sequencer-master.scala 288:26] + e[_T_1645].fn.union <= io.op.bits.fn.union @[sequencer-master.scala 289:23] + e[_T_1645].rports <= UInt<1>("h00") @[sequencer-master.scala 230:21] + e[_T_1645].wport.sram <= UInt<1>("h00") @[sequencer-master.scala 231:25] + e[_T_1645].wport.pred <= UInt<1>("h00") @[sequencer-master.scala 232:25] + v[_T_1647] <= UInt<1>("h01") @[sequencer-master.scala 267:35] + e[_T_1647].rate <= UInt<1>("h00") @[sequencer-master.scala 271:19] + e[_T_1647].base.vp.valid <= UInt<1>("h00") @[sequencer-master.scala 272:28] + e[_T_1647].base.vs1.valid <= UInt<1>("h00") @[sequencer-master.scala 273:29] + e[_T_1647].base.vs2.valid <= UInt<1>("h00") @[sequencer-master.scala 274:29] + e[_T_1647].base.vs3.valid <= UInt<1>("h00") @[sequencer-master.scala 275:29] + e[_T_1647].base.vd.valid <= UInt<1>("h00") @[sequencer-master.scala 276:28] + _T_1[_T_1647] <= UInt<1>("h01") @[sequencer-master.scala 188:42] + _T_2[_T_1647][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1647][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1647][UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1647][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1647][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1647][UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1647][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1647][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1647][UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1647][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1647][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1647][UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1647][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1647][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1647][UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1647][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1647][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1647][UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1647][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1647][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1647][UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_2[_T_1647][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[_T_1647][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[_T_1647][UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + e[_T_1647].last <= UInt<1>("h00") @[sequencer-master.scala 283:19] + io.master.update.valid[_T_1647] <= UInt<1>("h01") @[sequencer-master.scala 284:35] + e[_T_1647].active.vsu <= UInt<1>("h01") @[sequencer-master.scala 288:26] + e[_T_1647].fn.union <= io.op.bits.fn.union @[sequencer-master.scala 289:23] + when io.op.bits.base.vp.valid : @[sequencer-master.scala 320:41] + e[_T_1647].base.vp <- io.op.bits.base.vp @[sequencer-master.scala 321:24] + io.master.update.reg[_T_1647].vp.id <= io.op.bits.reg.vp.id @[sequencer-master.scala 322:41] + skip @[sequencer-master.scala 320:41] + when _T_181[0] : @[sequencer-master.scala 154:24] + _T_2[_T_1647][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[1] : @[sequencer-master.scala 154:24] + _T_2[_T_1647][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[2] : @[sequencer-master.scala 154:24] + _T_2[_T_1647][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[3] : @[sequencer-master.scala 154:24] + _T_2[_T_1647][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[4] : @[sequencer-master.scala 154:24] + _T_2[_T_1647][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[5] : @[sequencer-master.scala 154:24] + _T_2[_T_1647][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[6] : @[sequencer-master.scala 154:24] + _T_2[_T_1647][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_181[7] : @[sequencer-master.scala 154:24] + _T_2[_T_1647][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + node _T_2401 = eq(io.op.bits.base.vd.valid, UInt<1>("h00")) @[sequencer-master.scala 353:16] + node _T_2402 = eq(io.op.bits.base.vd.pred, UInt<1>("h00")) @[types-vxu.scala 119:31] + node _T_2403 = and(_T_2402, io.op.bits.base.vd.scalar) @[types-vxu.scala 119:37] + node _T_2404 = eq(_T_2403, UInt<1>("h00")) @[sequencer-master.scala 353:45] + node _T_2405 = or(_T_2401, _T_2404) @[sequencer-master.scala 353:42] + node _T_2406 = bits(reset, 0, 0) @[sequencer-master.scala 353:15] + node _T_2407 = or(_T_2405, _T_2406) @[sequencer-master.scala 353:15] + node _T_2408 = eq(_T_2407, UInt<1>("h00")) @[sequencer-master.scala 353:15] + when _T_2408 : @[sequencer-master.scala 353:15] + printf(clock, UInt<1>(1), "Assertion failed: iwindow.set.vd_as_vs1: vd should always be vector\n at sequencer-master.scala:353 assert(!io.op.bits.base.vd.valid || !io.op.bits.base.vd.is_scalar(), \"iwindow.set.vd_as_vs1: vd should always be vector\")\n") @[sequencer-master.scala 353:15] + stop(clock, UInt<1>(1), 1) @[sequencer-master.scala 353:15] + skip @[sequencer-master.scala 353:15] + when io.op.bits.base.vd.valid : @[sequencer-master.scala 354:41] + e[_T_1647].base.vs1 <- io.op.bits.base.vd @[sequencer-master.scala 355:25] + io.master.update.reg[_T_1647].vs1.id <= io.op.bits.reg.vd.id @[sequencer-master.scala 356:42] + skip @[sequencer-master.scala 354:41] + when _T_1597[0] : @[sequencer-master.scala 154:24] + _T_2[_T_1647][UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_1597[1] : @[sequencer-master.scala 154:24] + _T_2[_T_1647][UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_1597[2] : @[sequencer-master.scala 154:24] + _T_2[_T_1647][UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_1597[3] : @[sequencer-master.scala 154:24] + _T_2[_T_1647][UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_1597[4] : @[sequencer-master.scala 154:24] + _T_2[_T_1647][UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_1597[5] : @[sequencer-master.scala 154:24] + _T_2[_T_1647][UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_1597[6] : @[sequencer-master.scala 154:24] + _T_2[_T_1647][UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + when _T_1597[7] : @[sequencer-master.scala 154:24] + _T_2[_T_1647][UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + skip @[sequencer-master.scala 154:24] + e[_T_1647].rports <= _T_1639 @[sequencer-master.scala 230:21] + e[_T_1647].wport.sram <= UInt<1>("h00") @[sequencer-master.scala 231:25] + e[_T_1647].wport.pred <= UInt<1>("h00") @[sequencer-master.scala 232:25] + _T_2[_T_1647][_T_1645] <= UInt<1>("h01") @[sequencer-master.scala 131:52] + _T_1641 <= UInt<1>("h01") @[sequencer-master.scala 265:41] + _T_1643 <= _T_1649 @[sequencer-master.scala 265:66] + skip @[sequencer-master.scala 654:38] + skip @[sequencer-master.scala 639:27] + node _T_2409 = eq(maybe_full, UInt<1>("h00")) @[sequencer-master.scala 389:15] + node _T_2410 = eq(head, tail) @[sequencer-master.scala 389:36] + node _T_2411 = and(_T_2409, _T_2410) @[sequencer-master.scala 389:27] + node _T_2412 = sub(head, tail) @[sequencer-master.scala 389:52] + node _T_2413 = tail(_T_2412, 1) @[sequencer-master.scala 389:52] + node _T_2414 = cat(_T_2411, _T_2413) @[Cat.scala 30:58] + io.debug.empty <= _T_2414 @[sequencer-master.scala 394:22] + node _T_2415 = geq(_T_2414, UInt<1>("h01")) @[sequencer-master.scala 397:14] + node _T_2416 = or(io.op.bits.active.vint, io.op.bits.active.vipred) @[sequencer-master.scala 397:37] + node _T_2417 = or(_T_2416, io.op.bits.active.vimul) @[sequencer-master.scala 397:49] + node _T_2418 = or(_T_2417, io.op.bits.active.vfma) @[sequencer-master.scala 397:60] + node _T_2419 = or(_T_2418, io.op.bits.active.vfcmp) @[sequencer-master.scala 397:70] + node _T_2420 = or(_T_2419, io.op.bits.active.vfconv) @[sequencer-master.scala 397:81] + node _T_2421 = or(_T_2420, io.op.bits.active.vrpred) @[sequencer-master.scala 397:93] + node _T_2422 = or(_T_2421, io.op.bits.active.vrfirst) @[sequencer-master.scala 397:105] + node _T_2423 = and(_T_2415, _T_2422) @[sequencer-master.scala 397:26] + node _T_2424 = geq(_T_2414, UInt<2>("h02")) @[sequencer-master.scala 398:14] + node _T_2425 = or(io.op.bits.active.vidiv, io.op.bits.active.vfdiv) @[sequencer-master.scala 398:38] + node _T_2426 = and(_T_2424, _T_2425) @[sequencer-master.scala 398:26] + node _T_2427 = or(_T_2423, _T_2426) @[sequencer-master.scala 397:119] + node _T_2428 = geq(_T_2414, UInt<2>("h03")) @[sequencer-master.scala 399:14] + node _T_2429 = or(io.op.bits.active.vld, io.op.bits.active.vst) @[sequencer-master.scala 399:36] + node _T_2430 = or(_T_2429, io.op.bits.active.vldx) @[sequencer-master.scala 399:45] + node _T_2431 = or(_T_2430, io.op.bits.active.vstx) @[sequencer-master.scala 399:55] + node _T_2432 = and(_T_2428, _T_2431) @[sequencer-master.scala 399:26] + node _T_2433 = or(_T_2427, _T_2432) @[sequencer-master.scala 398:50] + node _T_2434 = geq(_T_2414, UInt<3>("h04")) @[sequencer-master.scala 400:14] + node _T_2435 = and(_T_2434, io.op.bits.active.vamo) @[sequencer-master.scala 400:26] + node _T_2436 = or(_T_2433, _T_2435) @[sequencer-master.scala 399:66] + io.op.ready <= _T_2436 @[sequencer-master.scala 416:19] + when _T_1641 : @[sequencer-master.scala 418:26] + tail <= _T_1643 @[sequencer-master.scala 419:14] + maybe_full <= UInt<1>("h01") @[sequencer-master.scala 420:20] + skip @[sequencer-master.scala 418:26] + when _T_1640 : @[sequencer-master.scala 422:26] + head <= _T_1642 @[sequencer-master.scala 423:14] + maybe_full <= UInt<1>("h00") @[sequencer-master.scala 424:20] + skip @[sequencer-master.scala 422:26] + node _T_2437 = add(tail, UInt<3>("h07")) @[util.scala 94:11] + node _T_2438 = tail(_T_2437, 1) @[util.scala 94:11] + node _T_2439 = add(head, UInt<1>("h01")) @[util.scala 94:11] + node _T_2440 = tail(_T_2439, 1) @[util.scala 94:11] + wire _T_2441 : UInt<1> @[sequencer-master.scala 430:25] + _T_2441 is invalid @[sequencer-master.scala 430:25] + _T_2441 <= UInt<1>("h00") @[sequencer-master.scala 432:15] + when io.vf.stop : @[sequencer-master.scala 433:25] + e[_T_2438].last <= UInt<1>("h01") @[sequencer-master.scala 293:19] + node _T_2442 = eq(io.pending.all, UInt<1>("h00")) @[sequencer-master.scala 435:20] + _T_2441 <= _T_2442 @[sequencer-master.scala 435:17] + skip @[sequencer-master.scala 433:25] + node _T_2443 = and(v[head], io.master.clear[head]) @[sequencer-master.scala 438:21] + when _T_2443 : @[sequencer-master.scala 438:47] + v[head] <= UInt<1>("h00") @[sequencer-master.scala 372:35] + wire _T_2444 : {viu : UInt<1>, vipu : UInt<1>, vimu : UInt<1>, vidu : UInt<1>, vfmu : UInt<1>, vfdu : UInt<1>, vfcu : UInt<1>, vfvu : UInt<1>, vrpu : UInt<1>, vrfu : UInt<1>, vpu : UInt<1>, vgu : UInt<1>, vcu : UInt<1>, vlu : UInt<1>, vsu : UInt<1>, vqu : UInt<1>} @[sequencer-master.scala 373:76] + _T_2444 is invalid @[sequencer-master.scala 373:76] + wire _T_2445 : UInt<16> + _T_2445 is invalid + _T_2445 <= UInt<1>("h00") + node _T_2446 = bits(_T_2445, 0, 0) @[sequencer-master.scala 373:76] + _T_2444.vqu <= _T_2446 @[sequencer-master.scala 373:76] + node _T_2447 = bits(_T_2445, 1, 1) @[sequencer-master.scala 373:76] + _T_2444.vsu <= _T_2447 @[sequencer-master.scala 373:76] + node _T_2448 = bits(_T_2445, 2, 2) @[sequencer-master.scala 373:76] + _T_2444.vlu <= _T_2448 @[sequencer-master.scala 373:76] + node _T_2449 = bits(_T_2445, 3, 3) @[sequencer-master.scala 373:76] + _T_2444.vcu <= _T_2449 @[sequencer-master.scala 373:76] + node _T_2450 = bits(_T_2445, 4, 4) @[sequencer-master.scala 373:76] + _T_2444.vgu <= _T_2450 @[sequencer-master.scala 373:76] + node _T_2451 = bits(_T_2445, 5, 5) @[sequencer-master.scala 373:76] + _T_2444.vpu <= _T_2451 @[sequencer-master.scala 373:76] + node _T_2452 = bits(_T_2445, 6, 6) @[sequencer-master.scala 373:76] + _T_2444.vrfu <= _T_2452 @[sequencer-master.scala 373:76] + node _T_2453 = bits(_T_2445, 7, 7) @[sequencer-master.scala 373:76] + _T_2444.vrpu <= _T_2453 @[sequencer-master.scala 373:76] + node _T_2454 = bits(_T_2445, 8, 8) @[sequencer-master.scala 373:76] + _T_2444.vfvu <= _T_2454 @[sequencer-master.scala 373:76] + node _T_2455 = bits(_T_2445, 9, 9) @[sequencer-master.scala 373:76] + _T_2444.vfcu <= _T_2455 @[sequencer-master.scala 373:76] + node _T_2456 = bits(_T_2445, 10, 10) @[sequencer-master.scala 373:76] + _T_2444.vfdu <= _T_2456 @[sequencer-master.scala 373:76] + node _T_2457 = bits(_T_2445, 11, 11) @[sequencer-master.scala 373:76] + _T_2444.vfmu <= _T_2457 @[sequencer-master.scala 373:76] + node _T_2458 = bits(_T_2445, 12, 12) @[sequencer-master.scala 373:76] + _T_2444.vidu <= _T_2458 @[sequencer-master.scala 373:76] + node _T_2459 = bits(_T_2445, 13, 13) @[sequencer-master.scala 373:76] + _T_2444.vimu <= _T_2459 @[sequencer-master.scala 373:76] + node _T_2460 = bits(_T_2445, 14, 14) @[sequencer-master.scala 373:76] + _T_2444.vipu <= _T_2460 @[sequencer-master.scala 373:76] + node _T_2461 = bits(_T_2445, 15, 15) @[sequencer-master.scala 373:76] + _T_2444.viu <= _T_2461 @[sequencer-master.scala 373:76] + e[head].active <- _T_2444 @[sequencer-master.scala 373:43] + _T_1[UInt<1>("h00")] <= UInt<1>("h01") @[sequencer-master.scala 188:42] + _T_2[UInt<1>("h00")][head] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[UInt<1>("h00")][head] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[UInt<1>("h00")][head] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_1[UInt<1>("h01")] <= UInt<1>("h01") @[sequencer-master.scala 188:42] + _T_2[UInt<1>("h01")][head] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[UInt<1>("h01")][head] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[UInt<1>("h01")][head] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_1[UInt<2>("h02")] <= UInt<1>("h01") @[sequencer-master.scala 188:42] + _T_2[UInt<2>("h02")][head] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[UInt<2>("h02")][head] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[UInt<2>("h02")][head] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_1[UInt<2>("h03")] <= UInt<1>("h01") @[sequencer-master.scala 188:42] + _T_2[UInt<2>("h03")][head] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[UInt<2>("h03")][head] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[UInt<2>("h03")][head] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_1[UInt<3>("h04")] <= UInt<1>("h01") @[sequencer-master.scala 188:42] + _T_2[UInt<3>("h04")][head] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[UInt<3>("h04")][head] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[UInt<3>("h04")][head] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_1[UInt<3>("h05")] <= UInt<1>("h01") @[sequencer-master.scala 188:42] + _T_2[UInt<3>("h05")][head] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[UInt<3>("h05")][head] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[UInt<3>("h05")][head] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_1[UInt<3>("h06")] <= UInt<1>("h01") @[sequencer-master.scala 188:42] + _T_2[UInt<3>("h06")][head] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[UInt<3>("h06")][head] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[UInt<3>("h06")][head] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_1[UInt<3>("h07")] <= UInt<1>("h01") @[sequencer-master.scala 188:42] + _T_2[UInt<3>("h07")][head] <= UInt<1>("h00") @[sequencer-master.scala 183:52] + _T_3[UInt<3>("h07")][head] <= UInt<1>("h00") @[sequencer-master.scala 184:52] + _T_4[UInt<3>("h07")][head] <= UInt<1>("h00") @[sequencer-master.scala 185:52] + _T_1640 <= UInt<1>("h01") @[sequencer-master.scala 264:41] + _T_1642 <= _T_2440 @[sequencer-master.scala 264:66] + node _T_2462 = eq(_T_2440, tail) @[sequencer-master.scala 441:58] + node _T_2463 = and(io.vf.stop, _T_2462) @[sequencer-master.scala 441:47] + node _T_2464 = or(e[head].last, _T_2463) @[sequencer-master.scala 441:33] + _T_2441 <= _T_2464 @[sequencer-master.scala 441:17] + skip @[sequencer-master.scala 438:47] + reg _T_2465 : UInt<1>, clock @[sequencer-master.scala 444:24] + _T_2465 <= _T_2441 @[sequencer-master.scala 444:24] + io.vf.last <= _T_2465 @[sequencer-master.scala 444:18] + node _T_2466 = and(v[0], e[0].active.vcu) @[sequencer-master.scala 446:59] + node _T_2467 = and(v[1], e[1].active.vcu) @[sequencer-master.scala 446:59] + node _T_2468 = and(v[2], e[2].active.vcu) @[sequencer-master.scala 446:59] + node _T_2469 = and(v[3], e[3].active.vcu) @[sequencer-master.scala 446:59] + node _T_2470 = and(v[4], e[4].active.vcu) @[sequencer-master.scala 446:59] + node _T_2471 = and(v[5], e[5].active.vcu) @[sequencer-master.scala 446:59] + node _T_2472 = and(v[6], e[6].active.vcu) @[sequencer-master.scala 446:59] + node _T_2473 = and(v[7], e[7].active.vcu) @[sequencer-master.scala 446:59] + node _T_2474 = or(_T_2466, _T_2467) @[sequencer-master.scala 447:39] + node _T_2475 = or(_T_2474, _T_2468) @[sequencer-master.scala 447:39] + node _T_2476 = or(_T_2475, _T_2469) @[sequencer-master.scala 447:39] + node _T_2477 = or(_T_2476, _T_2470) @[sequencer-master.scala 447:39] + node _T_2478 = or(_T_2477, _T_2471) @[sequencer-master.scala 447:39] + node _T_2479 = or(_T_2478, _T_2472) @[sequencer-master.scala 447:39] + node _T_2480 = or(_T_2479, _T_2473) @[sequencer-master.scala 447:39] + io.pending.mem <= _T_2480 @[sequencer-master.scala 447:22] + node _T_2481 = or(v[0], v[1]) @[sequencer-master.scala 448:36] + node _T_2482 = or(_T_2481, v[2]) @[sequencer-master.scala 448:36] + node _T_2483 = or(_T_2482, v[3]) @[sequencer-master.scala 448:36] + node _T_2484 = or(_T_2483, v[4]) @[sequencer-master.scala 448:36] + node _T_2485 = or(_T_2484, v[5]) @[sequencer-master.scala 448:36] + node _T_2486 = or(_T_2485, v[6]) @[sequencer-master.scala 448:36] + node _T_2487 = or(_T_2486, v[7]) @[sequencer-master.scala 448:36] + io.pending.all <= _T_2487 @[sequencer-master.scala 448:22] + node _T_2488 = or(e[0].active.vgu, e[0].active.vcu) @[sequencer-master.scala 452:25] + node _T_2489 = or(_T_2488, e[0].active.vlu) @[sequencer-master.scala 452:41] + node _T_2490 = or(_T_2489, e[0].active.vsu) @[sequencer-master.scala 452:57] + node _T_2491 = and(v[0], _T_2490) @[sequencer-master.scala 451:34] + node _T_2492 = or(e[1].active.vgu, e[1].active.vcu) @[sequencer-master.scala 452:25] + node _T_2493 = or(_T_2492, e[1].active.vlu) @[sequencer-master.scala 452:41] + node _T_2494 = or(_T_2493, e[1].active.vsu) @[sequencer-master.scala 452:57] + node _T_2495 = and(v[1], _T_2494) @[sequencer-master.scala 451:34] + node _T_2496 = or(e[2].active.vgu, e[2].active.vcu) @[sequencer-master.scala 452:25] + node _T_2497 = or(_T_2496, e[2].active.vlu) @[sequencer-master.scala 452:41] + node _T_2498 = or(_T_2497, e[2].active.vsu) @[sequencer-master.scala 452:57] + node _T_2499 = and(v[2], _T_2498) @[sequencer-master.scala 451:34] + node _T_2500 = or(e[3].active.vgu, e[3].active.vcu) @[sequencer-master.scala 452:25] + node _T_2501 = or(_T_2500, e[3].active.vlu) @[sequencer-master.scala 452:41] + node _T_2502 = or(_T_2501, e[3].active.vsu) @[sequencer-master.scala 452:57] + node _T_2503 = and(v[3], _T_2502) @[sequencer-master.scala 451:34] + node _T_2504 = or(e[4].active.vgu, e[4].active.vcu) @[sequencer-master.scala 452:25] + node _T_2505 = or(_T_2504, e[4].active.vlu) @[sequencer-master.scala 452:41] + node _T_2506 = or(_T_2505, e[4].active.vsu) @[sequencer-master.scala 452:57] + node _T_2507 = and(v[4], _T_2506) @[sequencer-master.scala 451:34] + node _T_2508 = or(e[5].active.vgu, e[5].active.vcu) @[sequencer-master.scala 452:25] + node _T_2509 = or(_T_2508, e[5].active.vlu) @[sequencer-master.scala 452:41] + node _T_2510 = or(_T_2509, e[5].active.vsu) @[sequencer-master.scala 452:57] + node _T_2511 = and(v[5], _T_2510) @[sequencer-master.scala 451:34] + node _T_2512 = or(e[6].active.vgu, e[6].active.vcu) @[sequencer-master.scala 452:25] + node _T_2513 = or(_T_2512, e[6].active.vlu) @[sequencer-master.scala 452:41] + node _T_2514 = or(_T_2513, e[6].active.vsu) @[sequencer-master.scala 452:57] + node _T_2515 = and(v[6], _T_2514) @[sequencer-master.scala 451:34] + node _T_2516 = or(e[7].active.vgu, e[7].active.vcu) @[sequencer-master.scala 452:25] + node _T_2517 = or(_T_2516, e[7].active.vlu) @[sequencer-master.scala 452:41] + node _T_2518 = or(_T_2517, e[7].active.vsu) @[sequencer-master.scala 452:57] + node _T_2519 = and(v[7], _T_2518) @[sequencer-master.scala 451:34] + node _T_2520 = add(_T_2491, _T_2495) @[Bitwise.scala 48:55] + node _T_2521 = add(_T_2499, _T_2503) @[Bitwise.scala 48:55] + node _T_2522 = add(_T_2520, _T_2521) @[Bitwise.scala 48:55] + node _T_2523 = add(_T_2507, _T_2511) @[Bitwise.scala 48:55] + node _T_2524 = add(_T_2515, _T_2519) @[Bitwise.scala 48:55] + node _T_2525 = add(_T_2523, _T_2524) @[Bitwise.scala 48:55] + node _T_2526 = add(_T_2522, _T_2525) @[Bitwise.scala 48:55] + io.counters.memoryUOps <= _T_2526 @[sequencer-master.scala 450:30] + node _T_2527 = or(e[0].active.viu, e[0].active.vimu) @[sequencer-master.scala 456:25] + node _T_2528 = or(_T_2527, e[0].active.vidu) @[sequencer-master.scala 456:42] + node _T_2529 = or(_T_2528, e[0].active.vfmu) @[sequencer-master.scala 456:59] + node _T_2530 = or(_T_2529, e[0].active.vfdu) @[sequencer-master.scala 457:25] + node _T_2531 = or(_T_2530, e[0].active.vfcu) @[sequencer-master.scala 457:42] + node _T_2532 = or(_T_2531, e[0].active.vfvu) @[sequencer-master.scala 457:59] + node _T_2533 = or(_T_2532, e[0].active.vqu) @[sequencer-master.scala 457:76] + node _T_2534 = and(v[0], _T_2533) @[sequencer-master.scala 455:34] + node _T_2535 = or(e[1].active.viu, e[1].active.vimu) @[sequencer-master.scala 456:25] + node _T_2536 = or(_T_2535, e[1].active.vidu) @[sequencer-master.scala 456:42] + node _T_2537 = or(_T_2536, e[1].active.vfmu) @[sequencer-master.scala 456:59] + node _T_2538 = or(_T_2537, e[1].active.vfdu) @[sequencer-master.scala 457:25] + node _T_2539 = or(_T_2538, e[1].active.vfcu) @[sequencer-master.scala 457:42] + node _T_2540 = or(_T_2539, e[1].active.vfvu) @[sequencer-master.scala 457:59] + node _T_2541 = or(_T_2540, e[1].active.vqu) @[sequencer-master.scala 457:76] + node _T_2542 = and(v[1], _T_2541) @[sequencer-master.scala 455:34] + node _T_2543 = or(e[2].active.viu, e[2].active.vimu) @[sequencer-master.scala 456:25] + node _T_2544 = or(_T_2543, e[2].active.vidu) @[sequencer-master.scala 456:42] + node _T_2545 = or(_T_2544, e[2].active.vfmu) @[sequencer-master.scala 456:59] + node _T_2546 = or(_T_2545, e[2].active.vfdu) @[sequencer-master.scala 457:25] + node _T_2547 = or(_T_2546, e[2].active.vfcu) @[sequencer-master.scala 457:42] + node _T_2548 = or(_T_2547, e[2].active.vfvu) @[sequencer-master.scala 457:59] + node _T_2549 = or(_T_2548, e[2].active.vqu) @[sequencer-master.scala 457:76] + node _T_2550 = and(v[2], _T_2549) @[sequencer-master.scala 455:34] + node _T_2551 = or(e[3].active.viu, e[3].active.vimu) @[sequencer-master.scala 456:25] + node _T_2552 = or(_T_2551, e[3].active.vidu) @[sequencer-master.scala 456:42] + node _T_2553 = or(_T_2552, e[3].active.vfmu) @[sequencer-master.scala 456:59] + node _T_2554 = or(_T_2553, e[3].active.vfdu) @[sequencer-master.scala 457:25] + node _T_2555 = or(_T_2554, e[3].active.vfcu) @[sequencer-master.scala 457:42] + node _T_2556 = or(_T_2555, e[3].active.vfvu) @[sequencer-master.scala 457:59] + node _T_2557 = or(_T_2556, e[3].active.vqu) @[sequencer-master.scala 457:76] + node _T_2558 = and(v[3], _T_2557) @[sequencer-master.scala 455:34] + node _T_2559 = or(e[4].active.viu, e[4].active.vimu) @[sequencer-master.scala 456:25] + node _T_2560 = or(_T_2559, e[4].active.vidu) @[sequencer-master.scala 456:42] + node _T_2561 = or(_T_2560, e[4].active.vfmu) @[sequencer-master.scala 456:59] + node _T_2562 = or(_T_2561, e[4].active.vfdu) @[sequencer-master.scala 457:25] + node _T_2563 = or(_T_2562, e[4].active.vfcu) @[sequencer-master.scala 457:42] + node _T_2564 = or(_T_2563, e[4].active.vfvu) @[sequencer-master.scala 457:59] + node _T_2565 = or(_T_2564, e[4].active.vqu) @[sequencer-master.scala 457:76] + node _T_2566 = and(v[4], _T_2565) @[sequencer-master.scala 455:34] + node _T_2567 = or(e[5].active.viu, e[5].active.vimu) @[sequencer-master.scala 456:25] + node _T_2568 = or(_T_2567, e[5].active.vidu) @[sequencer-master.scala 456:42] + node _T_2569 = or(_T_2568, e[5].active.vfmu) @[sequencer-master.scala 456:59] + node _T_2570 = or(_T_2569, e[5].active.vfdu) @[sequencer-master.scala 457:25] + node _T_2571 = or(_T_2570, e[5].active.vfcu) @[sequencer-master.scala 457:42] + node _T_2572 = or(_T_2571, e[5].active.vfvu) @[sequencer-master.scala 457:59] + node _T_2573 = or(_T_2572, e[5].active.vqu) @[sequencer-master.scala 457:76] + node _T_2574 = and(v[5], _T_2573) @[sequencer-master.scala 455:34] + node _T_2575 = or(e[6].active.viu, e[6].active.vimu) @[sequencer-master.scala 456:25] + node _T_2576 = or(_T_2575, e[6].active.vidu) @[sequencer-master.scala 456:42] + node _T_2577 = or(_T_2576, e[6].active.vfmu) @[sequencer-master.scala 456:59] + node _T_2578 = or(_T_2577, e[6].active.vfdu) @[sequencer-master.scala 457:25] + node _T_2579 = or(_T_2578, e[6].active.vfcu) @[sequencer-master.scala 457:42] + node _T_2580 = or(_T_2579, e[6].active.vfvu) @[sequencer-master.scala 457:59] + node _T_2581 = or(_T_2580, e[6].active.vqu) @[sequencer-master.scala 457:76] + node _T_2582 = and(v[6], _T_2581) @[sequencer-master.scala 455:34] + node _T_2583 = or(e[7].active.viu, e[7].active.vimu) @[sequencer-master.scala 456:25] + node _T_2584 = or(_T_2583, e[7].active.vidu) @[sequencer-master.scala 456:42] + node _T_2585 = or(_T_2584, e[7].active.vfmu) @[sequencer-master.scala 456:59] + node _T_2586 = or(_T_2585, e[7].active.vfdu) @[sequencer-master.scala 457:25] + node _T_2587 = or(_T_2586, e[7].active.vfcu) @[sequencer-master.scala 457:42] + node _T_2588 = or(_T_2587, e[7].active.vfvu) @[sequencer-master.scala 457:59] + node _T_2589 = or(_T_2588, e[7].active.vqu) @[sequencer-master.scala 457:76] + node _T_2590 = and(v[7], _T_2589) @[sequencer-master.scala 455:34] + node _T_2591 = add(_T_2534, _T_2542) @[Bitwise.scala 48:55] + node _T_2592 = add(_T_2550, _T_2558) @[Bitwise.scala 48:55] + node _T_2593 = add(_T_2591, _T_2592) @[Bitwise.scala 48:55] + node _T_2594 = add(_T_2566, _T_2574) @[Bitwise.scala 48:55] + node _T_2595 = add(_T_2582, _T_2590) @[Bitwise.scala 48:55] + node _T_2596 = add(_T_2594, _T_2595) @[Bitwise.scala 48:55] + node _T_2597 = add(_T_2593, _T_2596) @[Bitwise.scala 48:55] + io.counters.arithUOps <= _T_2597 @[sequencer-master.scala 454:29] + node _T_2598 = or(e[0].active.vpu, e[0].active.vipu) @[sequencer-master.scala 462:25] + node _T_2599 = and(v[0], _T_2598) @[sequencer-master.scala 461:34] + node _T_2600 = or(e[1].active.vpu, e[1].active.vipu) @[sequencer-master.scala 462:25] + node _T_2601 = and(v[1], _T_2600) @[sequencer-master.scala 461:34] + node _T_2602 = or(e[2].active.vpu, e[2].active.vipu) @[sequencer-master.scala 462:25] + node _T_2603 = and(v[2], _T_2602) @[sequencer-master.scala 461:34] + node _T_2604 = or(e[3].active.vpu, e[3].active.vipu) @[sequencer-master.scala 462:25] + node _T_2605 = and(v[3], _T_2604) @[sequencer-master.scala 461:34] + node _T_2606 = or(e[4].active.vpu, e[4].active.vipu) @[sequencer-master.scala 462:25] + node _T_2607 = and(v[4], _T_2606) @[sequencer-master.scala 461:34] + node _T_2608 = or(e[5].active.vpu, e[5].active.vipu) @[sequencer-master.scala 462:25] + node _T_2609 = and(v[5], _T_2608) @[sequencer-master.scala 461:34] + node _T_2610 = or(e[6].active.vpu, e[6].active.vipu) @[sequencer-master.scala 462:25] + node _T_2611 = and(v[6], _T_2610) @[sequencer-master.scala 461:34] + node _T_2612 = or(e[7].active.vpu, e[7].active.vipu) @[sequencer-master.scala 462:25] + node _T_2613 = and(v[7], _T_2612) @[sequencer-master.scala 461:34] + node _T_2614 = add(_T_2599, _T_2601) @[Bitwise.scala 48:55] + node _T_2615 = add(_T_2603, _T_2605) @[Bitwise.scala 48:55] + node _T_2616 = add(_T_2614, _T_2615) @[Bitwise.scala 48:55] + node _T_2617 = add(_T_2607, _T_2609) @[Bitwise.scala 48:55] + node _T_2618 = add(_T_2611, _T_2613) @[Bitwise.scala 48:55] + node _T_2619 = add(_T_2617, _T_2618) @[Bitwise.scala 48:55] + node _T_2620 = add(_T_2616, _T_2619) @[Bitwise.scala 48:55] + io.counters.predUOps <= _T_2620 @[sequencer-master.scala 460:28] + when _T_1[0] : @[sequencer-master.scala 203:31] + e[0].raw <- _T_2[0] @[sequencer-master.scala 204:20] + e[0].war <- _T_3[0] @[sequencer-master.scala 205:20] + e[0].waw <- _T_4[0] @[sequencer-master.scala 206:20] + skip @[sequencer-master.scala 203:31] + when _T_1[1] : @[sequencer-master.scala 203:31] + e[1].raw <- _T_2[1] @[sequencer-master.scala 204:20] + e[1].war <- _T_3[1] @[sequencer-master.scala 205:20] + e[1].waw <- _T_4[1] @[sequencer-master.scala 206:20] + skip @[sequencer-master.scala 203:31] + when _T_1[2] : @[sequencer-master.scala 203:31] + e[2].raw <- _T_2[2] @[sequencer-master.scala 204:20] + e[2].war <- _T_3[2] @[sequencer-master.scala 205:20] + e[2].waw <- _T_4[2] @[sequencer-master.scala 206:20] + skip @[sequencer-master.scala 203:31] + when _T_1[3] : @[sequencer-master.scala 203:31] + e[3].raw <- _T_2[3] @[sequencer-master.scala 204:20] + e[3].war <- _T_3[3] @[sequencer-master.scala 205:20] + e[3].waw <- _T_4[3] @[sequencer-master.scala 206:20] + skip @[sequencer-master.scala 203:31] + when _T_1[4] : @[sequencer-master.scala 203:31] + e[4].raw <- _T_2[4] @[sequencer-master.scala 204:20] + e[4].war <- _T_3[4] @[sequencer-master.scala 205:20] + e[4].waw <- _T_4[4] @[sequencer-master.scala 206:20] + skip @[sequencer-master.scala 203:31] + when _T_1[5] : @[sequencer-master.scala 203:31] + e[5].raw <- _T_2[5] @[sequencer-master.scala 204:20] + e[5].war <- _T_3[5] @[sequencer-master.scala 205:20] + e[5].waw <- _T_4[5] @[sequencer-master.scala 206:20] + skip @[sequencer-master.scala 203:31] + when _T_1[6] : @[sequencer-master.scala 203:31] + e[6].raw <- _T_2[6] @[sequencer-master.scala 204:20] + e[6].war <- _T_3[6] @[sequencer-master.scala 205:20] + e[6].waw <- _T_4[6] @[sequencer-master.scala 206:20] + skip @[sequencer-master.scala 203:31] + when _T_1[7] : @[sequencer-master.scala 203:31] + e[7].raw <- _T_2[7] @[sequencer-master.scala 204:20] + e[7].war <- _T_3[7] @[sequencer-master.scala 205:20] + e[7].waw <- _T_4[7] @[sequencer-master.scala 206:20] + skip @[sequencer-master.scala 203:31] + node _T_2621 = bits(reset, 0, 0) @[compatibility.scala 253:56] + when _T_2621 : @[sequencer-master.scala 468:20] + v[UInt<1>("h00")] <= UInt<1>("h00") @[sequencer-master.scala 372:35] + wire _T_2622 : {viu : UInt<1>, vipu : UInt<1>, vimu : UInt<1>, vidu : UInt<1>, vfmu : UInt<1>, vfdu : UInt<1>, vfcu : UInt<1>, vfvu : UInt<1>, vrpu : UInt<1>, vrfu : UInt<1>, vpu : UInt<1>, vgu : UInt<1>, vcu : UInt<1>, vlu : UInt<1>, vsu : UInt<1>, vqu : UInt<1>} @[sequencer-master.scala 373:76] + _T_2622 is invalid @[sequencer-master.scala 373:76] + wire _T_2623 : UInt<16> + _T_2623 is invalid + _T_2623 <= UInt<1>("h00") + node _T_2624 = bits(_T_2623, 0, 0) @[sequencer-master.scala 373:76] + _T_2622.vqu <= _T_2624 @[sequencer-master.scala 373:76] + node _T_2625 = bits(_T_2623, 1, 1) @[sequencer-master.scala 373:76] + _T_2622.vsu <= _T_2625 @[sequencer-master.scala 373:76] + node _T_2626 = bits(_T_2623, 2, 2) @[sequencer-master.scala 373:76] + _T_2622.vlu <= _T_2626 @[sequencer-master.scala 373:76] + node _T_2627 = bits(_T_2623, 3, 3) @[sequencer-master.scala 373:76] + _T_2622.vcu <= _T_2627 @[sequencer-master.scala 373:76] + node _T_2628 = bits(_T_2623, 4, 4) @[sequencer-master.scala 373:76] + _T_2622.vgu <= _T_2628 @[sequencer-master.scala 373:76] + node _T_2629 = bits(_T_2623, 5, 5) @[sequencer-master.scala 373:76] + _T_2622.vpu <= _T_2629 @[sequencer-master.scala 373:76] + node _T_2630 = bits(_T_2623, 6, 6) @[sequencer-master.scala 373:76] + _T_2622.vrfu <= _T_2630 @[sequencer-master.scala 373:76] + node _T_2631 = bits(_T_2623, 7, 7) @[sequencer-master.scala 373:76] + _T_2622.vrpu <= _T_2631 @[sequencer-master.scala 373:76] + node _T_2632 = bits(_T_2623, 8, 8) @[sequencer-master.scala 373:76] + _T_2622.vfvu <= _T_2632 @[sequencer-master.scala 373:76] + node _T_2633 = bits(_T_2623, 9, 9) @[sequencer-master.scala 373:76] + _T_2622.vfcu <= _T_2633 @[sequencer-master.scala 373:76] + node _T_2634 = bits(_T_2623, 10, 10) @[sequencer-master.scala 373:76] + _T_2622.vfdu <= _T_2634 @[sequencer-master.scala 373:76] + node _T_2635 = bits(_T_2623, 11, 11) @[sequencer-master.scala 373:76] + _T_2622.vfmu <= _T_2635 @[sequencer-master.scala 373:76] + node _T_2636 = bits(_T_2623, 12, 12) @[sequencer-master.scala 373:76] + _T_2622.vidu <= _T_2636 @[sequencer-master.scala 373:76] + node _T_2637 = bits(_T_2623, 13, 13) @[sequencer-master.scala 373:76] + _T_2622.vimu <= _T_2637 @[sequencer-master.scala 373:76] + node _T_2638 = bits(_T_2623, 14, 14) @[sequencer-master.scala 373:76] + _T_2622.vipu <= _T_2638 @[sequencer-master.scala 373:76] + node _T_2639 = bits(_T_2623, 15, 15) @[sequencer-master.scala 373:76] + _T_2622.viu <= _T_2639 @[sequencer-master.scala 373:76] + e[UInt<1>("h00")].active <- _T_2622 @[sequencer-master.scala 373:43] + v[UInt<1>("h01")] <= UInt<1>("h00") @[sequencer-master.scala 372:35] + wire _T_2640 : {viu : UInt<1>, vipu : UInt<1>, vimu : UInt<1>, vidu : UInt<1>, vfmu : UInt<1>, vfdu : UInt<1>, vfcu : UInt<1>, vfvu : UInt<1>, vrpu : UInt<1>, vrfu : UInt<1>, vpu : UInt<1>, vgu : UInt<1>, vcu : UInt<1>, vlu : UInt<1>, vsu : UInt<1>, vqu : UInt<1>} @[sequencer-master.scala 373:76] + _T_2640 is invalid @[sequencer-master.scala 373:76] + wire _T_2641 : UInt<16> + _T_2641 is invalid + _T_2641 <= UInt<1>("h00") + node _T_2642 = bits(_T_2641, 0, 0) @[sequencer-master.scala 373:76] + _T_2640.vqu <= _T_2642 @[sequencer-master.scala 373:76] + node _T_2643 = bits(_T_2641, 1, 1) @[sequencer-master.scala 373:76] + _T_2640.vsu <= _T_2643 @[sequencer-master.scala 373:76] + node _T_2644 = bits(_T_2641, 2, 2) @[sequencer-master.scala 373:76] + _T_2640.vlu <= _T_2644 @[sequencer-master.scala 373:76] + node _T_2645 = bits(_T_2641, 3, 3) @[sequencer-master.scala 373:76] + _T_2640.vcu <= _T_2645 @[sequencer-master.scala 373:76] + node _T_2646 = bits(_T_2641, 4, 4) @[sequencer-master.scala 373:76] + _T_2640.vgu <= _T_2646 @[sequencer-master.scala 373:76] + node _T_2647 = bits(_T_2641, 5, 5) @[sequencer-master.scala 373:76] + _T_2640.vpu <= _T_2647 @[sequencer-master.scala 373:76] + node _T_2648 = bits(_T_2641, 6, 6) @[sequencer-master.scala 373:76] + _T_2640.vrfu <= _T_2648 @[sequencer-master.scala 373:76] + node _T_2649 = bits(_T_2641, 7, 7) @[sequencer-master.scala 373:76] + _T_2640.vrpu <= _T_2649 @[sequencer-master.scala 373:76] + node _T_2650 = bits(_T_2641, 8, 8) @[sequencer-master.scala 373:76] + _T_2640.vfvu <= _T_2650 @[sequencer-master.scala 373:76] + node _T_2651 = bits(_T_2641, 9, 9) @[sequencer-master.scala 373:76] + _T_2640.vfcu <= _T_2651 @[sequencer-master.scala 373:76] + node _T_2652 = bits(_T_2641, 10, 10) @[sequencer-master.scala 373:76] + _T_2640.vfdu <= _T_2652 @[sequencer-master.scala 373:76] + node _T_2653 = bits(_T_2641, 11, 11) @[sequencer-master.scala 373:76] + _T_2640.vfmu <= _T_2653 @[sequencer-master.scala 373:76] + node _T_2654 = bits(_T_2641, 12, 12) @[sequencer-master.scala 373:76] + _T_2640.vidu <= _T_2654 @[sequencer-master.scala 373:76] + node _T_2655 = bits(_T_2641, 13, 13) @[sequencer-master.scala 373:76] + _T_2640.vimu <= _T_2655 @[sequencer-master.scala 373:76] + node _T_2656 = bits(_T_2641, 14, 14) @[sequencer-master.scala 373:76] + _T_2640.vipu <= _T_2656 @[sequencer-master.scala 373:76] + node _T_2657 = bits(_T_2641, 15, 15) @[sequencer-master.scala 373:76] + _T_2640.viu <= _T_2657 @[sequencer-master.scala 373:76] + e[UInt<1>("h01")].active <- _T_2640 @[sequencer-master.scala 373:43] + v[UInt<2>("h02")] <= UInt<1>("h00") @[sequencer-master.scala 372:35] + wire _T_2658 : {viu : UInt<1>, vipu : UInt<1>, vimu : UInt<1>, vidu : UInt<1>, vfmu : UInt<1>, vfdu : UInt<1>, vfcu : UInt<1>, vfvu : UInt<1>, vrpu : UInt<1>, vrfu : UInt<1>, vpu : UInt<1>, vgu : UInt<1>, vcu : UInt<1>, vlu : UInt<1>, vsu : UInt<1>, vqu : UInt<1>} @[sequencer-master.scala 373:76] + _T_2658 is invalid @[sequencer-master.scala 373:76] + wire _T_2659 : UInt<16> + _T_2659 is invalid + _T_2659 <= UInt<1>("h00") + node _T_2660 = bits(_T_2659, 0, 0) @[sequencer-master.scala 373:76] + _T_2658.vqu <= _T_2660 @[sequencer-master.scala 373:76] + node _T_2661 = bits(_T_2659, 1, 1) @[sequencer-master.scala 373:76] + _T_2658.vsu <= _T_2661 @[sequencer-master.scala 373:76] + node _T_2662 = bits(_T_2659, 2, 2) @[sequencer-master.scala 373:76] + _T_2658.vlu <= _T_2662 @[sequencer-master.scala 373:76] + node _T_2663 = bits(_T_2659, 3, 3) @[sequencer-master.scala 373:76] + _T_2658.vcu <= _T_2663 @[sequencer-master.scala 373:76] + node _T_2664 = bits(_T_2659, 4, 4) @[sequencer-master.scala 373:76] + _T_2658.vgu <= _T_2664 @[sequencer-master.scala 373:76] + node _T_2665 = bits(_T_2659, 5, 5) @[sequencer-master.scala 373:76] + _T_2658.vpu <= _T_2665 @[sequencer-master.scala 373:76] + node _T_2666 = bits(_T_2659, 6, 6) @[sequencer-master.scala 373:76] + _T_2658.vrfu <= _T_2666 @[sequencer-master.scala 373:76] + node _T_2667 = bits(_T_2659, 7, 7) @[sequencer-master.scala 373:76] + _T_2658.vrpu <= _T_2667 @[sequencer-master.scala 373:76] + node _T_2668 = bits(_T_2659, 8, 8) @[sequencer-master.scala 373:76] + _T_2658.vfvu <= _T_2668 @[sequencer-master.scala 373:76] + node _T_2669 = bits(_T_2659, 9, 9) @[sequencer-master.scala 373:76] + _T_2658.vfcu <= _T_2669 @[sequencer-master.scala 373:76] + node _T_2670 = bits(_T_2659, 10, 10) @[sequencer-master.scala 373:76] + _T_2658.vfdu <= _T_2670 @[sequencer-master.scala 373:76] + node _T_2671 = bits(_T_2659, 11, 11) @[sequencer-master.scala 373:76] + _T_2658.vfmu <= _T_2671 @[sequencer-master.scala 373:76] + node _T_2672 = bits(_T_2659, 12, 12) @[sequencer-master.scala 373:76] + _T_2658.vidu <= _T_2672 @[sequencer-master.scala 373:76] + node _T_2673 = bits(_T_2659, 13, 13) @[sequencer-master.scala 373:76] + _T_2658.vimu <= _T_2673 @[sequencer-master.scala 373:76] + node _T_2674 = bits(_T_2659, 14, 14) @[sequencer-master.scala 373:76] + _T_2658.vipu <= _T_2674 @[sequencer-master.scala 373:76] + node _T_2675 = bits(_T_2659, 15, 15) @[sequencer-master.scala 373:76] + _T_2658.viu <= _T_2675 @[sequencer-master.scala 373:76] + e[UInt<2>("h02")].active <- _T_2658 @[sequencer-master.scala 373:43] + v[UInt<2>("h03")] <= UInt<1>("h00") @[sequencer-master.scala 372:35] + wire _T_2676 : {viu : UInt<1>, vipu : UInt<1>, vimu : UInt<1>, vidu : UInt<1>, vfmu : UInt<1>, vfdu : UInt<1>, vfcu : UInt<1>, vfvu : UInt<1>, vrpu : UInt<1>, vrfu : UInt<1>, vpu : UInt<1>, vgu : UInt<1>, vcu : UInt<1>, vlu : UInt<1>, vsu : UInt<1>, vqu : UInt<1>} @[sequencer-master.scala 373:76] + _T_2676 is invalid @[sequencer-master.scala 373:76] + wire _T_2677 : UInt<16> + _T_2677 is invalid + _T_2677 <= UInt<1>("h00") + node _T_2678 = bits(_T_2677, 0, 0) @[sequencer-master.scala 373:76] + _T_2676.vqu <= _T_2678 @[sequencer-master.scala 373:76] + node _T_2679 = bits(_T_2677, 1, 1) @[sequencer-master.scala 373:76] + _T_2676.vsu <= _T_2679 @[sequencer-master.scala 373:76] + node _T_2680 = bits(_T_2677, 2, 2) @[sequencer-master.scala 373:76] + _T_2676.vlu <= _T_2680 @[sequencer-master.scala 373:76] + node _T_2681 = bits(_T_2677, 3, 3) @[sequencer-master.scala 373:76] + _T_2676.vcu <= _T_2681 @[sequencer-master.scala 373:76] + node _T_2682 = bits(_T_2677, 4, 4) @[sequencer-master.scala 373:76] + _T_2676.vgu <= _T_2682 @[sequencer-master.scala 373:76] + node _T_2683 = bits(_T_2677, 5, 5) @[sequencer-master.scala 373:76] + _T_2676.vpu <= _T_2683 @[sequencer-master.scala 373:76] + node _T_2684 = bits(_T_2677, 6, 6) @[sequencer-master.scala 373:76] + _T_2676.vrfu <= _T_2684 @[sequencer-master.scala 373:76] + node _T_2685 = bits(_T_2677, 7, 7) @[sequencer-master.scala 373:76] + _T_2676.vrpu <= _T_2685 @[sequencer-master.scala 373:76] + node _T_2686 = bits(_T_2677, 8, 8) @[sequencer-master.scala 373:76] + _T_2676.vfvu <= _T_2686 @[sequencer-master.scala 373:76] + node _T_2687 = bits(_T_2677, 9, 9) @[sequencer-master.scala 373:76] + _T_2676.vfcu <= _T_2687 @[sequencer-master.scala 373:76] + node _T_2688 = bits(_T_2677, 10, 10) @[sequencer-master.scala 373:76] + _T_2676.vfdu <= _T_2688 @[sequencer-master.scala 373:76] + node _T_2689 = bits(_T_2677, 11, 11) @[sequencer-master.scala 373:76] + _T_2676.vfmu <= _T_2689 @[sequencer-master.scala 373:76] + node _T_2690 = bits(_T_2677, 12, 12) @[sequencer-master.scala 373:76] + _T_2676.vidu <= _T_2690 @[sequencer-master.scala 373:76] + node _T_2691 = bits(_T_2677, 13, 13) @[sequencer-master.scala 373:76] + _T_2676.vimu <= _T_2691 @[sequencer-master.scala 373:76] + node _T_2692 = bits(_T_2677, 14, 14) @[sequencer-master.scala 373:76] + _T_2676.vipu <= _T_2692 @[sequencer-master.scala 373:76] + node _T_2693 = bits(_T_2677, 15, 15) @[sequencer-master.scala 373:76] + _T_2676.viu <= _T_2693 @[sequencer-master.scala 373:76] + e[UInt<2>("h03")].active <- _T_2676 @[sequencer-master.scala 373:43] + v[UInt<3>("h04")] <= UInt<1>("h00") @[sequencer-master.scala 372:35] + wire _T_2694 : {viu : UInt<1>, vipu : UInt<1>, vimu : UInt<1>, vidu : UInt<1>, vfmu : UInt<1>, vfdu : UInt<1>, vfcu : UInt<1>, vfvu : UInt<1>, vrpu : UInt<1>, vrfu : UInt<1>, vpu : UInt<1>, vgu : UInt<1>, vcu : UInt<1>, vlu : UInt<1>, vsu : UInt<1>, vqu : UInt<1>} @[sequencer-master.scala 373:76] + _T_2694 is invalid @[sequencer-master.scala 373:76] + wire _T_2695 : UInt<16> + _T_2695 is invalid + _T_2695 <= UInt<1>("h00") + node _T_2696 = bits(_T_2695, 0, 0) @[sequencer-master.scala 373:76] + _T_2694.vqu <= _T_2696 @[sequencer-master.scala 373:76] + node _T_2697 = bits(_T_2695, 1, 1) @[sequencer-master.scala 373:76] + _T_2694.vsu <= _T_2697 @[sequencer-master.scala 373:76] + node _T_2698 = bits(_T_2695, 2, 2) @[sequencer-master.scala 373:76] + _T_2694.vlu <= _T_2698 @[sequencer-master.scala 373:76] + node _T_2699 = bits(_T_2695, 3, 3) @[sequencer-master.scala 373:76] + _T_2694.vcu <= _T_2699 @[sequencer-master.scala 373:76] + node _T_2700 = bits(_T_2695, 4, 4) @[sequencer-master.scala 373:76] + _T_2694.vgu <= _T_2700 @[sequencer-master.scala 373:76] + node _T_2701 = bits(_T_2695, 5, 5) @[sequencer-master.scala 373:76] + _T_2694.vpu <= _T_2701 @[sequencer-master.scala 373:76] + node _T_2702 = bits(_T_2695, 6, 6) @[sequencer-master.scala 373:76] + _T_2694.vrfu <= _T_2702 @[sequencer-master.scala 373:76] + node _T_2703 = bits(_T_2695, 7, 7) @[sequencer-master.scala 373:76] + _T_2694.vrpu <= _T_2703 @[sequencer-master.scala 373:76] + node _T_2704 = bits(_T_2695, 8, 8) @[sequencer-master.scala 373:76] + _T_2694.vfvu <= _T_2704 @[sequencer-master.scala 373:76] + node _T_2705 = bits(_T_2695, 9, 9) @[sequencer-master.scala 373:76] + _T_2694.vfcu <= _T_2705 @[sequencer-master.scala 373:76] + node _T_2706 = bits(_T_2695, 10, 10) @[sequencer-master.scala 373:76] + _T_2694.vfdu <= _T_2706 @[sequencer-master.scala 373:76] + node _T_2707 = bits(_T_2695, 11, 11) @[sequencer-master.scala 373:76] + _T_2694.vfmu <= _T_2707 @[sequencer-master.scala 373:76] + node _T_2708 = bits(_T_2695, 12, 12) @[sequencer-master.scala 373:76] + _T_2694.vidu <= _T_2708 @[sequencer-master.scala 373:76] + node _T_2709 = bits(_T_2695, 13, 13) @[sequencer-master.scala 373:76] + _T_2694.vimu <= _T_2709 @[sequencer-master.scala 373:76] + node _T_2710 = bits(_T_2695, 14, 14) @[sequencer-master.scala 373:76] + _T_2694.vipu <= _T_2710 @[sequencer-master.scala 373:76] + node _T_2711 = bits(_T_2695, 15, 15) @[sequencer-master.scala 373:76] + _T_2694.viu <= _T_2711 @[sequencer-master.scala 373:76] + e[UInt<3>("h04")].active <- _T_2694 @[sequencer-master.scala 373:43] + v[UInt<3>("h05")] <= UInt<1>("h00") @[sequencer-master.scala 372:35] + wire _T_2712 : {viu : UInt<1>, vipu : UInt<1>, vimu : UInt<1>, vidu : UInt<1>, vfmu : UInt<1>, vfdu : UInt<1>, vfcu : UInt<1>, vfvu : UInt<1>, vrpu : UInt<1>, vrfu : UInt<1>, vpu : UInt<1>, vgu : UInt<1>, vcu : UInt<1>, vlu : UInt<1>, vsu : UInt<1>, vqu : UInt<1>} @[sequencer-master.scala 373:76] + _T_2712 is invalid @[sequencer-master.scala 373:76] + wire _T_2713 : UInt<16> + _T_2713 is invalid + _T_2713 <= UInt<1>("h00") + node _T_2714 = bits(_T_2713, 0, 0) @[sequencer-master.scala 373:76] + _T_2712.vqu <= _T_2714 @[sequencer-master.scala 373:76] + node _T_2715 = bits(_T_2713, 1, 1) @[sequencer-master.scala 373:76] + _T_2712.vsu <= _T_2715 @[sequencer-master.scala 373:76] + node _T_2716 = bits(_T_2713, 2, 2) @[sequencer-master.scala 373:76] + _T_2712.vlu <= _T_2716 @[sequencer-master.scala 373:76] + node _T_2717 = bits(_T_2713, 3, 3) @[sequencer-master.scala 373:76] + _T_2712.vcu <= _T_2717 @[sequencer-master.scala 373:76] + node _T_2718 = bits(_T_2713, 4, 4) @[sequencer-master.scala 373:76] + _T_2712.vgu <= _T_2718 @[sequencer-master.scala 373:76] + node _T_2719 = bits(_T_2713, 5, 5) @[sequencer-master.scala 373:76] + _T_2712.vpu <= _T_2719 @[sequencer-master.scala 373:76] + node _T_2720 = bits(_T_2713, 6, 6) @[sequencer-master.scala 373:76] + _T_2712.vrfu <= _T_2720 @[sequencer-master.scala 373:76] + node _T_2721 = bits(_T_2713, 7, 7) @[sequencer-master.scala 373:76] + _T_2712.vrpu <= _T_2721 @[sequencer-master.scala 373:76] + node _T_2722 = bits(_T_2713, 8, 8) @[sequencer-master.scala 373:76] + _T_2712.vfvu <= _T_2722 @[sequencer-master.scala 373:76] + node _T_2723 = bits(_T_2713, 9, 9) @[sequencer-master.scala 373:76] + _T_2712.vfcu <= _T_2723 @[sequencer-master.scala 373:76] + node _T_2724 = bits(_T_2713, 10, 10) @[sequencer-master.scala 373:76] + _T_2712.vfdu <= _T_2724 @[sequencer-master.scala 373:76] + node _T_2725 = bits(_T_2713, 11, 11) @[sequencer-master.scala 373:76] + _T_2712.vfmu <= _T_2725 @[sequencer-master.scala 373:76] + node _T_2726 = bits(_T_2713, 12, 12) @[sequencer-master.scala 373:76] + _T_2712.vidu <= _T_2726 @[sequencer-master.scala 373:76] + node _T_2727 = bits(_T_2713, 13, 13) @[sequencer-master.scala 373:76] + _T_2712.vimu <= _T_2727 @[sequencer-master.scala 373:76] + node _T_2728 = bits(_T_2713, 14, 14) @[sequencer-master.scala 373:76] + _T_2712.vipu <= _T_2728 @[sequencer-master.scala 373:76] + node _T_2729 = bits(_T_2713, 15, 15) @[sequencer-master.scala 373:76] + _T_2712.viu <= _T_2729 @[sequencer-master.scala 373:76] + e[UInt<3>("h05")].active <- _T_2712 @[sequencer-master.scala 373:43] + v[UInt<3>("h06")] <= UInt<1>("h00") @[sequencer-master.scala 372:35] + wire _T_2730 : {viu : UInt<1>, vipu : UInt<1>, vimu : UInt<1>, vidu : UInt<1>, vfmu : UInt<1>, vfdu : UInt<1>, vfcu : UInt<1>, vfvu : UInt<1>, vrpu : UInt<1>, vrfu : UInt<1>, vpu : UInt<1>, vgu : UInt<1>, vcu : UInt<1>, vlu : UInt<1>, vsu : UInt<1>, vqu : UInt<1>} @[sequencer-master.scala 373:76] + _T_2730 is invalid @[sequencer-master.scala 373:76] + wire _T_2731 : UInt<16> + _T_2731 is invalid + _T_2731 <= UInt<1>("h00") + node _T_2732 = bits(_T_2731, 0, 0) @[sequencer-master.scala 373:76] + _T_2730.vqu <= _T_2732 @[sequencer-master.scala 373:76] + node _T_2733 = bits(_T_2731, 1, 1) @[sequencer-master.scala 373:76] + _T_2730.vsu <= _T_2733 @[sequencer-master.scala 373:76] + node _T_2734 = bits(_T_2731, 2, 2) @[sequencer-master.scala 373:76] + _T_2730.vlu <= _T_2734 @[sequencer-master.scala 373:76] + node _T_2735 = bits(_T_2731, 3, 3) @[sequencer-master.scala 373:76] + _T_2730.vcu <= _T_2735 @[sequencer-master.scala 373:76] + node _T_2736 = bits(_T_2731, 4, 4) @[sequencer-master.scala 373:76] + _T_2730.vgu <= _T_2736 @[sequencer-master.scala 373:76] + node _T_2737 = bits(_T_2731, 5, 5) @[sequencer-master.scala 373:76] + _T_2730.vpu <= _T_2737 @[sequencer-master.scala 373:76] + node _T_2738 = bits(_T_2731, 6, 6) @[sequencer-master.scala 373:76] + _T_2730.vrfu <= _T_2738 @[sequencer-master.scala 373:76] + node _T_2739 = bits(_T_2731, 7, 7) @[sequencer-master.scala 373:76] + _T_2730.vrpu <= _T_2739 @[sequencer-master.scala 373:76] + node _T_2740 = bits(_T_2731, 8, 8) @[sequencer-master.scala 373:76] + _T_2730.vfvu <= _T_2740 @[sequencer-master.scala 373:76] + node _T_2741 = bits(_T_2731, 9, 9) @[sequencer-master.scala 373:76] + _T_2730.vfcu <= _T_2741 @[sequencer-master.scala 373:76] + node _T_2742 = bits(_T_2731, 10, 10) @[sequencer-master.scala 373:76] + _T_2730.vfdu <= _T_2742 @[sequencer-master.scala 373:76] + node _T_2743 = bits(_T_2731, 11, 11) @[sequencer-master.scala 373:76] + _T_2730.vfmu <= _T_2743 @[sequencer-master.scala 373:76] + node _T_2744 = bits(_T_2731, 12, 12) @[sequencer-master.scala 373:76] + _T_2730.vidu <= _T_2744 @[sequencer-master.scala 373:76] + node _T_2745 = bits(_T_2731, 13, 13) @[sequencer-master.scala 373:76] + _T_2730.vimu <= _T_2745 @[sequencer-master.scala 373:76] + node _T_2746 = bits(_T_2731, 14, 14) @[sequencer-master.scala 373:76] + _T_2730.vipu <= _T_2746 @[sequencer-master.scala 373:76] + node _T_2747 = bits(_T_2731, 15, 15) @[sequencer-master.scala 373:76] + _T_2730.viu <= _T_2747 @[sequencer-master.scala 373:76] + e[UInt<3>("h06")].active <- _T_2730 @[sequencer-master.scala 373:43] + v[UInt<3>("h07")] <= UInt<1>("h00") @[sequencer-master.scala 372:35] + wire _T_2748 : {viu : UInt<1>, vipu : UInt<1>, vimu : UInt<1>, vidu : UInt<1>, vfmu : UInt<1>, vfdu : UInt<1>, vfcu : UInt<1>, vfvu : UInt<1>, vrpu : UInt<1>, vrfu : UInt<1>, vpu : UInt<1>, vgu : UInt<1>, vcu : UInt<1>, vlu : UInt<1>, vsu : UInt<1>, vqu : UInt<1>} @[sequencer-master.scala 373:76] + _T_2748 is invalid @[sequencer-master.scala 373:76] + wire _T_2749 : UInt<16> + _T_2749 is invalid + _T_2749 <= UInt<1>("h00") + node _T_2750 = bits(_T_2749, 0, 0) @[sequencer-master.scala 373:76] + _T_2748.vqu <= _T_2750 @[sequencer-master.scala 373:76] + node _T_2751 = bits(_T_2749, 1, 1) @[sequencer-master.scala 373:76] + _T_2748.vsu <= _T_2751 @[sequencer-master.scala 373:76] + node _T_2752 = bits(_T_2749, 2, 2) @[sequencer-master.scala 373:76] + _T_2748.vlu <= _T_2752 @[sequencer-master.scala 373:76] + node _T_2753 = bits(_T_2749, 3, 3) @[sequencer-master.scala 373:76] + _T_2748.vcu <= _T_2753 @[sequencer-master.scala 373:76] + node _T_2754 = bits(_T_2749, 4, 4) @[sequencer-master.scala 373:76] + _T_2748.vgu <= _T_2754 @[sequencer-master.scala 373:76] + node _T_2755 = bits(_T_2749, 5, 5) @[sequencer-master.scala 373:76] + _T_2748.vpu <= _T_2755 @[sequencer-master.scala 373:76] + node _T_2756 = bits(_T_2749, 6, 6) @[sequencer-master.scala 373:76] + _T_2748.vrfu <= _T_2756 @[sequencer-master.scala 373:76] + node _T_2757 = bits(_T_2749, 7, 7) @[sequencer-master.scala 373:76] + _T_2748.vrpu <= _T_2757 @[sequencer-master.scala 373:76] + node _T_2758 = bits(_T_2749, 8, 8) @[sequencer-master.scala 373:76] + _T_2748.vfvu <= _T_2758 @[sequencer-master.scala 373:76] + node _T_2759 = bits(_T_2749, 9, 9) @[sequencer-master.scala 373:76] + _T_2748.vfcu <= _T_2759 @[sequencer-master.scala 373:76] + node _T_2760 = bits(_T_2749, 10, 10) @[sequencer-master.scala 373:76] + _T_2748.vfdu <= _T_2760 @[sequencer-master.scala 373:76] + node _T_2761 = bits(_T_2749, 11, 11) @[sequencer-master.scala 373:76] + _T_2748.vfmu <= _T_2761 @[sequencer-master.scala 373:76] + node _T_2762 = bits(_T_2749, 12, 12) @[sequencer-master.scala 373:76] + _T_2748.vidu <= _T_2762 @[sequencer-master.scala 373:76] + node _T_2763 = bits(_T_2749, 13, 13) @[sequencer-master.scala 373:76] + _T_2748.vimu <= _T_2763 @[sequencer-master.scala 373:76] + node _T_2764 = bits(_T_2749, 14, 14) @[sequencer-master.scala 373:76] + _T_2748.vipu <= _T_2764 @[sequencer-master.scala 373:76] + node _T_2765 = bits(_T_2749, 15, 15) @[sequencer-master.scala 373:76] + _T_2748.viu <= _T_2765 @[sequencer-master.scala 373:76] + e[UInt<3>("h07")].active <- _T_2748 @[sequencer-master.scala 373:43] + skip @[sequencer-master.scala 468:20] + io.debug.maybe_full <= maybe_full @[sequencer-master.scala 477:27] + io.debug.head <= head @[sequencer-master.scala 478:21] + io.debug.tail <= tail @[sequencer-master.scala 479:21] |