sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Collapse)	Author
2018-02-21	Change primop arg type (#587)	Adam Izraelevitz
	* Changed primops to not accept mixed-type args * Changed return type of sub of two uints to uint * Added negative tests * Removed rocket.fir. Manually changed RocketCore to not mix mul arg types. Added integration tests * Clarified test description and remove println * Fixed use of throwInternalError
2017-03-15	Use newer rocket regression spec without comb loop	Albert Magyar

2016-02-23	Add rocket regression, just runs rocket.fir through Verilog compiler and ↵	Jack
	compares to expected Verilog. Uses ScalaTest. Should be eventually replaced with actual simulation of rocket-chip
2016-02-09	CHIRRTL passes work, parser is updated	azidar

2016-01-28	Update rocket regression	Andrew Waterman

2016-01-23	Update rocket regression	Andrew Waterman

2016-01-16	WIP need to correctly output readwrite ports	azidar

2015-08-26	Added regression test	azidar