| Age | Commit message (Expand) | Author |
|---|
| 2016-01-16 | WIP getting through tests | azidar |
| 2016-01-16 | WIP | azidar |
| 2015-10-07 | Added Printf and Stop to firrtl. #23 #24. | azidar |
| 2015-08-31 | Updated spec | azidar |
| 2015-08-26 | Updated todo | azidar |
| 2015-08-24 | Removed old chisel3 tests that all failed for syntax reasons. Tests should no... | azidar |
| 2015-08-17 | Fixed bug where equality between expressions was incorrect, leading to | azidar |
| 2015-08-17 | Added tests for shl and mem. Fixed bug in verilog output of mem size. | azidar |
| 2015-08-03 | Fixed performance bug in Split Expressions. Changed delin for connect indexed... | azidar |
| 2015-07-31 | Added errors for bulk connects where field names match but types/flips don't | azidar |
| 2015-07-31 | Updated tests to pipe from stderr to stdout | azidar |
| 2015-07-30 | Added module name to error messages. | azidar |
| 2015-07-30 | Added eqv for bitwise equality, and change eq to be arithmetic equality | azidar |
| 2015-07-30 | Updated lots of tests so they pass. Found one bug in expand whens | azidar |
| 2015-07-29 | Finished supporting Chisel 2.0 Ref Chip | Adam Izraelevitz |
| 2015-07-21 | Merge branch 'new-low-firrtl' of github.com:ucb-bar/firrtl into new-low-firrtl | azidar |
| 2015-07-21 | Updated TODO | azidar |
| 2015-07-17 | Datapath compiles with Chisel 2.0 -> FIRRTL -> Verilog! | Adam Izraelevitz |
| 2015-07-14 | Added clock support | azidar |
| 2015-07-14 | Updated flo backend | azidar |
| 2015-07-06 | Updated todo | azidar |
| 2015-07-02 | Fixed performance bugs, runs 7x faster | azidar |
| 2015-07-01 | Updated TODO. | azidar |
| 2015-06-30 | Updated TODO. Ran spelling/grammar check on spec | azidar |
| 2015-06-22 | Updated spec to remove Register,WritePort,ReadPort,RdWrPort,biaccessors | azidar |
| 2015-06-12 | Added more changes to spec | azidar |
| 2015-06-12 | Major revisions to spec. Bumped to v0.1.2 | azidar |
| 2015-06-02 | Changed Core.fir so dshl wasn't huge. Fixed padding pass to preserve correct ... | azidar |
| 2015-06-02 | Added sequential/combinational memories. Started debugging verilog backend. A... | azidar |
| 2015-05-27 | Added external modules. Switched lower firrtl back to wire r; r := Register, ... | azidar |
| 2015-05-26 | Added <>. Added additional checks for primops. Added new chisel3 files. | azidar |
| 2015-05-18 | First pass at a Verilog Backend. Not tested, but compiles and generates reaso... | azidar |
| 2015-05-18 | Big API Change. Pad is no longer supported. Widths of primops can be flexible... | azidar |
| 2015-05-15 | Updated firrtl for its passes to be a bit more modular, and to enable pluggin... | azidar |
| 2015-05-13 | Added source indicators from FIRRTL files. Pass in -p i to get them printed. ... | azidar |
| 2015-05-13 | Updated Spec. Added scoped-reg which exposes on-reset bug. Fixed lowering bug | azidar |
| 2015-05-05 | Added a bunch of tests. In the middle of implementing check kinds and check t... | azidar |
| 2015-05-04 | Added new stanza | azidar |
| 2015-05-04 | Added a few more error checks. Not tested yet. Fixed bug in pad type inference | azidar |
| 2015-05-02 | Added a infrastructure for check passes, and wrote a few | azidar |
| 2015-05-01 | Fixed bug where the enable was looked at for lowering MUX. | azidar |
| 2015-04-29 | Made temp name generation counter, as well as the name, based off the eventua... | azidar |
| 2015-04-29 | Added dshl and dshr | azidar |
| 2015-04-28 | Updated todo | azidar |
| 2015-04-28 | Instances are now male. Reworked lowering pass to be sane. chisel3/ModuleVec.... | azidar |
| 2015-04-27 | Added on-reset | azidar |
| 2015-04-24 | Merged TODO | azidar |
| 2015-04-24 | Merge branch 'master' of github.com:ucb-bar/firrtl into parser | azidar |
| 2015-04-24 | Updated TODO. Added backwards with prop for as and bits | azidar |
| 2015-04-24 | Inflight | azidar |
