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2020-06-09Update Mergify to refer to travis-ci.com (#1672)Jack Koenig
2020-06-09Speed up ExpandWhens for very large designs (#1666)Jack Koenig
Use WrappedExpression instead of MemoizedHash. The benefit of memoizing the hash pales in comparison to the cost of hashing deeply nested Types in the AST. Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-06-04Add test case for retype-based component renaming in DedupModulesAlbert Magyar
2020-06-04Add unit test for Utils.expandRefAlbert Magyar
2020-06-04Make Utils.expandRef properly return intermediate expressionsAlbert Magyar
* Switch to more idiomatic flatMap for Utils.expandRef
2020-06-03Use recursive-then-iterative approach for check_width_eAlbert Magyar
* Avoid excessively deep recursion * Avoid overhead of DFS for shallow expression trees * Reduce work: skip expressions that cannot contain error-containing subtrees * Review feedback: added commentary to explain new check_widths_e structure
2020-06-03Generalize pattern of ResolveKindsBenchmarkAlbert Magyar
* Extend PassBenchmark to benchmark a particular Pass * Add license note to file
2020-06-03Revert: Generalize keyword collision to name manipulation, Add ↵Schuyler Eldridge
{Lower,Upper}CaseNames Transforms (#1651) * Revert "Add test of {Lower, Upper}CaseNames" This reverts commit 93c078b8469bc55cd2d33147c33e2b5421fda9d9. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Revert "Add --change-name-case <lower|upper> option" This reverts commit d3ab7e2db66fe3a63778f427dad6c08f64695ba5. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Revert "Add features.{LowerCaseNames, UpperCaseNames} transforms" This reverts commit c8dcdacf313f19a4d0238be694478a325432edd4. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Revert "Refactor RemoveKeywordCollisions->ManipulateNames" This reverts commit c534c5abae7b80a725ec9925569b3383b3c24a34. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-06-03Add mapString method to ir.Port (#1655)Schuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-06-03Scaladoc updates (#1656)Schuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-06-02Update tutorial to reflect IR/WIR forms being mergedAlbert Magyar
2020-06-02Add extra convenience factories for regular IR nodesAlbert Magyar
* This will help encourage use of these rather than WIR
2020-06-02Fix performance pathology in DedupModules (#1654)Jack Koenig
Fix a performance bug in DedupModules introduced in #1539. Stop recalculating the same expensive datastructures for each module, potentially multiple times. Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-06-02Bump SNAPSHOT version. (#1652)Jim Lawson
2020-05-28Implement InstanceTarget Behavior for Dedup + EliminateTargetPaths (#1539)Albert Chen
- RenameMap Behavior -- Prevent transitive renaming A -> B -> C (continueRenaming) -- Prevent transitive renaming for self-renames - Target -- Override toString as serialize for CompleteTarget -- Expansion of stripHierarchy to enable stripping InstanceTargets to become ModuleTargets Annotations -- Bugfix in extractComponents where Products were not iterated over -- Converts renamed targets to local targets using Target.referringModule to preserve sticky behavior - Eliminate Target Paths -- Make DuplicationHelper use LinkedHashMap, as we iterate over its contents and convert to Seq in def makePathless -- Add DupedResult to map original module to new module targets -- Update renaming to record a map from all relative instance paths to original module, to new module target -- Consumes DedupedResult to give better name to new duplicated module if it was originally deduplicated -- Reorder modules in attempt to preserve original ordering, pre-deduplication -- Move utility functions to object -- Bugfix: add self-renames to prevent ofModule _ of target _ cannot be renamed to Vector(_, _, _, ...) errors - Dedup -- Changed NoDedupAnnotation to contain ModuleTarget, rather than ModuleName -- Added DedupedResult to map original module to the duplicate module -- Consumes DupedResult to pick better name, if it existed -- Updates renaming to chain the following: instancify deduped modules, remap differently named internal signals, then remap AST modules -- Move utility functions to object -- Remove annotations as part of determination of dedup correctness -- Bugfix: add instance renames so that deduped modules have their instances properly renamed - Dead Code Elimination -- Add deletion of ASTModules - Tests -- Morphism Spec to ensure Dedup -> EliminateTargetPaths and EliminateTargetPaths -> Dedup patterns work properly -- Update existing tests to make sure they work properly -- Add Dedup tests to demonstrate instance renaming bug, EliminateTargetPaths for ofModule rename bug, and update RenameMap tests Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: Adam Izraelevitz <adam.izraelevitz@sifive.com> Co-authored-by: Adam Izraelevitz <azidar@gmail.com> Co-authored-by: Jack Koenig <koenig@sifive.com>
2020-05-26Make WrappedTransform work with --class-log-level (#1640)Schuyler Eldridge
Change WrappedTransforms to be sensitive to the --class-log-level of their true underlying transform. In effect, information logged in a wrapper (like timing information) will now print as expected. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-05-26Cleanup unused imports (no-warning docs req from CI)Albert Magyar
2020-05-26Remove trivially dead code from now-redundant WIR/IR match patternsAlbert Magyar
2020-05-26[API change] Absorb repetitive WIR nodes into IRAlbert Magyar
* Absorb WRef into Reference * Absorb WSubField into SubField * Absorb WSubIndex into SubIndex * Absorb WSubAccess into SubAccess * Absorb WDefInstance into DefInstance ------------------------- API CHANGE SEVERITY -------------------------- This is projected to not break source-level compatibility with any known user code. However, it will break *binary* compatibility with all existing user FIRRTL passes, as is generally allowed with major releases of FIRRTL. --------------------------- DESCRIPTION -------------------------------- Previously, there were several nodes in WIR.scala that had a one-to-one correspondance with existing nodes in the standard firrtl.ir hierarchy. These nodes would have a case class resembling the corresponding standard IR node, but with the addition of one or more "analysis" fields. Since these fields (such as kind) represent helpful info that can be invalidated or set to Unknown (e.g. UnknownKind for Kind), it does not cause any issues to simply include these fields on any in-memory representation of FIRRTL IR. Although other systems for tracking FIRRTL analyses have evolved over time, the ubiquity of pattern-matching on these fields has lead most core and custom transforms to be written against WIR, rather than IR. This PR unifies the IRs by adding the fields that would be in an "augmented" WIR node directly into the corresponding IR node; i.e., the "type" and "kind" fields from WRef are added directly to the definition of the Reference case class, while these "repetitive" WIR case classes are removed entirely. -------------------- SOURCE-COMPATIBILITY ADAPTERS --------------------- Several object methods are added to WIR.scala to maintain source-compatiblity for passes that used WIR. These objects define factory methods and unapply methods, so passes that relied on implicit case class factories or pattern matching for the removed WIR types will remain perfectly source-compatible. However, these do not guarantee compatibility at the binary level. The types of the removed WIR case classes are also added as type aliases to the top-level firrtl package, which allows code that relies on explicit constructor calls or reflection to retain source-compatibility. Finally, additional explicit factory methods are added to the companion objects of the newly-augmented IR case classes, which allows user code to avoid having to specify any of the new analysis fields. Existing code that created non-WIR IR nodes will be able to continue using the previous factory signatures, which will cause all omitted analysis fields to be set to Unknown. ---------------------- UNMITIGATED API CHANGES ------------------------- While passes that used WIR will be source-compatible with this change, there is one significant change that affects any pass currently using non-WIR IR: the signatures of pattern-matching cases for Reference, SubField, SubIndex, SubAccess, and DefInstance must change to accommodate the extra fields. This cannot be worked at the API level due to restrictions on unapply overloading, but it could theoretically be solved with macros or other static rewriting. However, only four core transforms (RemoveProto, ToWorkingIR, Dedup, and RemoveChirrtl) use non-WIR IR, and it is expected that no user code currently relies on it, so the expected migration strategy is simply to change the small fraction of code relying on these nodes.
2020-05-22Merge pull request #1639 from freechipsproject/improve-anno-loggingJack Koenig
Improve annotation logging
2020-05-22Do not throw NonFatal exceptions in annotation loggingJack Koenig
If an annotation cannot be serialized by json4s, we should not throw exceptions when doing trace-level logging.
2020-05-22DRY out transform running and annotation remappingJack Koenig
2020-05-21RenameMap: remove implicit rename chaining (#1591)Albert Chen
* RenameMap: remove implicit rename chaining * RenameMap: remove trailing comma Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-05-20Add scaladoc for LogicNode and tighten LowForm-only constraint (#1635)Albert Magyar
2020-05-18Don't try deduping the main module of a circuit (#1594)Albert Magyar
2020-05-18Fix equivalence tests (#853)Albert Chen
* - modify firrtlEquivalenceTest to use yosys equiv_simple/equiv_induct instead of miter - add RemoveValidIf pass to MinimumLowFirrtlOptimization * add EquivalenceTest to FirrtlSpec.scala, make classes in IntegrationSpec.scala abstract * change types of inputForm/outputForm to CircuitForm * change EquivalenceTest message * remove ICache equivalence tests * fix rebase errors * Add Ops scalatests to LEC suite * Only run compiler-path-comparison LEC tests on Ops design * Fixup issues with merge Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
2020-05-18Fix typo in spec description of 'tail' (#1626)Albert Magyar
* Closes #1597
2020-05-18Canonicalize init of regs with zero as reset in RemoveReset (#1627)Albert Magyar
* Fixes #1561 * Add test for zero-reset reg from #1561
2020-05-14Make find_port return Unit and use Foreachers in ResolveKindsAlbert Magyar
2020-05-14Eliminate unnecessary traversals in ResolveKindsJack Koenig
2020-05-14Use HashMap instead of LinkedHashMap in ResolveKindsJack Koenig
2020-05-14Add benchmark for ResolveKinds with hot JITJack Koenig
2020-05-14Move Reg/Mem initializations to end of module (#1613)Deborah Soung
* Move reg/mem initializations to end of module * Add comment before reg/mem init if inits exist
2020-05-13Merge pull request #1602 from freechipsproject/speed-up-dedupJack Koenig
Speed up Deduplication
2020-05-13Remove accidental hashing of all Modules in DedupJack Koenig
2020-05-13Remove expensive .distinct in DedupJack Koenig
2020-05-13Merge pull request #1601 from freechipsproject/speed-up-infer-typesJack Koenig
Speed up InferTypes and CInferTypes
2020-05-13Remove a redundant Expression traversal in InferTypesJack Koenig
2020-05-13Use HashMap instead of LinkedHashMap in InferTypesJack Koenig
Do the same in CInferTypes
2020-05-14Update json4s-native to 3.6.8 (#1607)Jim Lawson
Co-authored-by: Scala Steward <me@scala-steward.org> Co-authored-by: Scala Steward <43047562+scala-steward@users.noreply.github.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-05-13Update scalacheck-1-14 to 3.1.1.1 (#1606)Jim Lawson
Co-authored-by: Scala Steward <me@scala-steward.org> Co-authored-by: Scala Steward <43047562+scala-steward@users.noreply.github.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-05-13Merge pull request #1592 from ↵Schuyler Eldridge
freechipsproject/generalize-keyword-collision-to-name-manipulation Generalize keyword collision to name manipulation, Add {Lower,Upper}CaseNames Transforms
2020-05-13Add test of {Lower, Upper}CaseNamesSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-05-13Add --change-name-case <lower|upper> optionSchuyler Eldridge
Adds an options to the FIRRTL compiler command line to schedule the LowerCaseNames and UpperCaseNames transforms. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-05-13Add features.{LowerCaseNames, UpperCaseNames} transformsSchuyler Eldridge
Creates the features package and populates it with two new transforms: LowerCaseNames and UpperCaseNames. These transforms convert all names in a FIRRTL circuit to lower case or upper case. This is intended to help align generated Verilog with the policies of the company/institution using it. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> squash! Add LowerCaseNames and UpperCaseNames transforms
2020-05-13Refactor RemoveKeywordCollisions->ManipulateNamesSchuyler Eldridge
Generalize the operations of the RemoveKeywordCollisions transform into a new ManipulateNames transform. The ManipulateNames transform is an abstract transform for making conditional modifications to keywords/names in a FIRRTL circuit. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-05-13[Mergify] Add back backporting to 1.2.x (#1595)Jack Koenig
Labeling a PR with Milestone 1.2.X now will tell Mergify to backport it to both 1.2.x and 1.3.x. Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
2020-05-13Update scalatest to 3.1.2 (#1584)Scala Steward
Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu>
2020-05-13consolidated wire+assign to just wire, with expression inlined (#1600)Murali Vijayaraghavan
* consolidated wire <type> x; assign x = y; to wire <type> x = y; * Remove dead code from Emitter.scala Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
2020-05-11spec: Ran `aspell` on `spec.tex`. (#1564)Alberto Gonzalez
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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