Canonicalize init of regs with zero as reset in RemoveReset (#1627)

* Fixes #1561
* Add test for zero-reset reg from #1561

2 files changed, 24 insertions, 3 deletions

diff --git a/src/main/scala/firrtl/transforms/RemoveReset.scala b/src/main/scala/firrtl/transforms/RemoveReset.scala
index 530b12d9..2db93626 100644
--- a/src/main/scala/firrtl/transforms/RemoveReset.scala
+++ b/src/main/scala/firrtl/transforms/RemoveReset.scala
@@ -56,8 +56,9 @@ object RemoveReset extends Transform with DependencyAPIMigration {
         /* A register is initialized to an invalid expression */
         case reg @ DefRegister(_, _, _, _, _, init) if invalids.contains(we(init)) =>
           reg.copy(reset = Utils.zero, init = WRef(reg))
-        case reg @ DefRegister(_, rname, _, _, reset, init)
-            if reset != Utils.zero && reset.tpe != AsyncResetType =>
+        case reg @ DefRegister(_, rname, _, _, Utils.zero, _) =>
+          reg.copy(init = WRef(reg)) // canonicalize
+        case reg @ DefRegister(_, rname, _, _, reset, init) if reset.tpe != AsyncResetType =>
           // Add register reset to map
           resets(rname) = Reset(reset, init)
           reg.copy(reset = Utils.zero, init = WRef(reg))
diff --git a/src/test/scala/firrtlTests/transforms/RemoveResetSpec.scala b/src/test/scala/firrtlTests/transforms/RemoveResetSpec.scala
index 9b020b8e..299a4f48 100644
--- a/src/test/scala/firrtlTests/transforms/RemoveResetSpec.scala
+++ b/src/test/scala/firrtlTests/transforms/RemoveResetSpec.scala
@@ -8,7 +8,7 @@ import firrtl.testutils.FirrtlFlatSpec
 import firrtl.testutils.FirrtlCheckers._
 
 import firrtl.{CircuitState, WRef}
-import firrtl.ir.{Connect, Mux}
+import firrtl.ir.{Connect, Mux, DefRegister}
 import firrtl.stage.{FirrtlCircuitAnnotation, FirrtlSourceAnnotation, FirrtlStage}
 
 class RemoveResetSpec extends FirrtlFlatSpec with GivenWhenThen {
@@ -112,4 +112,24 @@ class RemoveResetSpec extends FirrtlFlatSpec with GivenWhenThen {
     outputState shouldNot containTree { case Connect(_, WRef("foo_b",_,_,_), Mux(_,_,_,_)) => true }
   }
 
+  it should "canvert a reset wired to UInt<0> to a canonical non-reset" in {
+    Given("foo's reset is connected to zero")
+    val input =
+      """|circuit Example :
+         |  module Example :
+         |    input clock : Clock
+         |    input rst : UInt<1>
+         |    input in : UInt<2>
+         |    output out : UInt<2>
+         |    reg foo : UInt<2>, clock with : (reset => (UInt(0), UInt(3)))
+         |    foo <= in
+         |    out <= foo""".stripMargin
+
+    val outputState = toLowFirrtl(input)
+
+    Then("foo has a canonical non-reset declaration after RemoveReset")
+    outputState should containTree { case DefRegister(_, "foo", _,_, firrtl.Utils.zero, WRef("foo", _,_,_)) => true }
+    And("foo is NOT connected to a reset mux")
+    outputState shouldNot containTree { case Connect(_, WRef("foo",_,_,_), Mux(_,_,_,_)) => true }
+  }
 }