aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorAlbert Magyar2020-04-04 19:05:25 -0700
committerAlbert Magyar2020-05-26 09:57:56 -0700
commit2fba1d304c4ae462aab00b71cd96efce4808178f (patch)
tree698dddf0fc42c84f259931039a3973711c2534ae
parent5d486688342297ab3230ce55b0ff65359627d44a (diff)
Cleanup unused imports (no-warning docs req from CI)
-rw-r--r--src/main/scala/firrtl/passes/ToWorkingIR.scala5
-rw-r--r--src/main/scala/tutorial/lesson2-working-ir/AnalyzeCircuit.scala4
2 files changed, 4 insertions, 5 deletions
diff --git a/src/main/scala/firrtl/passes/ToWorkingIR.scala b/src/main/scala/firrtl/passes/ToWorkingIR.scala
index 3f044e03..7da94be8 100644
--- a/src/main/scala/firrtl/passes/ToWorkingIR.scala
+++ b/src/main/scala/firrtl/passes/ToWorkingIR.scala
@@ -1,9 +1,8 @@
package firrtl.passes
import firrtl.ir._
-import firrtl.Mappers._
-import firrtl.options.{PreservesAll}
-import firrtl.{Transform, UnknownFlow, UnknownKind, WDefInstance, WRef, WSubAccess, WSubField, WSubIndex}
+import firrtl.options.PreservesAll
+import firrtl.Transform
object ToWorkingIR extends Pass with PreservesAll[Transform] {
override def prerequisites = firrtl.stage.Forms.MinimalHighForm
diff --git a/src/main/scala/tutorial/lesson2-working-ir/AnalyzeCircuit.scala b/src/main/scala/tutorial/lesson2-working-ir/AnalyzeCircuit.scala
index f7344fd2..8ca2b26b 100644
--- a/src/main/scala/tutorial/lesson2-working-ir/AnalyzeCircuit.scala
+++ b/src/main/scala/tutorial/lesson2-working-ir/AnalyzeCircuit.scala
@@ -4,9 +4,9 @@ package tutorial
package lesson2
// Compiler Infrastructure
-import firrtl.{Transform, LowForm, CircuitState, Utils}
+import firrtl.{Transform, LowForm, CircuitState}
// Firrtl IR classes
-import firrtl.ir.{DefModule, Statement, DefInstance, Expression, Mux}
+import firrtl.ir.{DefModule, Statement, Expression, Mux}
// Firrtl compiler's working IR classes (WIR)
import firrtl.WDefInstance
// Map functions