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2020-08-07ExpandWhens: VerificationStatements should be part of the simlist (#1829)Kevin Laeufer
2020-08-06Add deprecations for more firrtl.Compiler methods (#1791)Schuyler Eldridge
Adds missing deprecation warnings to firrtl.Compiler methods: compile and compileAndEmit. This provides a more informative message to the user about how to actually migrate. Without this, the user only has the generic deprecation warning about class Compiler. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-08-05ir: add UseSerializer mixin trait (#1824)Kevin Laeufer
Using the new trait to overwrite serialize at the leaf classes, we ensure that new, e.g., Expression nodes will not automatically try to call `Serializer.serialize` which would fail by default. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-08-05Deprecate InstanceGraph (#1800)Kevin Laeufer
* InstanceKeyGraph: add staticInstanceCount, getGraph and getChildrenInstanceMap * InstanceKeyGraph: reachableModules, unreachableModules, lowestCommonAncestor and fullHierarchy * Replace usage of InstanceGraph with InstanceKeyGraph Also deprecates all unused methods. * WiringUtils: make new version of sinksToSources package private This will make our live easier next time we need to change it. * CircuitGraph: use InstanceKeyGraph * InstanceKeyGraphSpec: respect maximum line width * InstanceKeyGraph: make constructor private * InstanceKeyGraph: move lowestCommonAncestor function to Wiring * WiringUtils: update deprecation message
2020-08-01Error on ExtModules w/ same defname, diff. ports (#1734)Schuyler Eldridge
* Use signed output in LargeParamExecutionTest Change the Verilog used in LargeParamExecutionTest to match its ExtModule specification. An ExtModule with an SInt port should map to a separate Verilog module with a signed port and this is disjoint from an ExtModule with a UInt port. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Error on ExtModules w/ same defname, diff. ports Adds a high form check to ensure that external modules that have the same defname also have exactly the same ports. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-07-31Fixed typo in fixed-point type parameter examples (#1816)Kevin Laeufer
Co-authored-by: chick <chick@qrhino.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-07-31Avoid repeated inlining in FlattenRegUpdate (#1727)Jack Koenig
* Avoid repeated inlining in FlattenRegUpdate When-else structure can lead to the same complex mux structure being the default on several branches in register update logic. When these are inlined, it can lead to artifical unreachable branches that show up as coverage holes in coverage of the emitted Verilog. This commit changes the inlining logic to prevent inlining any reference expression that shows up multiple times because this is a common indicator of the problematic case. * Add tests for improved register update logic emission * Improve FlattenRegUpdate comment and add more tests * [skip formal checks] ICache equivalence check verified locally
2020-07-31CircuitGraph: remove fields from public API (#1813)Kevin Laeufer
They are never used outside of the class not even in tests.
2020-07-31[WIP] Implement CircuitGraph and IRLookup to firrtl.analyses (#1603)Jiuyang Liu
* WIP Commit * Add EdgeDataDiGraph with views to amortize graph construction * WIP, got basic structure, need tests to pipeclean * First tests pass. Need more. * Tests pass, more need to be written * More tests pass! Things should work, except for memories * Added clearPrev to fix digraph uses where caching prev breaks * Removed old Component. Documented IRLookup * Added comments. Make prev arg to getEdges * WIP: Refactoring for CircuitGraph * Refactored into CircuitGraph. Can do topological module analysis * Removed old versions * Added support for memories * Added cached test * More stufffff * Added implicit caching of connectivity * Added tests for IRLookup, and others * Many major changes. Replaced CircuitGraph as ConnectionGraph Added CircuitGraph to be top-level user-facing object ConnectionGraph now automatically shortcuts getEdges ConnectionGraph overwrites BFS as PriorityBFS Added leafModule to Target Added lookup by kind to IRLookup Added more tests * Reordered stuff in ConnectionGraph * Made path work with deep hierarchies. Added PML for IllegalClockCrossings * Made pathsInDAG work with current shortcut semantics * Bugfix: check pathless targets when shortcutting paths * Added documentation/licenses * Removed UnnamedToken and related functionality * Added documentation of ConnectionGraph * Added back topo, needed for correct solving of intermediate modules * Bugfix. Cache intermediate clockSources from same BFS with same root, but not BFS with different root * Added literal/invalid clock source, and unknown top for getclocksource * Bugfix for clocks in bundles * Add CompleteTargetSerializer and test * remove ClockFinder, be able to compile. * test is able to compile, but need to fix. * public and abstract DiGraph, remove DiGraphLike. * revert some DiGraph code, ConnectionGraphSpec passed. * CircuitGraphSpec passed. * minimize diff between master * codes clean up * override linearize and revert DiGraph * keep DiGraph unchanged. * make ci happy again. * codes clean up. * bug fix for rebase * remove wir * make scaladoc happy again. * update for review. * add some documentation. * remove tag * wip IRLookup * code clean up and add some doucmentations. * IRLookup cache with ModuleTarget guarded. * make unidoc and 2.13 happy Co-authored-by: Adam Izraelevitz <azidar@gmail.com> Co-authored-by: Albert Magyar <albert.magyar@gmail.com> Co-authored-by: Jack Koenig <koenig@sifive.com>
2020-07-30ir: use Serializer.serialize where possible (#1809)Kevin Laeufer
* ir: use Serializer.serialize where possible * ir.Serializer: serialize MultiInfo correctly * ir.Serializer: empty body needs to result in a skip statement The firrtl grammar requires at least one statement. * ir.Serializer: correctly serialize fixed point types and literals * Serializer: change Seq -> Iterable in order to be Scala 2.13 compatible
2020-07-30Merge pull request #1796 from ekiwi-sifive/scala-2.13-supportJack Koenig
Scala 2.13 support
2020-07-29ManipulateNames: use composition instead of extending HashMapKevin Laeufer
2020-07-29[2.13] fix legacy procedure syntaxKevin Laeufer
2020-07-29Travis: try using openjdk8Kevin Laeufer
2020-07-29[2.13] use scala.collection.Seq instead of mutable.SeqKevin Laeufer
2020-07-29[2.13] update scalafix and reenable scalafixSemanticdbKevin Laeufer
0.9.16+ fixes https://github.com/scalacenter/scalafix/issues/1109 -Ywarn-unused-imports seems to be no longer supported by 2.13: https://github.com/scala/scala/releases/tag/v2.13.0
2020-07-29build.sbt: remove -Xsource optionKevin Laeufer
This should not be needed in firrtl.
2020-07-29PropagatePreset: use partition function to find other annotationsKevin Laeufer
2020-07-29[2.13] travis: add scala 2.13 to testsKevin Laeufer
2020-07-29[2.13] toSeq, Unit -> (), and postfix fixesKevin Laeufer
2020-07-29[2.13] Range.Double -> Range.BigDecimalKevin Laeufer
The values end up being converted to BigDecimal anyways.
2020-07-29[2.13] EmissionOptionMap now uses a HashMap instead of extending itKevin Laeufer
Extending HashMap is discouraged.
2020-07-29[2.13] replace `= Unit` with `= ()`Kevin Laeufer
2020-07-29Compiler: clarify package of DedupModulesKevin Laeufer
2020-07-29MemConf: build list of tuples and turn it into a map at the endKevin Laeufer
2020-07-29[2.13] convert toSeq and toMap where necessary to compileKevin Laeufer
2020-07-29[2.13] explicitly use a parallel vectorKevin Laeufer
2020-07-29[2.13] build.sbt: add scala 2.13 and remove semanticdb for nowKevin Laeufer
semanticdb seemed to be missing a 2.13 package
2020-07-29WiringTransform: fix non-determinism (#1799)Kevin Laeufer
* WiringUtils.sinksToSources: make sinkInsts order deterministic * WiringUtils: make owners a LinkedHashMap * Wiring: only make something a Wire if it isn't a port already Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-07-29RemoveWires: improve dependencies and declare ResolveKinds as an ↵Kevin Laeufer
invalidation (#1797) Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-07-29InferTypes: fix bugs with unknown widths on ports and memories (#1769)Kevin Laeufer
* InferTypesFlowsAndKindsSpec: test the results of InferTypes, ResolveKinds and ResolveFlows * Don't use passes sub-package in tests This changes two test files using the "passes" sub-package to "firrtl.passes". This allows a new "firrtlTests.passes" package to be freely created and used without a name collision. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * ResolveFlows: only depends on types and working ir The types are needed to know the orientation of a bundle field of a SubField node. * InferTypes: fix bugs with unknown widths on ports and memories * LoweringCompileSpec: Uniquify pass moved Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-07-29RenameMapSpec: try rename instance and port (#1776)Kevin Laeufer
* RenameMapSpec: try rename instance and port * RenameMapSpec: explicit chaining is required Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-07-28Fix incorrect error message (#1795)Andrew Waterman
dshl amount must be < 20 bits, not <= 20 bits. Resolves #1794
2020-07-27Merge pull request #1528 from freechipsproject/conditionally-scopesAlbert Magyar
Create new scopes for child statements of Conditionally
2020-07-27Fix out-of-scope reference in handwritten CHIRRTL mem testAlbert Magyar
2020-07-27Add adapter to make current CHIRRTL mport scoping legalAlbert Magyar
* See #1505 * Inferred mports are implicitly added to scope of their parent mem * This allows current chisel3 emission to work with new scope checks * This may change in a future refactor of CHIRRTL memory ports
2020-07-27Add Conditionally scoping tests to CheckSpecAlbert Magyar
* Add specific test for shadowing
2020-07-27Honor block scoping of Conditionally in CheckHighFormAlbert Magyar
* Fixes #1505
2020-07-27Update RightShiftTests.fir to avoid buggy Counter patternAlbert Magyar
* See freechipsproject/chisel3#1408
2020-07-27Add Treadle publishLocal to CI for Chisel3 Tests (#1793)Schuyler Eldridge
Add a Treadle build to the portion of CI that runs Chisel3 tests. Chisel3 needs to have a master copy of Treadle in order for it to work and cannot rely on resolution from Maven. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-07-25Integrate new transforms with firrtl.stage.Forms (#1754)Schuyler Eldridge
Move new transforms, recently added, into existing or new sets of transforms (defined in firrtl.stage.Forms). One transform is a mandatory low FIRRTL optimization: - firrtl.transforms.LegalizeAndReductionsTransform Previously, this was included as a prerequisite of all Verilog emitters (minimum, normal, and SystemVerilog). Two transforms associated with converting and removing the new verification statements are moved into a new set of transforms, AssertsRemoved: - firrtl.transforms.formal.ConvertAsserts - firrtl.transforms.formal.RemoveVerificationStatements Previously, these transforms were directly added as prerequisites to the minimum Verilog and normal Verilog emitter, but not the SystemVerilog emitter. The designation of inputForm=LowForm for legacy, custom transforms is updated to include assertion removal transforms as part of their optionalPrerequisites. This has the effect of continuing to cause inputForm=LowForm transforms to run as late as possible (right before the low FIRRTL, minimum Verilog, Verilog, or SystemVeriog emitter). Tests are updated to reflect the new order in both CustomTransformSpec and LoweringCompilersSpec. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-07-24Fix sign extension issue in Emitter (#1785)Albert Chen
* add sign-extend const-prop test * Emitter: don't wrap Neg operand in concat
2020-07-23fix reduction op bug ConstantPropagation (#1746)Albert Chen
* add const prop bitwise reduction equivalence test * mask negative literals when propagating reduction * change widths * get rid of unnecessary if * add BigInt mask utility
2020-07-23mask bits when propagating bitwise ops (#1745)Albert Chen
* ConstProp: test bitwise op of signed literals * ConstProp: use bit mask for FoldOr/FoldXor * handle and also * add UIntLiteral.masked helper Co-authored-by: Jack Koenig <koenig@sifive.com>
2020-07-23Update negative literal emission (#1782)Albert Chen
* test const prop of addition of negative literals * Emitter: handle minimum negative values correctly * update expected verilog in AsyncResetSpec
2020-07-20Make InferWidths thread safe (#1775)Schuyler Eldridge
Change the class-global, but private ConstraintSolver object inside InferWidths to instead be constructed on each execute invocation. This prevents issues with thread safety where running the same InferWidths object at the same time would cause the ConstraintSolver to get trampled on. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-07-18Faster dedup instance graph (#1732)Kevin Laeufer
* dedup: add faster InstanceGraph implementation and use it in dedup The new implementation takes care not to hash the instance types contained in DefInstance nodes. This should make dedup considerably faster. * FastInstanceGraph: cache vertices for faster findInstancesInHierarchy * FastInstanceGraph: remove the parent name field since it isn't actually necessary * FastInstanceGraph -> InstanceKeyGraph * InstanceGraph: describe performance problems. * InstanceKeyGraph: turn moduleMap into a def instead of a val This will make changing implementation details much easier in the future. * InstanceKeyGraph: return childInstances as Seq instead of Map This ensures a deterministic iteration order and it can easily be turned into a Map for O(1) accesses. * InstanceKeyGraph: add tests for public methods * InstanceKeyGraph: group public methods together * InstanceKeyGraphSpec: fix wording of a comment Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-07-17Cross-build unidoc in CI (#1772)Schuyler Eldridge
Add cross-building of unidoc to test issues if a user later does a +publishLocal (like with Chisel CI). Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-07-17Merge pull request #1771 from freechipsproject/fuzzer-2.11-fixesSchuyler Eldridge
Fix Fuzzer for 2.11
2020-07-17Fix Fuzzer for 2.11Schuyler Eldridge
This fixes two issues with the Fuzzer when running '+publishLocal': - Avoid foo(_) pattern due to weaker 2.11 type inference - Use seqAsJavaListConverter instead of seqAsJavaList (a 2.12 addition) Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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